1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 
34 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
35   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 
37 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
39   cl::desc("Disable Hexagon Addressing Mode Optimization"));
40 
41 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon CFG Optimization"));
44 
45 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
46   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
47 
48 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
49   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
50 
51 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
52   cl::init(true), cl::Hidden, cl::ZeroOrMore,
53   cl::desc("Early expansion of MUX"));
54 
55 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
56   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
57 
58 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
59   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
60 
61 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
62   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
63 
64 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
65   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
66 
67 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
68   cl::desc("Enable converting conditional transfers into MUX instructions"));
69 
70 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
71   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
72   "predicate instructions"));
73 
74 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
75   cl::init(false), cl::Hidden, cl::ZeroOrMore,
76   cl::desc("Enable loop data prefetch on Hexagon"));
77 
78 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
79   cl::desc("Disable splitting double registers"));
80 
81 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
82   cl::Hidden, cl::desc("Bit simplification"));
83 
84 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
85   cl::Hidden, cl::desc("Loop rescheduling"));
86 
87 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
88   cl::Hidden, cl::desc("Disable backend optimizations"));
89 
90 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
91   cl::Hidden, cl::ZeroOrMore, cl::init(false),
92   cl::desc("Enable Hexagon Vector print instr pass"));
93 
94 /// HexagonTargetMachineModule - Note that this is used on hosts that
95 /// cannot link in a library unless there are references into the
96 /// library.  In particular, it seems that it is not possible to get
97 /// things to work on Win32 without this.  Though it is unused, do not
98 /// remove it.
99 extern "C" int HexagonTargetMachineModule;
100 int HexagonTargetMachineModule = 0;
101 
102 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
103   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
104 }
105 
106 static MachineSchedRegistry
107 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
108                     createVLIWMachineSched);
109 
110 namespace llvm {
111   extern char &HexagonExpandCondsetsID;
112   void initializeHexagonExpandCondsetsPass(PassRegistry&);
113   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
114   void initializeHexagonGenMuxPass(PassRegistry&);
115   void initializeHexagonOptAddrModePass(PassRegistry&);
116   void initializeHexagonNewValueJumpPass(PassRegistry&);
117   Pass *createHexagonLoopIdiomPass();
118 
119   FunctionPass *createHexagonBitSimplify();
120   FunctionPass *createHexagonBranchRelaxation();
121   FunctionPass *createHexagonCallFrameInformation();
122   FunctionPass *createHexagonCFGOptimizer();
123   FunctionPass *createHexagonCommonGEP();
124   FunctionPass *createHexagonConstPropagationPass();
125   FunctionPass *createHexagonCopyToCombine();
126   FunctionPass *createHexagonEarlyIfConversion();
127   FunctionPass *createHexagonFixupHwLoops();
128   FunctionPass *createHexagonGenExtract();
129   FunctionPass *createHexagonGenInsert();
130   FunctionPass *createHexagonGenMux();
131   FunctionPass *createHexagonGenPredicate();
132   FunctionPass *createHexagonHardwareLoops();
133   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
134                                      CodeGenOpt::Level OptLevel);
135   FunctionPass *createHexagonLoopRescheduling();
136   FunctionPass *createHexagonNewValueJump();
137   FunctionPass *createHexagonOptimizeSZextends();
138   FunctionPass *createHexagonOptAddrMode();
139   FunctionPass *createHexagonPacketizer();
140   FunctionPass *createHexagonPeephole();
141   FunctionPass *createHexagonRDFOpt();
142   FunctionPass *createHexagonSplitConst32AndConst64();
143   FunctionPass *createHexagonSplitDoubleRegs();
144   FunctionPass *createHexagonStoreWidening();
145   FunctionPass *createHexagonVectorPrint();
146 } // end namespace llvm;
147 
148 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
149   if (!RM.hasValue())
150     return Reloc::Static;
151   return *RM;
152 }
153 
154 extern "C" void LLVMInitializeHexagonTarget() {
155   // Register the target.
156   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
157 
158   PassRegistry &PR = *PassRegistry::getPassRegistry();
159   initializeHexagonLoopIdiomRecognizePass(PR);
160   initializeHexagonGenMuxPass(PR);
161   initializeHexagonOptAddrModePass(PR);
162   initializeHexagonNewValueJumpPass(PR);
163 }
164 
165 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
166                                            StringRef CPU, StringRef FS,
167                                            const TargetOptions &Options,
168                                            Optional<Reloc::Model> RM,
169                                            CodeModel::Model CM,
170                                            CodeGenOpt::Level OL)
171     // Specify the vector alignment explicitly. For v512x1, the calculated
172     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
173     // the required minimum of 64 bytes.
174     : LLVMTargetMachine(
175           T, "e-m:e-p:32:32:32-a:0-n16:32-"
176              "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
177              "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
178           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
179           (HexagonNoOpt ? CodeGenOpt::None : OL)),
180       TLOF(make_unique<HexagonTargetObjectFile>()) {
181   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
182   initAsmInfo();
183 }
184 
185 const HexagonSubtarget *
186 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
187   AttributeList FnAttrs = F.getAttributes();
188   Attribute CPUAttr =
189       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
190   Attribute FSAttr =
191       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
192 
193   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
194                         ? CPUAttr.getValueAsString().str()
195                         : TargetCPU;
196   std::string FS = !FSAttr.hasAttribute(Attribute::None)
197                        ? FSAttr.getValueAsString().str()
198                        : TargetFS;
199 
200   auto &I = SubtargetMap[CPU + FS];
201   if (!I) {
202     // This needs to be done before we create a new subtarget since any
203     // creation will depend on the TM and the code generation flags on the
204     // function that reside in TargetOptions.
205     resetTargetOptions(F);
206     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
207   }
208   return I.get();
209 }
210 
211 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
212   PMB.addExtension(
213     PassManagerBuilder::EP_LateLoopOptimizations,
214     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
215       PM.add(createHexagonLoopIdiomPass());
216     });
217 }
218 
219 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
220   return TargetIRAnalysis([this](const Function &F) {
221     return TargetTransformInfo(HexagonTTIImpl(this, F));
222   });
223 }
224 
225 
226 HexagonTargetMachine::~HexagonTargetMachine() {}
227 
228 namespace {
229 /// Hexagon Code Generator Pass Configuration Options.
230 class HexagonPassConfig : public TargetPassConfig {
231 public:
232   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
233     : TargetPassConfig(TM, PM) {}
234 
235   HexagonTargetMachine &getHexagonTargetMachine() const {
236     return getTM<HexagonTargetMachine>();
237   }
238 
239   ScheduleDAGInstrs *
240   createMachineScheduler(MachineSchedContext *C) const override {
241     return createVLIWMachineSched(C);
242   }
243 
244   void addIRPasses() override;
245   bool addInstSelector() override;
246   void addPreRegAlloc() override;
247   void addPostRegAlloc() override;
248   void addPreSched2() override;
249   void addPreEmitPass() override;
250 };
251 } // namespace
252 
253 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
254   return new HexagonPassConfig(*this, PM);
255 }
256 
257 void HexagonPassConfig::addIRPasses() {
258   TargetPassConfig::addIRPasses();
259   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
260 
261   addPass(createAtomicExpandPass());
262   if (!NoOpt) {
263     if (EnableLoopPrefetch)
264       addPass(createLoopDataPrefetchPass());
265     if (EnableCommGEP)
266       addPass(createHexagonCommonGEP());
267     // Replace certain combinations of shifts and ands with extracts.
268     if (EnableGenExtract)
269       addPass(createHexagonGenExtract());
270   }
271 }
272 
273 bool HexagonPassConfig::addInstSelector() {
274   HexagonTargetMachine &TM = getHexagonTargetMachine();
275   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
276 
277   if (!NoOpt)
278     addPass(createHexagonOptimizeSZextends());
279 
280   addPass(createHexagonISelDag(TM, getOptLevel()));
281 
282   if (!NoOpt) {
283     // Create logical operations on predicate registers.
284     if (EnableGenPred)
285       addPass(createHexagonGenPredicate());
286     // Rotate loops to expose bit-simplification opportunities.
287     if (EnableLoopResched)
288       addPass(createHexagonLoopRescheduling());
289     // Split double registers.
290     if (!DisableHSDR)
291       addPass(createHexagonSplitDoubleRegs());
292     // Bit simplification.
293     if (EnableBitSimplify)
294       addPass(createHexagonBitSimplify());
295     addPass(createHexagonPeephole());
296     // Constant propagation.
297     if (!DisableHCP) {
298       addPass(createHexagonConstPropagationPass());
299       addPass(&UnreachableMachineBlockElimID);
300     }
301     if (EnableGenInsert)
302       addPass(createHexagonGenInsert());
303     if (EnableEarlyIf)
304       addPass(createHexagonEarlyIfConversion());
305   }
306 
307   return false;
308 }
309 
310 void HexagonPassConfig::addPreRegAlloc() {
311   if (getOptLevel() != CodeGenOpt::None) {
312     if (EnableExpandCondsets)
313       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
314     if (!DisableStoreWidening)
315       addPass(createHexagonStoreWidening());
316     if (!DisableHardwareLoops)
317       addPass(createHexagonHardwareLoops());
318   }
319   if (TM->getOptLevel() >= CodeGenOpt::Default)
320     addPass(&MachinePipelinerID);
321 }
322 
323 void HexagonPassConfig::addPostRegAlloc() {
324   if (getOptLevel() != CodeGenOpt::None) {
325     if (EnableRDFOpt)
326       addPass(createHexagonRDFOpt());
327     if (!DisableHexagonCFGOpt)
328       addPass(createHexagonCFGOptimizer());
329     if (!DisableAModeOpt)
330       addPass(createHexagonOptAddrMode());
331   }
332 }
333 
334 void HexagonPassConfig::addPreSched2() {
335   addPass(createHexagonCopyToCombine());
336   if (getOptLevel() != CodeGenOpt::None)
337     addPass(&IfConverterID);
338   addPass(createHexagonSplitConst32AndConst64());
339 }
340 
341 void HexagonPassConfig::addPreEmitPass() {
342   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
343 
344   if (!NoOpt)
345     addPass(createHexagonNewValueJump());
346 
347   addPass(createHexagonBranchRelaxation());
348 
349   // Create Packets.
350   if (!NoOpt) {
351     if (!DisableHardwareLoops)
352       addPass(createHexagonFixupHwLoops());
353     // Generate MUX from pairs of conditional transfers.
354     if (EnableGenMux)
355       addPass(createHexagonGenMux());
356 
357     addPass(createHexagonPacketizer(), false);
358   }
359   if (EnableVectorPrint)
360     addPass(createHexagonVectorPrint(), false);
361 
362   // Add CFI instructions if necessary.
363   addPass(createHexagonCallFrameInformation(), false);
364 }
365