1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineScheduler.h"
17 #include "HexagonTargetObjectFile.h"
18 #include "HexagonTargetTransformInfo.h"
19 #include "TargetInfo/HexagonTargetInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
33 
34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
35   cl::init(true), cl::desc("Enable RDF-based optimizations"));
36 
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
39 
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon Addressing Mode Optimization"));
43 
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon CFG Optimization"));
47 
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
50 
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
53 
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55   cl::init(true), cl::Hidden, cl::ZeroOrMore,
56   cl::desc("Early expansion of MUX"));
57 
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
60 
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
63 
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
66 
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
69 
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71   cl::desc("Enable converting conditional transfers into MUX instructions"));
72 
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75   "predicate instructions"));
76 
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78   cl::init(false), cl::Hidden, cl::ZeroOrMore,
79   cl::desc("Enable loop data prefetch on Hexagon"));
80 
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82   cl::desc("Disable splitting double registers"));
83 
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85   cl::Hidden, cl::desc("Bit simplification"));
86 
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88   cl::Hidden, cl::desc("Loop rescheduling"));
89 
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91   cl::Hidden, cl::desc("Disable backend optimizations"));
92 
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94   cl::Hidden, cl::ZeroOrMore, cl::init(false),
95   cl::desc("Enable Hexagon Vector print instr pass"));
96 
97 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
98   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
99 
100 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
101   cl::Hidden, cl::ZeroOrMore, cl::init(true),
102   cl::desc("Simplify the CFG after atomic expansion pass"));
103 
104 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
105                                         cl::ZeroOrMore, cl::init(true),
106                                         cl::desc("Enable instsimplify"));
107 
108 /// HexagonTargetMachineModule - Note that this is used on hosts that
109 /// cannot link in a library unless there are references into the
110 /// library.  In particular, it seems that it is not possible to get
111 /// things to work on Win32 without this.  Though it is unused, do not
112 /// remove it.
113 extern "C" int HexagonTargetMachineModule;
114 int HexagonTargetMachineModule = 0;
115 
116 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
117   ScheduleDAGMILive *DAG =
118     new VLIWMachineScheduler(C, std::make_unique<ConvergingVLIWScheduler>());
119   DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
120   DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
121   DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
122   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
123   return DAG;
124 }
125 
126 static MachineSchedRegistry
127 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
128                     createVLIWMachineSched);
129 
130 namespace llvm {
131   extern char &HexagonExpandCondsetsID;
132   void initializeHexagonBitSimplifyPass(PassRegistry&);
133   void initializeHexagonConstExtendersPass(PassRegistry&);
134   void initializeHexagonConstPropagationPass(PassRegistry&);
135   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
136   void initializeHexagonExpandCondsetsPass(PassRegistry&);
137   void initializeHexagonGenMuxPass(PassRegistry&);
138   void initializeHexagonHardwareLoopsPass(PassRegistry&);
139   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
140   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
141   void initializeHexagonNewValueJumpPass(PassRegistry&);
142   void initializeHexagonOptAddrModePass(PassRegistry&);
143   void initializeHexagonPacketizerPass(PassRegistry&);
144   void initializeHexagonRDFOptPass(PassRegistry&);
145   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
146   void initializeHexagonVExtractPass(PassRegistry&);
147   Pass *createHexagonLoopIdiomPass();
148   Pass *createHexagonVectorLoopCarriedReusePass();
149 
150   FunctionPass *createHexagonBitSimplify();
151   FunctionPass *createHexagonBranchRelaxation();
152   FunctionPass *createHexagonCallFrameInformation();
153   FunctionPass *createHexagonCFGOptimizer();
154   FunctionPass *createHexagonCommonGEP();
155   FunctionPass *createHexagonConstExtenders();
156   FunctionPass *createHexagonConstPropagationPass();
157   FunctionPass *createHexagonCopyToCombine();
158   FunctionPass *createHexagonEarlyIfConversion();
159   FunctionPass *createHexagonFixupHwLoops();
160   FunctionPass *createHexagonGenExtract();
161   FunctionPass *createHexagonGenInsert();
162   FunctionPass *createHexagonGenMux();
163   FunctionPass *createHexagonGenPredicate();
164   FunctionPass *createHexagonHardwareLoops();
165   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
166                                      CodeGenOpt::Level OptLevel);
167   FunctionPass *createHexagonLoopRescheduling();
168   FunctionPass *createHexagonNewValueJump();
169   FunctionPass *createHexagonOptimizeSZextends();
170   FunctionPass *createHexagonOptAddrMode();
171   FunctionPass *createHexagonPacketizer(bool Minimal);
172   FunctionPass *createHexagonPeephole();
173   FunctionPass *createHexagonRDFOpt();
174   FunctionPass *createHexagonSplitConst32AndConst64();
175   FunctionPass *createHexagonSplitDoubleRegs();
176   FunctionPass *createHexagonStoreWidening();
177   FunctionPass *createHexagonVectorPrint();
178   FunctionPass *createHexagonVExtract();
179 } // end namespace llvm;
180 
181 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
182   if (!RM.hasValue())
183     return Reloc::Static;
184   return *RM;
185 }
186 
187 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
188   // Register the target.
189   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
190 
191   PassRegistry &PR = *PassRegistry::getPassRegistry();
192   initializeHexagonBitSimplifyPass(PR);
193   initializeHexagonConstExtendersPass(PR);
194   initializeHexagonConstPropagationPass(PR);
195   initializeHexagonEarlyIfConversionPass(PR);
196   initializeHexagonGenMuxPass(PR);
197   initializeHexagonHardwareLoopsPass(PR);
198   initializeHexagonLoopIdiomRecognizePass(PR);
199   initializeHexagonVectorLoopCarriedReusePass(PR);
200   initializeHexagonNewValueJumpPass(PR);
201   initializeHexagonOptAddrModePass(PR);
202   initializeHexagonPacketizerPass(PR);
203   initializeHexagonRDFOptPass(PR);
204   initializeHexagonSplitDoubleRegsPass(PR);
205   initializeHexagonVExtractPass(PR);
206 }
207 
208 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
209                                            StringRef CPU, StringRef FS,
210                                            const TargetOptions &Options,
211                                            Optional<Reloc::Model> RM,
212                                            Optional<CodeModel::Model> CM,
213                                            CodeGenOpt::Level OL, bool JIT)
214     // Specify the vector alignment explicitly. For v512x1, the calculated
215     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
216     // the required minimum of 64 bytes.
217     : LLVMTargetMachine(
218           T,
219           "e-m:e-p:32:32:32-a:0-n16:32-"
220           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
221           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
222           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
223           getEffectiveCodeModel(CM, CodeModel::Small),
224           (HexagonNoOpt ? CodeGenOpt::None : OL)),
225       TLOF(std::make_unique<HexagonTargetObjectFile>()) {
226   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
227   initAsmInfo();
228 }
229 
230 const HexagonSubtarget *
231 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
232   AttributeList FnAttrs = F.getAttributes();
233   Attribute CPUAttr =
234       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
235   Attribute FSAttr =
236       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
237 
238   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
239                         ? CPUAttr.getValueAsString().str()
240                         : TargetCPU;
241   std::string FS = !FSAttr.hasAttribute(Attribute::None)
242                        ? FSAttr.getValueAsString().str()
243                        : TargetFS;
244   // Append the preexisting target features last, so that +mattr overrides
245   // the "unsafe-fp-math" function attribute.
246   // Creating a separate target feature is not strictly necessary, it only
247   // exists to make "unsafe-fp-math" force creating a new subtarget.
248 
249   if (FnAttrs.hasFnAttribute("unsafe-fp-math") &&
250       F.getFnAttribute("unsafe-fp-math").getValueAsString() == "true")
251     FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
252 
253   auto &I = SubtargetMap[CPU + FS];
254   if (!I) {
255     // This needs to be done before we create a new subtarget since any
256     // creation will depend on the TM and the code generation flags on the
257     // function that reside in TargetOptions.
258     resetTargetOptions(F);
259     I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
260   }
261   return I.get();
262 }
263 
264 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
265   PMB.addExtension(
266     PassManagerBuilder::EP_LateLoopOptimizations,
267     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
268       PM.add(createHexagonLoopIdiomPass());
269     });
270   PMB.addExtension(
271     PassManagerBuilder::EP_LoopOptimizerEnd,
272     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
273       PM.add(createHexagonVectorLoopCarriedReusePass());
274     });
275 }
276 
277 TargetTransformInfo
278 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
279   return TargetTransformInfo(HexagonTTIImpl(this, F));
280 }
281 
282 
283 HexagonTargetMachine::~HexagonTargetMachine() {}
284 
285 namespace {
286 /// Hexagon Code Generator Pass Configuration Options.
287 class HexagonPassConfig : public TargetPassConfig {
288 public:
289   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
290     : TargetPassConfig(TM, PM) {}
291 
292   HexagonTargetMachine &getHexagonTargetMachine() const {
293     return getTM<HexagonTargetMachine>();
294   }
295 
296   ScheduleDAGInstrs *
297   createMachineScheduler(MachineSchedContext *C) const override {
298     return createVLIWMachineSched(C);
299   }
300 
301   void addIRPasses() override;
302   bool addInstSelector() override;
303   void addPreRegAlloc() override;
304   void addPostRegAlloc() override;
305   void addPreSched2() override;
306   void addPreEmitPass() override;
307 };
308 } // namespace
309 
310 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
311   return new HexagonPassConfig(*this, PM);
312 }
313 
314 void HexagonPassConfig::addIRPasses() {
315   TargetPassConfig::addIRPasses();
316   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
317 
318   if (!NoOpt) {
319     if (EnableInstSimplify)
320       addPass(createInstSimplifyLegacyPass());
321     addPass(createDeadCodeEliminationPass());
322   }
323 
324   addPass(createAtomicExpandPass());
325 
326   if (!NoOpt) {
327     if (EnableInitialCFGCleanup)
328       addPass(createCFGSimplificationPass(SimplifyCFGOptions()
329                                               .forwardSwitchCondToPhi(true)
330                                               .convertSwitchToLookupTable(true)
331                                               .needCanonicalLoops(false)
332                                               .hoistCommonInsts(true)
333                                               .sinkCommonInsts(true)));
334     if (EnableLoopPrefetch)
335       addPass(createLoopDataPrefetchPass());
336     if (EnableCommGEP)
337       addPass(createHexagonCommonGEP());
338     // Replace certain combinations of shifts and ands with extracts.
339     if (EnableGenExtract)
340       addPass(createHexagonGenExtract());
341   }
342 }
343 
344 bool HexagonPassConfig::addInstSelector() {
345   HexagonTargetMachine &TM = getHexagonTargetMachine();
346   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
347 
348   if (!NoOpt)
349     addPass(createHexagonOptimizeSZextends());
350 
351   addPass(createHexagonISelDag(TM, getOptLevel()));
352 
353   if (!NoOpt) {
354     if (EnableVExtractOpt)
355       addPass(createHexagonVExtract());
356     // Create logical operations on predicate registers.
357     if (EnableGenPred)
358       addPass(createHexagonGenPredicate());
359     // Rotate loops to expose bit-simplification opportunities.
360     if (EnableLoopResched)
361       addPass(createHexagonLoopRescheduling());
362     // Split double registers.
363     if (!DisableHSDR)
364       addPass(createHexagonSplitDoubleRegs());
365     // Bit simplification.
366     if (EnableBitSimplify)
367       addPass(createHexagonBitSimplify());
368     addPass(createHexagonPeephole());
369     // Constant propagation.
370     if (!DisableHCP) {
371       addPass(createHexagonConstPropagationPass());
372       addPass(&UnreachableMachineBlockElimID);
373     }
374     if (EnableGenInsert)
375       addPass(createHexagonGenInsert());
376     if (EnableEarlyIf)
377       addPass(createHexagonEarlyIfConversion());
378   }
379 
380   return false;
381 }
382 
383 void HexagonPassConfig::addPreRegAlloc() {
384   if (getOptLevel() != CodeGenOpt::None) {
385     if (EnableCExtOpt)
386       addPass(createHexagonConstExtenders());
387     if (EnableExpandCondsets)
388       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
389     if (!DisableStoreWidening)
390       addPass(createHexagonStoreWidening());
391     if (!DisableHardwareLoops)
392       addPass(createHexagonHardwareLoops());
393   }
394   if (TM->getOptLevel() >= CodeGenOpt::Default)
395     addPass(&MachinePipelinerID);
396 }
397 
398 void HexagonPassConfig::addPostRegAlloc() {
399   if (getOptLevel() != CodeGenOpt::None) {
400     if (EnableRDFOpt)
401       addPass(createHexagonRDFOpt());
402     if (!DisableHexagonCFGOpt)
403       addPass(createHexagonCFGOptimizer());
404     if (!DisableAModeOpt)
405       addPass(createHexagonOptAddrMode());
406   }
407 }
408 
409 void HexagonPassConfig::addPreSched2() {
410   addPass(createHexagonCopyToCombine());
411   if (getOptLevel() != CodeGenOpt::None)
412     addPass(&IfConverterID);
413   addPass(createHexagonSplitConst32AndConst64());
414 }
415 
416 void HexagonPassConfig::addPreEmitPass() {
417   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
418 
419   if (!NoOpt)
420     addPass(createHexagonNewValueJump());
421 
422   addPass(createHexagonBranchRelaxation());
423 
424   if (!NoOpt) {
425     if (!DisableHardwareLoops)
426       addPass(createHexagonFixupHwLoops());
427     // Generate MUX from pairs of conditional transfers.
428     if (EnableGenMux)
429       addPass(createHexagonGenMux());
430   }
431 
432   // Packetization is mandatory: it handles gather/scatter at all opt levels.
433   addPass(createHexagonPacketizer(NoOpt), false);
434 
435   if (EnableVectorPrint)
436     addPass(createHexagonVectorPrint(), false);
437 
438   // Add CFI instructions if necessary.
439   addPass(createHexagonCallFrameInformation(), false);
440 }
441