1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/Scalar.h"
27 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 
34 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
35   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 
37 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
39   cl::desc("Disable Hexagon Addressing Mode Optimization"));
40 
41 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon CFG Optimization"));
44 
45 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
46   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
47 
48 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
49   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
50 
51 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
52   cl::init(true), cl::Hidden, cl::ZeroOrMore,
53   cl::desc("Early expansion of MUX"));
54 
55 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
56   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
57 
58 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
59   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
60 
61 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
62   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
63 
64 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
65   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
66 
67 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
68   cl::desc("Enable converting conditional transfers into MUX instructions"));
69 
70 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
71   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
72   "predicate instructions"));
73 
74 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
75   cl::init(false), cl::Hidden, cl::ZeroOrMore,
76   cl::desc("Enable loop data prefetch on Hexagon"));
77 
78 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
79   cl::desc("Disable splitting double registers"));
80 
81 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
82   cl::Hidden, cl::desc("Bit simplification"));
83 
84 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
85   cl::Hidden, cl::desc("Loop rescheduling"));
86 
87 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
88   cl::Hidden, cl::desc("Disable backend optimizations"));
89 
90 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
91   cl::Hidden, cl::ZeroOrMore, cl::init(false),
92   cl::desc("Enable Hexagon Vector print instr pass"));
93 
94 /// HexagonTargetMachineModule - Note that this is used on hosts that
95 /// cannot link in a library unless there are references into the
96 /// library.  In particular, it seems that it is not possible to get
97 /// things to work on Win32 without this.  Though it is unused, do not
98 /// remove it.
99 extern "C" int HexagonTargetMachineModule;
100 int HexagonTargetMachineModule = 0;
101 
102 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
103   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
104 }
105 
106 static MachineSchedRegistry
107 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
108                     createVLIWMachineSched);
109 
110 namespace llvm {
111   extern char &HexagonExpandCondsetsID;
112   void initializeHexagonExpandCondsetsPass(PassRegistry&);
113   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
114   void initializeHexagonOptAddrModePass(PassRegistry&);
115   Pass *createHexagonLoopIdiomPass();
116 
117   FunctionPass *createHexagonBitSimplify();
118   FunctionPass *createHexagonBranchRelaxation();
119   FunctionPass *createHexagonCallFrameInformation();
120   FunctionPass *createHexagonCFGOptimizer();
121   FunctionPass *createHexagonCommonGEP();
122   FunctionPass *createHexagonConstPropagationPass();
123   FunctionPass *createHexagonCopyToCombine();
124   FunctionPass *createHexagonEarlyIfConversion();
125   FunctionPass *createHexagonFixupHwLoops();
126   FunctionPass *createHexagonGenExtract();
127   FunctionPass *createHexagonGenInsert();
128   FunctionPass *createHexagonGenMux();
129   FunctionPass *createHexagonGenPredicate();
130   FunctionPass *createHexagonHardwareLoops();
131   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
132                                      CodeGenOpt::Level OptLevel);
133   FunctionPass *createHexagonLoopRescheduling();
134   FunctionPass *createHexagonNewValueJump();
135   FunctionPass *createHexagonOptimizeSZextends();
136   FunctionPass *createHexagonOptAddrMode();
137   FunctionPass *createHexagonPacketizer();
138   FunctionPass *createHexagonPeephole();
139   FunctionPass *createHexagonRDFOpt();
140   FunctionPass *createHexagonSplitConst32AndConst64();
141   FunctionPass *createHexagonSplitDoubleRegs();
142   FunctionPass *createHexagonStoreWidening();
143   FunctionPass *createHexagonVectorPrint();
144 } // end namespace llvm;
145 
146 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
147   if (!RM.hasValue())
148     return Reloc::Static;
149   return *RM;
150 }
151 
152 extern "C" void LLVMInitializeHexagonTarget() {
153   // Register the target.
154   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
155   initializeHexagonLoopIdiomRecognizePass(*PassRegistry::getPassRegistry());
156   initializeHexagonOptAddrModePass(*PassRegistry::getPassRegistry());
157 }
158 
159 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
160                                            StringRef CPU, StringRef FS,
161                                            const TargetOptions &Options,
162                                            Optional<Reloc::Model> RM,
163                                            CodeModel::Model CM,
164                                            CodeGenOpt::Level OL)
165     // Specify the vector alignment explicitly. For v512x1, the calculated
166     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
167     // the required minimum of 64 bytes.
168     : LLVMTargetMachine(
169           T, "e-m:e-p:32:32:32-a:0-n16:32-"
170              "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
171              "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
172           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
173           (HexagonNoOpt ? CodeGenOpt::None : OL)),
174       TLOF(make_unique<HexagonTargetObjectFile>()) {
175   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
176   initAsmInfo();
177 }
178 
179 const HexagonSubtarget *
180 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
181   AttributeList FnAttrs = F.getAttributes();
182   Attribute CPUAttr =
183       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
184   Attribute FSAttr =
185       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
186 
187   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
188                         ? CPUAttr.getValueAsString().str()
189                         : TargetCPU;
190   std::string FS = !FSAttr.hasAttribute(Attribute::None)
191                        ? FSAttr.getValueAsString().str()
192                        : TargetFS;
193 
194   auto &I = SubtargetMap[CPU + FS];
195   if (!I) {
196     // This needs to be done before we create a new subtarget since any
197     // creation will depend on the TM and the code generation flags on the
198     // function that reside in TargetOptions.
199     resetTargetOptions(F);
200     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
201   }
202   return I.get();
203 }
204 
205 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
206   PMB.addExtension(
207     PassManagerBuilder::EP_LateLoopOptimizations,
208     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
209       PM.add(createHexagonLoopIdiomPass());
210     });
211 }
212 
213 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
214   return TargetIRAnalysis([this](const Function &F) {
215     return TargetTransformInfo(HexagonTTIImpl(this, F));
216   });
217 }
218 
219 
220 HexagonTargetMachine::~HexagonTargetMachine() {}
221 
222 namespace {
223 /// Hexagon Code Generator Pass Configuration Options.
224 class HexagonPassConfig : public TargetPassConfig {
225 public:
226   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
227     : TargetPassConfig(TM, PM) {}
228 
229   HexagonTargetMachine &getHexagonTargetMachine() const {
230     return getTM<HexagonTargetMachine>();
231   }
232 
233   ScheduleDAGInstrs *
234   createMachineScheduler(MachineSchedContext *C) const override {
235     return createVLIWMachineSched(C);
236   }
237 
238   void addIRPasses() override;
239   bool addInstSelector() override;
240   void addPreRegAlloc() override;
241   void addPostRegAlloc() override;
242   void addPreSched2() override;
243   void addPreEmitPass() override;
244 };
245 } // namespace
246 
247 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
248   return new HexagonPassConfig(this, PM);
249 }
250 
251 void HexagonPassConfig::addIRPasses() {
252   TargetPassConfig::addIRPasses();
253   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
254 
255   addPass(createAtomicExpandPass());
256   if (!NoOpt) {
257     if (EnableLoopPrefetch)
258       addPass(createLoopDataPrefetchPass());
259     if (EnableCommGEP)
260       addPass(createHexagonCommonGEP());
261     // Replace certain combinations of shifts and ands with extracts.
262     if (EnableGenExtract)
263       addPass(createHexagonGenExtract());
264   }
265 }
266 
267 bool HexagonPassConfig::addInstSelector() {
268   HexagonTargetMachine &TM = getHexagonTargetMachine();
269   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
270 
271   if (!NoOpt)
272     addPass(createHexagonOptimizeSZextends());
273 
274   addPass(createHexagonISelDag(TM, getOptLevel()));
275 
276   if (!NoOpt) {
277     // Create logical operations on predicate registers.
278     if (EnableGenPred)
279       addPass(createHexagonGenPredicate(), false);
280     // Rotate loops to expose bit-simplification opportunities.
281     if (EnableLoopResched)
282       addPass(createHexagonLoopRescheduling(), false);
283     // Split double registers.
284     if (!DisableHSDR)
285       addPass(createHexagonSplitDoubleRegs());
286     // Bit simplification.
287     if (EnableBitSimplify)
288       addPass(createHexagonBitSimplify(), false);
289     addPass(createHexagonPeephole());
290     printAndVerify("After hexagon peephole pass");
291     // Constant propagation.
292     if (!DisableHCP) {
293       addPass(createHexagonConstPropagationPass(), false);
294       addPass(&UnreachableMachineBlockElimID, false);
295     }
296     if (EnableGenInsert)
297       addPass(createHexagonGenInsert(), false);
298     if (EnableEarlyIf)
299       addPass(createHexagonEarlyIfConversion(), false);
300   }
301 
302   return false;
303 }
304 
305 void HexagonPassConfig::addPreRegAlloc() {
306   if (getOptLevel() != CodeGenOpt::None) {
307     if (EnableExpandCondsets)
308       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
309     if (!DisableStoreWidening)
310       addPass(createHexagonStoreWidening(), false);
311     if (!DisableHardwareLoops)
312       addPass(createHexagonHardwareLoops(), false);
313   }
314   if (TM->getOptLevel() >= CodeGenOpt::Default)
315     addPass(&MachinePipelinerID);
316 }
317 
318 void HexagonPassConfig::addPostRegAlloc() {
319   if (getOptLevel() != CodeGenOpt::None) {
320     if (EnableRDFOpt)
321       addPass(createHexagonRDFOpt());
322     if (!DisableHexagonCFGOpt)
323       addPass(createHexagonCFGOptimizer(), false);
324     if (!DisableAModeOpt)
325       addPass(createHexagonOptAddrMode(), false);
326   }
327 }
328 
329 void HexagonPassConfig::addPreSched2() {
330   addPass(createHexagonCopyToCombine(), false);
331   if (getOptLevel() != CodeGenOpt::None)
332     addPass(&IfConverterID, false);
333   addPass(createHexagonSplitConst32AndConst64());
334 }
335 
336 void HexagonPassConfig::addPreEmitPass() {
337   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
338 
339   if (!NoOpt)
340     addPass(createHexagonNewValueJump(), false);
341 
342   addPass(createHexagonBranchRelaxation(), false);
343 
344   // Create Packets.
345   if (!NoOpt) {
346     if (!DisableHardwareLoops)
347       addPass(createHexagonFixupHwLoops(), false);
348     // Generate MUX from pairs of conditional transfers.
349     if (EnableGenMux)
350       addPass(createHexagonGenMux(), false);
351 
352     addPass(createHexagonPacketizer(), false);
353   }
354   if (EnableVectorPrint)
355     addPass(createHexagonVectorPrint(), false);
356 
357   // Add CFI instructions if necessary.
358   addPass(createHexagonCallFrameInformation(), false);
359 }
360