1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/IR/LegacyPassManager.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Transforms/Scalar.h"
26 
27 using namespace llvm;
28 
29 
30 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
31   cl::init(true), cl::desc("Enable RDF-based optimizations"));
32 
33 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
34   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
35 
36 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
37   cl::Hidden, cl::ZeroOrMore, cl::init(false),
38   cl::desc("Disable Hexagon CFG Optimization"));
39 
40 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
41   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
42 
43 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
44   cl::init(true), cl::Hidden, cl::ZeroOrMore,
45   cl::desc("Early expansion of MUX"));
46 
47 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
48   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
49 
50 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
51   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
52 
53 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
54   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
55 
56 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
57   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
58 
59 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
60   cl::desc("Enable converting conditional transfers into MUX instructions"));
61 
62 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
63   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
64   "predicate instructions"));
65 
66 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
67   cl::desc("Disable splitting double registers"));
68 
69 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
70   cl::Hidden, cl::desc("Bit simplification"));
71 
72 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
73   cl::Hidden, cl::desc("Loop rescheduling"));
74 
75 /// HexagonTargetMachineModule - Note that this is used on hosts that
76 /// cannot link in a library unless there are references into the
77 /// library.  In particular, it seems that it is not possible to get
78 /// things to work on Win32 without this.  Though it is unused, do not
79 /// remove it.
80 extern "C" int HexagonTargetMachineModule;
81 int HexagonTargetMachineModule = 0;
82 
83 extern "C" void LLVMInitializeHexagonTarget() {
84   // Register the target.
85   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
86 }
87 
88 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
89   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
90 }
91 
92 static MachineSchedRegistry
93 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
94                     createVLIWMachineSched);
95 
96 namespace llvm {
97   FunctionPass *createHexagonBitSimplify();
98   FunctionPass *createHexagonCallFrameInformation();
99   FunctionPass *createHexagonCFGOptimizer();
100   FunctionPass *createHexagonCommonGEP();
101   FunctionPass *createHexagonCopyToCombine();
102   FunctionPass *createHexagonEarlyIfConversion();
103   FunctionPass *createHexagonExpandCondsets();
104   FunctionPass *createHexagonFixupHwLoops();
105   FunctionPass *createHexagonGenExtract();
106   FunctionPass *createHexagonGenInsert();
107   FunctionPass *createHexagonGenMux();
108   FunctionPass *createHexagonGenPredicate();
109   FunctionPass *createHexagonHardwareLoops();
110   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
111                                      CodeGenOpt::Level OptLevel);
112   FunctionPass *createHexagonLoopRescheduling();
113   FunctionPass *createHexagonNewValueJump();
114   FunctionPass *createHexagonOptimizeSZextends();
115   FunctionPass *createHexagonPacketizer();
116   FunctionPass *createHexagonPeephole();
117   FunctionPass *createHexagonRDFOpt();
118   FunctionPass *createHexagonSplitConst32AndConst64();
119   FunctionPass *createHexagonSplitDoubleRegs();
120   FunctionPass *createHexagonStoreWidening();
121 } // end namespace llvm;
122 
123 
124 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
125                                            StringRef CPU, StringRef FS,
126                                            const TargetOptions &Options,
127                                            Reloc::Model RM, CodeModel::Model CM,
128                                            CodeGenOpt::Level OL)
129     // Specify the vector alignment explicitly. For v512x1, the calculated
130     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
131     // the required minimum of 64 bytes.
132     : LLVMTargetMachine(T, "e-m:e-p:32:32:32-a:0-n16:32-"
133          "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
134          "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
135          TT, CPU, FS, Options, RM, CM, OL),
136       TLOF(make_unique<HexagonTargetObjectFile>()) {
137   initAsmInfo();
138 }
139 
140 const HexagonSubtarget *
141 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
142   AttributeSet FnAttrs = F.getAttributes();
143   Attribute CPUAttr =
144       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
145   Attribute FSAttr =
146       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
147 
148   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
149                         ? CPUAttr.getValueAsString().str()
150                         : TargetCPU;
151   std::string FS = !FSAttr.hasAttribute(Attribute::None)
152                        ? FSAttr.getValueAsString().str()
153                        : TargetFS;
154 
155   auto &I = SubtargetMap[CPU + FS];
156   if (!I) {
157     // This needs to be done before we create a new subtarget since any
158     // creation will depend on the TM and the code generation flags on the
159     // function that reside in TargetOptions.
160     resetTargetOptions(F);
161     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
162   }
163   return I.get();
164 }
165 
166 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
167   return TargetIRAnalysis([this](const Function &F) {
168     return TargetTransformInfo(HexagonTTIImpl(this, F));
169   });
170 }
171 
172 
173 HexagonTargetMachine::~HexagonTargetMachine() {}
174 
175 namespace {
176 /// Hexagon Code Generator Pass Configuration Options.
177 class HexagonPassConfig : public TargetPassConfig {
178 public:
179   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
180     : TargetPassConfig(TM, PM) {
181     bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
182     if (!NoOpt) {
183       if (EnableExpandCondsets) {
184         Pass *Exp = createHexagonExpandCondsets();
185         insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
186       }
187     }
188   }
189 
190   HexagonTargetMachine &getHexagonTargetMachine() const {
191     return getTM<HexagonTargetMachine>();
192   }
193 
194   ScheduleDAGInstrs *
195   createMachineScheduler(MachineSchedContext *C) const override {
196     return createVLIWMachineSched(C);
197   }
198 
199   void addIRPasses() override;
200   bool addInstSelector() override;
201   void addPreRegAlloc() override;
202   void addPostRegAlloc() override;
203   void addPreSched2() override;
204   void addPreEmitPass() override;
205 };
206 } // namespace
207 
208 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
209   return new HexagonPassConfig(this, PM);
210 }
211 
212 void HexagonPassConfig::addIRPasses() {
213   TargetPassConfig::addIRPasses();
214   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
215 
216   addPass(createAtomicExpandPass(TM));
217   if (!NoOpt) {
218     if (EnableCommGEP)
219       addPass(createHexagonCommonGEP());
220     // Replace certain combinations of shifts and ands with extracts.
221     if (EnableGenExtract)
222       addPass(createHexagonGenExtract());
223   }
224 }
225 
226 bool HexagonPassConfig::addInstSelector() {
227   HexagonTargetMachine &TM = getHexagonTargetMachine();
228   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
229 
230   if (!NoOpt)
231     addPass(createHexagonOptimizeSZextends());
232 
233   addPass(createHexagonISelDag(TM, getOptLevel()));
234 
235   if (!NoOpt) {
236     // Create logical operations on predicate registers.
237     if (EnableGenPred)
238       addPass(createHexagonGenPredicate(), false);
239     // Rotate loops to expose bit-simplification opportunities.
240     if (EnableLoopResched)
241       addPass(createHexagonLoopRescheduling(), false);
242     // Split double registers.
243     if (!DisableHSDR)
244       addPass(createHexagonSplitDoubleRegs());
245     // Bit simplification.
246     if (EnableBitSimplify)
247       addPass(createHexagonBitSimplify(), false);
248     addPass(createHexagonPeephole());
249     printAndVerify("After hexagon peephole pass");
250     if (EnableGenInsert)
251       addPass(createHexagonGenInsert(), false);
252     if (EnableEarlyIf)
253       addPass(createHexagonEarlyIfConversion(), false);
254   }
255 
256   return false;
257 }
258 
259 void HexagonPassConfig::addPreRegAlloc() {
260   if (getOptLevel() != CodeGenOpt::None) {
261     if (!DisableStoreWidening)
262       addPass(createHexagonStoreWidening(), false);
263     if (!DisableHardwareLoops)
264       addPass(createHexagonHardwareLoops(), false);
265   }
266 }
267 
268 void HexagonPassConfig::addPostRegAlloc() {
269   if (getOptLevel() != CodeGenOpt::None) {
270     if (EnableRDFOpt)
271       addPass(createHexagonRDFOpt());
272     if (!DisableHexagonCFGOpt)
273       addPass(createHexagonCFGOptimizer(), false);
274   }
275 }
276 
277 void HexagonPassConfig::addPreSched2() {
278   addPass(createHexagonCopyToCombine(), false);
279   if (getOptLevel() != CodeGenOpt::None)
280     addPass(&IfConverterID, false);
281   addPass(createHexagonSplitConst32AndConst64());
282 }
283 
284 void HexagonPassConfig::addPreEmitPass() {
285   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
286 
287   if (!NoOpt)
288     addPass(createHexagonNewValueJump(), false);
289 
290   // Create Packets.
291   if (!NoOpt) {
292     if (!DisableHardwareLoops)
293       addPass(createHexagonFixupHwLoops(), false);
294     // Generate MUX from pairs of conditional transfers.
295     if (EnableGenMux)
296       addPass(createHexagonGenMux(), false);
297 
298     addPass(createHexagonPacketizer(), false);
299   }
300 
301   // Add CFI instructions if necessary.
302   addPass(createHexagonCallFrameInformation(), false);
303 }
304