1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/IR/LegacyPassManager.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Transforms/Scalar.h"
26 
27 using namespace llvm;
28 
29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
31 
32 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
33   cl::Hidden, cl::ZeroOrMore, cl::init(false),
34   cl::desc("Disable Hexagon CFG Optimization"));
35 
36 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
37   cl::init(true), cl::Hidden, cl::ZeroOrMore,
38   cl::desc("Early expansion of MUX"));
39 
40 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
41   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
42 
43 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
44   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
45 
46 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
47   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
48 
49 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
50   cl::desc("Enable converting conditional transfers into MUX instructions"));
51 
52 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
53   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
54   "predicate instructions"));
55 
56 /// HexagonTargetMachineModule - Note that this is used on hosts that
57 /// cannot link in a library unless there are references into the
58 /// library.  In particular, it seems that it is not possible to get
59 /// things to work on Win32 without this.  Though it is unused, do not
60 /// remove it.
61 extern "C" int HexagonTargetMachineModule;
62 int HexagonTargetMachineModule = 0;
63 
64 extern "C" void LLVMInitializeHexagonTarget() {
65   // Register the target.
66   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
67 }
68 
69 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
70   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
71 }
72 
73 static MachineSchedRegistry
74 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
75                     createVLIWMachineSched);
76 
77 namespace llvm {
78   FunctionPass *createHexagonCFGOptimizer();
79   FunctionPass *createHexagonCommonGEP();
80   FunctionPass *createHexagonCopyToCombine();
81   FunctionPass *createHexagonExpandCondsets();
82   FunctionPass *createHexagonExpandPredSpillCode();
83   FunctionPass *createHexagonFixupHwLoops();
84   FunctionPass *createHexagonGenExtract();
85   FunctionPass *createHexagonGenInsert();
86   FunctionPass *createHexagonGenMux();
87   FunctionPass *createHexagonGenPredicate();
88   FunctionPass *createHexagonHardwareLoops();
89   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
90                                      CodeGenOpt::Level OptLevel);
91   FunctionPass *createHexagonNewValueJump();
92   FunctionPass *createHexagonPacketizer();
93   FunctionPass *createHexagonPeephole();
94   FunctionPass *createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM);
95   FunctionPass *createHexagonSplitConst32AndConst64();
96 } // end namespace llvm;
97 
98 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
99 ///
100 
101 /// Hexagon_TODO: Do I need an aggregate alignment?
102 ///
103 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
104                                            StringRef CPU, StringRef FS,
105                                            const TargetOptions &Options,
106                                            Reloc::Model RM, CodeModel::Model CM,
107                                            CodeGenOpt::Level OL)
108     : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
109                         Options, RM, CM, OL),
110       TLOF(make_unique<HexagonTargetObjectFile>()) {
111   initAsmInfo();
112 }
113 
114 const HexagonSubtarget *
115 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
116   AttributeSet FnAttrs = F.getAttributes();
117   Attribute CPUAttr =
118       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
119   Attribute FSAttr =
120       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
121 
122   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
123                         ? CPUAttr.getValueAsString().str()
124                         : TargetCPU;
125   std::string FS = !FSAttr.hasAttribute(Attribute::None)
126                        ? FSAttr.getValueAsString().str()
127                        : TargetFS;
128 
129   auto &I = SubtargetMap[CPU + FS];
130   if (!I) {
131     // This needs to be done before we create a new subtarget since any
132     // creation will depend on the TM and the code generation flags on the
133     // function that reside in TargetOptions.
134     resetTargetOptions(F);
135     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
136   }
137   return I.get();
138 }
139 
140 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
141   return TargetIRAnalysis([this](const Function &F) {
142     return TargetTransformInfo(HexagonTTIImpl(this, F));
143   });
144 }
145 
146 
147 HexagonTargetMachine::~HexagonTargetMachine() {}
148 
149 namespace {
150 /// Hexagon Code Generator Pass Configuration Options.
151 class HexagonPassConfig : public TargetPassConfig {
152 public:
153   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
154     : TargetPassConfig(TM, PM) {
155     bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
156     if (!NoOpt) {
157       if (EnableExpandCondsets) {
158         Pass *Exp = createHexagonExpandCondsets();
159         insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
160       }
161     }
162   }
163 
164   HexagonTargetMachine &getHexagonTargetMachine() const {
165     return getTM<HexagonTargetMachine>();
166   }
167 
168   ScheduleDAGInstrs *
169   createMachineScheduler(MachineSchedContext *C) const override {
170     return createVLIWMachineSched(C);
171   }
172 
173   void addIRPasses() override;
174   bool addInstSelector() override;
175   void addPreRegAlloc() override;
176   void addPostRegAlloc() override;
177   void addPreSched2() override;
178   void addPreEmitPass() override;
179 };
180 } // namespace
181 
182 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
183   return new HexagonPassConfig(this, PM);
184 }
185 
186 void HexagonPassConfig::addIRPasses() {
187   TargetPassConfig::addIRPasses();
188   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
189 
190   addPass(createAtomicExpandPass(TM));
191   if (!NoOpt) {
192     if (EnableCommGEP)
193       addPass(createHexagonCommonGEP());
194     // Replace certain combinations of shifts and ands with extracts.
195     if (EnableGenExtract)
196       addPass(createHexagonGenExtract());
197   }
198 }
199 
200 bool HexagonPassConfig::addInstSelector() {
201   HexagonTargetMachine &TM = getHexagonTargetMachine();
202   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
203 
204   if (!NoOpt)
205     addPass(createHexagonRemoveExtendArgs(TM));
206 
207   addPass(createHexagonISelDag(TM, getOptLevel()));
208 
209   if (!NoOpt) {
210     // Create logical operations on predicate registers.
211     if (EnableGenPred)
212       addPass(createHexagonGenPredicate(), false);
213     addPass(createHexagonPeephole());
214     printAndVerify("After hexagon peephole pass");
215     if (EnableGenInsert)
216       addPass(createHexagonGenInsert(), false);
217   }
218 
219   return false;
220 }
221 
222 void HexagonPassConfig::addPreRegAlloc() {
223   if (getOptLevel() != CodeGenOpt::None)
224     if (!DisableHardwareLoops)
225       addPass(createHexagonHardwareLoops(), false);
226 }
227 
228 void HexagonPassConfig::addPostRegAlloc() {
229   if (getOptLevel() != CodeGenOpt::None)
230     if (!DisableHexagonCFGOpt)
231       addPass(createHexagonCFGOptimizer(), false);
232 }
233 
234 void HexagonPassConfig::addPreSched2() {
235   addPass(createHexagonCopyToCombine(), false);
236   if (getOptLevel() != CodeGenOpt::None)
237     addPass(&IfConverterID, false);
238   addPass(createHexagonSplitConst32AndConst64());
239 }
240 
241 void HexagonPassConfig::addPreEmitPass() {
242   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
243 
244   if (!NoOpt)
245     addPass(createHexagonNewValueJump(), false);
246 
247   // Expand Spill code for predicate registers.
248   addPass(createHexagonExpandPredSpillCode(), false);
249 
250   // Create Packets.
251   if (!NoOpt) {
252     if (!DisableHardwareLoops)
253       addPass(createHexagonFixupHwLoops(), false);
254     // Generate MUX from pairs of conditional transfers.
255     if (EnableGenMux)
256       addPass(createHexagonGenMux(), false);
257 
258     addPass(createHexagonPacketizer(), false);
259   }
260 }
261