1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
16 #include "HexagonLoopIdiomRecognition.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "HexagonVectorLoopCarriedReuse.h"
21 #include "TargetInfo/HexagonTargetInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/CodeGen/VLIWMachineScheduler.h"
25 #include "llvm/IR/LegacyPassManager.h"
26 #include "llvm/IR/Module.h"
27 #include "llvm/MC/TargetRegistry.h"
28 #include "llvm/Passes/PassBuilder.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
31 #include "llvm/Transforms/Scalar.h"
32 
33 using namespace llvm;
34 
35 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
36   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
37 
38 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
39   cl::init(true), cl::desc("Enable RDF-based optimizations"));
40 
41 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
42   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
43 
44 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon Addressing Mode Optimization"));
47 
48 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
49   cl::Hidden, cl::ZeroOrMore, cl::init(false),
50   cl::desc("Disable Hexagon CFG Optimization"));
51 
52 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
53   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
54 
55 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
56   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
57 
58 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
59   cl::init(true), cl::Hidden, cl::ZeroOrMore,
60   cl::desc("Early expansion of MUX"));
61 
62 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
63   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
64 
65 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
66   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
67 
68 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
69   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
70 
71 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
72   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
73 
74 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
75   cl::desc("Enable converting conditional transfers into MUX instructions"));
76 
77 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
78   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
79   "predicate instructions"));
80 
81 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
82   cl::init(false), cl::Hidden, cl::ZeroOrMore,
83   cl::desc("Enable loop data prefetch on Hexagon"));
84 
85 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
86   cl::desc("Disable splitting double registers"));
87 
88 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
89   cl::Hidden, cl::desc("Bit simplification"));
90 
91 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
92   cl::Hidden, cl::desc("Loop rescheduling"));
93 
94 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
95   cl::Hidden, cl::desc("Disable backend optimizations"));
96 
97 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
98   cl::Hidden, cl::ZeroOrMore, cl::init(false),
99   cl::desc("Enable Hexagon Vector print instr pass"));
100 
101 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
102   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
103 
104 static cl::opt<bool> EnableVectorCombine("hexagon-vector-combine", cl::Hidden,
105   cl::ZeroOrMore, cl::init(true), cl::desc("Enable HVX vector combining"));
106 
107 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
108   cl::Hidden, cl::ZeroOrMore, cl::init(true),
109   cl::desc("Simplify the CFG after atomic expansion pass"));
110 
111 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
112                                         cl::ZeroOrMore, cl::init(true),
113                                         cl::desc("Enable instsimplify"));
114 
115 /// HexagonTargetMachineModule - Note that this is used on hosts that
116 /// cannot link in a library unless there are references into the
117 /// library.  In particular, it seems that it is not possible to get
118 /// things to work on Win32 without this.  Though it is unused, do not
119 /// remove it.
120 extern "C" int HexagonTargetMachineModule;
121 int HexagonTargetMachineModule = 0;
122 
123 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
124   ScheduleDAGMILive *DAG = new VLIWMachineScheduler(
125       C, std::make_unique<HexagonConvergingVLIWScheduler>());
126   DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
127   DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
128   DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
129   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
130   return DAG;
131 }
132 
133 static MachineSchedRegistry
134 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
135                     createVLIWMachineSched);
136 
137 namespace llvm {
138   extern char &HexagonExpandCondsetsID;
139   void initializeHexagonBitSimplifyPass(PassRegistry&);
140   void initializeHexagonConstExtendersPass(PassRegistry&);
141   void initializeHexagonConstPropagationPass(PassRegistry&);
142   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
143   void initializeHexagonExpandCondsetsPass(PassRegistry&);
144   void initializeHexagonGenMuxPass(PassRegistry&);
145   void initializeHexagonHardwareLoopsPass(PassRegistry&);
146   void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
147   void initializeHexagonNewValueJumpPass(PassRegistry&);
148   void initializeHexagonOptAddrModePass(PassRegistry&);
149   void initializeHexagonPacketizerPass(PassRegistry&);
150   void initializeHexagonRDFOptPass(PassRegistry&);
151   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
152   void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
153   void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
154   void initializeHexagonVExtractPass(PassRegistry&);
155   Pass *createHexagonLoopIdiomPass();
156   Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
157 
158   FunctionPass *createHexagonBitSimplify();
159   FunctionPass *createHexagonBranchRelaxation();
160   FunctionPass *createHexagonCallFrameInformation();
161   FunctionPass *createHexagonCFGOptimizer();
162   FunctionPass *createHexagonCommonGEP();
163   FunctionPass *createHexagonConstExtenders();
164   FunctionPass *createHexagonConstPropagationPass();
165   FunctionPass *createHexagonCopyToCombine();
166   FunctionPass *createHexagonEarlyIfConversion();
167   FunctionPass *createHexagonFixupHwLoops();
168   FunctionPass *createHexagonGenExtract();
169   FunctionPass *createHexagonGenInsert();
170   FunctionPass *createHexagonGenMux();
171   FunctionPass *createHexagonGenPredicate();
172   FunctionPass *createHexagonHardwareLoops();
173   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
174                                      CodeGenOpt::Level OptLevel);
175   FunctionPass *createHexagonLoopRescheduling();
176   FunctionPass *createHexagonNewValueJump();
177   FunctionPass *createHexagonOptAddrMode();
178   FunctionPass *createHexagonOptimizeSZextends();
179   FunctionPass *createHexagonPacketizer(bool Minimal);
180   FunctionPass *createHexagonPeephole();
181   FunctionPass *createHexagonRDFOpt();
182   FunctionPass *createHexagonSplitConst32AndConst64();
183   FunctionPass *createHexagonSplitDoubleRegs();
184   FunctionPass *createHexagonStoreWidening();
185   FunctionPass *createHexagonVectorCombineLegacyPass();
186   FunctionPass *createHexagonVectorPrint();
187   FunctionPass *createHexagonVExtract();
188 } // end namespace llvm;
189 
190 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
191   return RM.getValueOr(Reloc::Static);
192 }
193 
194 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
195   // Register the target.
196   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
197 
198   PassRegistry &PR = *PassRegistry::getPassRegistry();
199   initializeHexagonBitSimplifyPass(PR);
200   initializeHexagonConstExtendersPass(PR);
201   initializeHexagonConstPropagationPass(PR);
202   initializeHexagonEarlyIfConversionPass(PR);
203   initializeHexagonGenMuxPass(PR);
204   initializeHexagonHardwareLoopsPass(PR);
205   initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
206   initializeHexagonNewValueJumpPass(PR);
207   initializeHexagonOptAddrModePass(PR);
208   initializeHexagonPacketizerPass(PR);
209   initializeHexagonRDFOptPass(PR);
210   initializeHexagonSplitDoubleRegsPass(PR);
211   initializeHexagonVectorCombineLegacyPass(PR);
212   initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
213   initializeHexagonVExtractPass(PR);
214 }
215 
216 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
217                                            StringRef CPU, StringRef FS,
218                                            const TargetOptions &Options,
219                                            Optional<Reloc::Model> RM,
220                                            Optional<CodeModel::Model> CM,
221                                            CodeGenOpt::Level OL, bool JIT)
222     // Specify the vector alignment explicitly. For v512x1, the calculated
223     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
224     // the required minimum of 64 bytes.
225     : LLVMTargetMachine(
226           T,
227           "e-m:e-p:32:32:32-a:0-n16:32-"
228           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
229           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
230           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
231           getEffectiveCodeModel(CM, CodeModel::Small),
232           (HexagonNoOpt ? CodeGenOpt::None : OL)),
233       TLOF(std::make_unique<HexagonTargetObjectFile>()) {
234   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
235   initAsmInfo();
236 }
237 
238 const HexagonSubtarget *
239 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
240   AttributeList FnAttrs = F.getAttributes();
241   Attribute CPUAttr =
242       FnAttrs.getFnAttr("target-cpu");
243   Attribute FSAttr =
244       FnAttrs.getFnAttr("target-features");
245 
246   std::string CPU =
247       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
248   std::string FS =
249       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
250   // Append the preexisting target features last, so that +mattr overrides
251   // the "unsafe-fp-math" function attribute.
252   // Creating a separate target feature is not strictly necessary, it only
253   // exists to make "unsafe-fp-math" force creating a new subtarget.
254 
255   if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
256     FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
257 
258   auto &I = SubtargetMap[CPU + FS];
259   if (!I) {
260     // This needs to be done before we create a new subtarget since any
261     // creation will depend on the TM and the code generation flags on the
262     // function that reside in TargetOptions.
263     resetTargetOptions(F);
264     I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
265   }
266   return I.get();
267 }
268 
269 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
270   PMB.addExtension(
271     PassManagerBuilder::EP_LateLoopOptimizations,
272     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
273       PM.add(createHexagonLoopIdiomPass());
274     });
275   PMB.addExtension(
276       PassManagerBuilder::EP_LoopOptimizerEnd,
277       [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
278         PM.add(createHexagonVectorLoopCarriedReuseLegacyPass());
279       });
280 }
281 
282 void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
283   PB.registerLateLoopOptimizationsEPCallback(
284       [=](LoopPassManager &LPM, OptimizationLevel Level) {
285         LPM.addPass(HexagonLoopIdiomRecognitionPass());
286       });
287   PB.registerLoopOptimizerEndEPCallback(
288       [=](LoopPassManager &LPM, OptimizationLevel Level) {
289         LPM.addPass(HexagonVectorLoopCarriedReusePass());
290       });
291 }
292 
293 TargetTransformInfo
294 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
295   return TargetTransformInfo(HexagonTTIImpl(this, F));
296 }
297 
298 
299 HexagonTargetMachine::~HexagonTargetMachine() {}
300 
301 namespace {
302 /// Hexagon Code Generator Pass Configuration Options.
303 class HexagonPassConfig : public TargetPassConfig {
304 public:
305   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
306     : TargetPassConfig(TM, PM) {}
307 
308   HexagonTargetMachine &getHexagonTargetMachine() const {
309     return getTM<HexagonTargetMachine>();
310   }
311 
312   ScheduleDAGInstrs *
313   createMachineScheduler(MachineSchedContext *C) const override {
314     return createVLIWMachineSched(C);
315   }
316 
317   void addIRPasses() override;
318   bool addInstSelector() override;
319   void addPreRegAlloc() override;
320   void addPostRegAlloc() override;
321   void addPreSched2() override;
322   void addPreEmitPass() override;
323 };
324 } // namespace
325 
326 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
327   return new HexagonPassConfig(*this, PM);
328 }
329 
330 void HexagonPassConfig::addIRPasses() {
331   TargetPassConfig::addIRPasses();
332   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
333 
334   if (!NoOpt) {
335     if (EnableInstSimplify)
336       addPass(createInstSimplifyLegacyPass());
337     addPass(createDeadCodeEliminationPass());
338   }
339 
340   addPass(createAtomicExpandPass());
341 
342   if (!NoOpt) {
343     if (EnableInitialCFGCleanup)
344       addPass(createCFGSimplificationPass(SimplifyCFGOptions()
345                                               .forwardSwitchCondToPhi(true)
346                                               .convertSwitchToLookupTable(true)
347                                               .needCanonicalLoops(false)
348                                               .hoistCommonInsts(true)
349                                               .sinkCommonInsts(true)));
350     if (EnableLoopPrefetch)
351       addPass(createLoopDataPrefetchPass());
352     if (EnableVectorCombine)
353       addPass(createHexagonVectorCombineLegacyPass());
354     if (EnableCommGEP)
355       addPass(createHexagonCommonGEP());
356     // Replace certain combinations of shifts and ands with extracts.
357     if (EnableGenExtract)
358       addPass(createHexagonGenExtract());
359   }
360 }
361 
362 bool HexagonPassConfig::addInstSelector() {
363   HexagonTargetMachine &TM = getHexagonTargetMachine();
364   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
365 
366   if (!NoOpt)
367     addPass(createHexagonOptimizeSZextends());
368 
369   addPass(createHexagonISelDag(TM, getOptLevel()));
370 
371   if (!NoOpt) {
372     if (EnableVExtractOpt)
373       addPass(createHexagonVExtract());
374     // Create logical operations on predicate registers.
375     if (EnableGenPred)
376       addPass(createHexagonGenPredicate());
377     // Rotate loops to expose bit-simplification opportunities.
378     if (EnableLoopResched)
379       addPass(createHexagonLoopRescheduling());
380     // Split double registers.
381     if (!DisableHSDR)
382       addPass(createHexagonSplitDoubleRegs());
383     // Bit simplification.
384     if (EnableBitSimplify)
385       addPass(createHexagonBitSimplify());
386     addPass(createHexagonPeephole());
387     // Constant propagation.
388     if (!DisableHCP) {
389       addPass(createHexagonConstPropagationPass());
390       addPass(&UnreachableMachineBlockElimID);
391     }
392     if (EnableGenInsert)
393       addPass(createHexagonGenInsert());
394     if (EnableEarlyIf)
395       addPass(createHexagonEarlyIfConversion());
396   }
397 
398   return false;
399 }
400 
401 void HexagonPassConfig::addPreRegAlloc() {
402   if (getOptLevel() != CodeGenOpt::None) {
403     if (EnableCExtOpt)
404       addPass(createHexagonConstExtenders());
405     if (EnableExpandCondsets)
406       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
407     if (!DisableStoreWidening)
408       addPass(createHexagonStoreWidening());
409     if (!DisableHardwareLoops)
410       addPass(createHexagonHardwareLoops());
411   }
412   if (TM->getOptLevel() >= CodeGenOpt::Default)
413     addPass(&MachinePipelinerID);
414 }
415 
416 void HexagonPassConfig::addPostRegAlloc() {
417   if (getOptLevel() != CodeGenOpt::None) {
418     if (EnableRDFOpt)
419       addPass(createHexagonRDFOpt());
420     if (!DisableHexagonCFGOpt)
421       addPass(createHexagonCFGOptimizer());
422     if (!DisableAModeOpt)
423       addPass(createHexagonOptAddrMode());
424   }
425 }
426 
427 void HexagonPassConfig::addPreSched2() {
428   addPass(createHexagonCopyToCombine());
429   if (getOptLevel() != CodeGenOpt::None)
430     addPass(&IfConverterID);
431   addPass(createHexagonSplitConst32AndConst64());
432 }
433 
434 void HexagonPassConfig::addPreEmitPass() {
435   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
436 
437   if (!NoOpt)
438     addPass(createHexagonNewValueJump());
439 
440   addPass(createHexagonBranchRelaxation());
441 
442   if (!NoOpt) {
443     if (!DisableHardwareLoops)
444       addPass(createHexagonFixupHwLoops());
445     // Generate MUX from pairs of conditional transfers.
446     if (EnableGenMux)
447       addPass(createHexagonGenMux());
448   }
449 
450   // Packetization is mandatory: it handles gather/scatter at all opt levels.
451   addPass(createHexagonPacketizer(NoOpt));
452 
453   if (EnableVectorPrint)
454     addPass(createHexagonVectorPrint());
455 
456   // Add CFI instructions if necessary.
457   addPass(createHexagonCallFrameInformation());
458 }
459