1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Hexagon target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "HexagonTargetMachine.h" 15 #include "Hexagon.h" 16 #include "HexagonISelLowering.h" 17 #include "HexagonMachineScheduler.h" 18 #include "HexagonTargetObjectFile.h" 19 #include "llvm/CodeGen/Passes.h" 20 #include "llvm/IR/Module.h" 21 #include "llvm/PassManager.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Transforms/IPO/PassManagerBuilder.h" 25 #include "llvm/Transforms/Scalar.h" 26 27 using namespace llvm; 28 29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops", 30 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target")); 31 32 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched", 33 cl::Hidden, cl::ZeroOrMore, cl::init(false), 34 cl::desc("Disable Hexagon MI Scheduling")); 35 36 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt", 37 cl::Hidden, cl::ZeroOrMore, cl::init(false), 38 cl::desc("Disable Hexagon CFG Optimization")); 39 40 41 /// HexagonTargetMachineModule - Note that this is used on hosts that 42 /// cannot link in a library unless there are references into the 43 /// library. In particular, it seems that it is not possible to get 44 /// things to work on Win32 without this. Though it is unused, do not 45 /// remove it. 46 extern "C" int HexagonTargetMachineModule; 47 int HexagonTargetMachineModule = 0; 48 49 extern "C" void LLVMInitializeHexagonTarget() { 50 // Register the target. 51 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget); 52 } 53 54 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) { 55 return new VLIWMachineScheduler(C, new ConvergingVLIWScheduler()); 56 } 57 58 static MachineSchedRegistry 59 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", 60 createVLIWMachineSched); 61 62 /// HexagonTargetMachine ctor - Create an ILP32 architecture model. 63 /// 64 65 /// Hexagon_TODO: Do I need an aggregate alignment? 66 /// 67 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, 68 StringRef CPU, StringRef FS, 69 const TargetOptions &Options, 70 Reloc::Model RM, 71 CodeModel::Model CM, 72 CodeGenOpt::Level OL) 73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 74 DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32") , 75 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this), 76 TSInfo(*this), 77 FrameLowering(Subtarget), 78 InstrItins(&Subtarget.getInstrItineraryData()) { 79 setMCUseCFI(false); 80 initAsmInfo(); 81 } 82 83 // addPassesForOptimizations - Allow the backend (target) to add Target 84 // Independent Optimization passes to the Pass Manager. 85 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) { 86 if (getOptLevel() != CodeGenOpt::None) { 87 PM.add(createConstantPropagationPass()); 88 PM.add(createLoopSimplifyPass()); 89 PM.add(createDeadCodeEliminationPass()); 90 PM.add(createConstantPropagationPass()); 91 PM.add(createLoopUnrollPass()); 92 PM.add(createLoopStrengthReducePass()); 93 } 94 return true; 95 } 96 97 namespace { 98 /// Hexagon Code Generator Pass Configuration Options. 99 class HexagonPassConfig : public TargetPassConfig { 100 public: 101 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) 102 : TargetPassConfig(TM, PM) { 103 // FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define 104 // HexagonSubtarget::enableMachineScheduler() { return true; }. 105 // That will bypass the SelectionDAG VLIW scheduler, which is probably just 106 // hurting compile time and will be removed eventually anyway. 107 if (DisableHexagonMISched) 108 disablePass(&MachineSchedulerID); 109 else 110 enablePass(&MachineSchedulerID); 111 } 112 113 HexagonTargetMachine &getHexagonTargetMachine() const { 114 return getTM<HexagonTargetMachine>(); 115 } 116 117 virtual ScheduleDAGInstrs * 118 createMachineScheduler(MachineSchedContext *C) const { 119 return createVLIWMachineSched(C); 120 } 121 122 virtual bool addInstSelector(); 123 virtual bool addPreRegAlloc(); 124 virtual bool addPostRegAlloc(); 125 virtual bool addPreSched2(); 126 virtual bool addPreEmitPass(); 127 }; 128 } // namespace 129 130 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) { 131 return new HexagonPassConfig(this, PM); 132 } 133 134 bool HexagonPassConfig::addInstSelector() { 135 HexagonTargetMachine &TM = getHexagonTargetMachine(); 136 bool NoOpt = (getOptLevel() == CodeGenOpt::None); 137 138 if (!NoOpt) 139 addPass(createHexagonRemoveExtendArgs(TM)); 140 141 addPass(createHexagonISelDag(TM, getOptLevel())); 142 143 if (!NoOpt) { 144 addPass(createHexagonPeephole()); 145 printAndVerify("After hexagon peephole pass"); 146 } 147 148 return false; 149 } 150 151 bool HexagonPassConfig::addPreRegAlloc() { 152 if (getOptLevel() != CodeGenOpt::None) 153 if (!DisableHardwareLoops) 154 addPass(createHexagonHardwareLoops()); 155 return false; 156 } 157 158 bool HexagonPassConfig::addPostRegAlloc() { 159 const HexagonTargetMachine &TM = getHexagonTargetMachine(); 160 if (getOptLevel() != CodeGenOpt::None) 161 if (!DisableHexagonCFGOpt) 162 addPass(createHexagonCFGOptimizer(TM)); 163 return false; 164 } 165 166 bool HexagonPassConfig::addPreSched2() { 167 const HexagonTargetMachine &TM = getHexagonTargetMachine(); 168 const HexagonTargetObjectFile &TLOF = 169 (const HexagonTargetObjectFile &)getTargetLowering()->getObjFileLowering(); 170 171 addPass(createHexagonCopyToCombine()); 172 if (getOptLevel() != CodeGenOpt::None) 173 addPass(&IfConverterID); 174 if (!TLOF.IsSmallDataEnabled()) { 175 addPass(createHexagonSplitConst32AndConst64(TM)); 176 printAndVerify("After hexagon split const32/64 pass"); 177 } 178 return true; 179 } 180 181 bool HexagonPassConfig::addPreEmitPass() { 182 const HexagonTargetMachine &TM = getHexagonTargetMachine(); 183 bool NoOpt = (getOptLevel() == CodeGenOpt::None); 184 185 if (!NoOpt) 186 addPass(createHexagonNewValueJump()); 187 188 // Expand Spill code for predicate registers. 189 addPass(createHexagonExpandPredSpillCode(TM)); 190 191 // Split up TFRcondsets into conditional transfers. 192 addPass(createHexagonSplitTFRCondSets(TM)); 193 194 // Create Packets. 195 if (!NoOpt) { 196 if (!DisableHardwareLoops) 197 addPass(createHexagonFixupHwLoops()); 198 addPass(createHexagonPacketizer()); 199 } 200 201 return false; 202 } 203