1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
33 
34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
35   cl::init(true), cl::desc("Enable RDF-based optimizations"));
36 
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
39 
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon Addressing Mode Optimization"));
43 
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon CFG Optimization"));
47 
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
50 
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
53 
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55   cl::init(true), cl::Hidden, cl::ZeroOrMore,
56   cl::desc("Early expansion of MUX"));
57 
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
60 
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
63 
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
66 
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
69 
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71   cl::desc("Enable converting conditional transfers into MUX instructions"));
72 
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75   "predicate instructions"));
76 
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78   cl::init(false), cl::Hidden, cl::ZeroOrMore,
79   cl::desc("Enable loop data prefetch on Hexagon"));
80 
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82   cl::desc("Disable splitting double registers"));
83 
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85   cl::Hidden, cl::desc("Bit simplification"));
86 
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88   cl::Hidden, cl::desc("Loop rescheduling"));
89 
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91   cl::Hidden, cl::desc("Disable backend optimizations"));
92 
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94   cl::Hidden, cl::ZeroOrMore, cl::init(false),
95   cl::desc("Enable Hexagon Vector print instr pass"));
96 
97 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
98   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
99 
100 /// HexagonTargetMachineModule - Note that this is used on hosts that
101 /// cannot link in a library unless there are references into the
102 /// library.  In particular, it seems that it is not possible to get
103 /// things to work on Win32 without this.  Though it is unused, do not
104 /// remove it.
105 extern "C" int HexagonTargetMachineModule;
106 int HexagonTargetMachineModule = 0;
107 
108 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
109   ScheduleDAGMILive *DAG =
110     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
111   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
112   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
113   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
114   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
115   return DAG;
116 }
117 
118 static MachineSchedRegistry
119 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
120                     createVLIWMachineSched);
121 
122 namespace llvm {
123   extern char &HexagonExpandCondsetsID;
124   void initializeHexagonBitSimplifyPass(PassRegistry&);
125   void initializeHexagonConstExtendersPass(PassRegistry&);
126   void initializeHexagonConstPropagationPass(PassRegistry&);
127   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
128   void initializeHexagonExpandCondsetsPass(PassRegistry&);
129   void initializeHexagonGenMuxPass(PassRegistry&);
130   void initializeHexagonHardwareLoopsPass(PassRegistry&);
131   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
132   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
133   void initializeHexagonNewValueJumpPass(PassRegistry&);
134   void initializeHexagonOptAddrModePass(PassRegistry&);
135   void initializeHexagonPacketizerPass(PassRegistry&);
136   void initializeHexagonRDFOptPass(PassRegistry&);
137   void initializeHexagonVExtractPass(PassRegistry&);
138   Pass *createHexagonLoopIdiomPass();
139   Pass *createHexagonVectorLoopCarriedReusePass();
140 
141   FunctionPass *createHexagonBitSimplify();
142   FunctionPass *createHexagonBranchRelaxation();
143   FunctionPass *createHexagonCallFrameInformation();
144   FunctionPass *createHexagonCFGOptimizer();
145   FunctionPass *createHexagonCommonGEP();
146   FunctionPass *createHexagonConstExtenders();
147   FunctionPass *createHexagonConstPropagationPass();
148   FunctionPass *createHexagonCopyToCombine();
149   FunctionPass *createHexagonEarlyIfConversion();
150   FunctionPass *createHexagonFixupHwLoops();
151   FunctionPass *createHexagonGatherPacketize();
152   FunctionPass *createHexagonGenExtract();
153   FunctionPass *createHexagonGenInsert();
154   FunctionPass *createHexagonGenMux();
155   FunctionPass *createHexagonGenPredicate();
156   FunctionPass *createHexagonHardwareLoops();
157   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
158                                      CodeGenOpt::Level OptLevel);
159   FunctionPass *createHexagonLoopRescheduling();
160   FunctionPass *createHexagonNewValueJump();
161   FunctionPass *createHexagonOptimizeSZextends();
162   FunctionPass *createHexagonOptAddrMode();
163   FunctionPass *createHexagonPacketizer();
164   FunctionPass *createHexagonPeephole();
165   FunctionPass *createHexagonRDFOpt();
166   FunctionPass *createHexagonSplitConst32AndConst64();
167   FunctionPass *createHexagonSplitDoubleRegs();
168   FunctionPass *createHexagonStoreWidening();
169   FunctionPass *createHexagonVectorPrint();
170   FunctionPass *createHexagonVExtract();
171 } // end namespace llvm;
172 
173 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
174   if (!RM.hasValue())
175     return Reloc::Static;
176   return *RM;
177 }
178 
179 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
180   if (CM)
181     return *CM;
182   return CodeModel::Small;
183 }
184 
185 extern "C" void LLVMInitializeHexagonTarget() {
186   // Register the target.
187   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
188 
189   PassRegistry &PR = *PassRegistry::getPassRegistry();
190   initializeHexagonBitSimplifyPass(PR);
191   initializeHexagonConstExtendersPass(PR);
192   initializeHexagonConstPropagationPass(PR);
193   initializeHexagonEarlyIfConversionPass(PR);
194   initializeHexagonGenMuxPass(PR);
195   initializeHexagonHardwareLoopsPass(PR);
196   initializeHexagonLoopIdiomRecognizePass(PR);
197   initializeHexagonVectorLoopCarriedReusePass(PR);
198   initializeHexagonNewValueJumpPass(PR);
199   initializeHexagonOptAddrModePass(PR);
200   initializeHexagonPacketizerPass(PR);
201   initializeHexagonRDFOptPass(PR);
202   initializeHexagonVExtractPass(PR);
203 }
204 
205 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
206                                            StringRef CPU, StringRef FS,
207                                            const TargetOptions &Options,
208                                            Optional<Reloc::Model> RM,
209                                            Optional<CodeModel::Model> CM,
210                                            CodeGenOpt::Level OL, bool JIT)
211     // Specify the vector alignment explicitly. For v512x1, the calculated
212     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
213     // the required minimum of 64 bytes.
214     : LLVMTargetMachine(
215           T,
216           "e-m:e-p:32:32:32-a:0-n16:32-"
217           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
218           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
219           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
220           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
221       TLOF(make_unique<HexagonTargetObjectFile>()) {
222   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
223   initAsmInfo();
224 }
225 
226 const HexagonSubtarget *
227 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
228   AttributeList FnAttrs = F.getAttributes();
229   Attribute CPUAttr =
230       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
231   Attribute FSAttr =
232       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
233 
234   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
235                         ? CPUAttr.getValueAsString().str()
236                         : TargetCPU;
237   std::string FS = !FSAttr.hasAttribute(Attribute::None)
238                        ? FSAttr.getValueAsString().str()
239                        : TargetFS;
240 
241   auto &I = SubtargetMap[CPU + FS];
242   if (!I) {
243     // This needs to be done before we create a new subtarget since any
244     // creation will depend on the TM and the code generation flags on the
245     // function that reside in TargetOptions.
246     resetTargetOptions(F);
247     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
248   }
249   return I.get();
250 }
251 
252 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
253   PMB.addExtension(
254     PassManagerBuilder::EP_LateLoopOptimizations,
255     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
256       PM.add(createHexagonLoopIdiomPass());
257     });
258   PMB.addExtension(
259     PassManagerBuilder::EP_LoopOptimizerEnd,
260     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
261       PM.add(createHexagonVectorLoopCarriedReusePass());
262     });
263 }
264 
265 TargetTransformInfo
266 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
267   return TargetTransformInfo(HexagonTTIImpl(this, F));
268 }
269 
270 
271 HexagonTargetMachine::~HexagonTargetMachine() {}
272 
273 namespace {
274 /// Hexagon Code Generator Pass Configuration Options.
275 class HexagonPassConfig : public TargetPassConfig {
276 public:
277   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
278     : TargetPassConfig(TM, PM) {}
279 
280   HexagonTargetMachine &getHexagonTargetMachine() const {
281     return getTM<HexagonTargetMachine>();
282   }
283 
284   ScheduleDAGInstrs *
285   createMachineScheduler(MachineSchedContext *C) const override {
286     return createVLIWMachineSched(C);
287   }
288 
289   void addIRPasses() override;
290   bool addInstSelector() override;
291   void addPreRegAlloc() override;
292   void addPostRegAlloc() override;
293   void addPreSched2() override;
294   void addPreEmitPass() override;
295 };
296 } // namespace
297 
298 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
299   return new HexagonPassConfig(*this, PM);
300 }
301 
302 void HexagonPassConfig::addIRPasses() {
303   TargetPassConfig::addIRPasses();
304   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
305 
306   if (!NoOpt) {
307     addPass(createConstantPropagationPass());
308     addPass(createDeadCodeEliminationPass());
309   }
310 
311   addPass(createAtomicExpandPass());
312   if (!NoOpt) {
313     if (EnableLoopPrefetch)
314       addPass(createLoopDataPrefetchPass());
315     if (EnableCommGEP)
316       addPass(createHexagonCommonGEP());
317     // Replace certain combinations of shifts and ands with extracts.
318     if (EnableGenExtract)
319       addPass(createHexagonGenExtract());
320   }
321 }
322 
323 bool HexagonPassConfig::addInstSelector() {
324   HexagonTargetMachine &TM = getHexagonTargetMachine();
325   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
326 
327   if (!NoOpt)
328     addPass(createHexagonOptimizeSZextends());
329 
330   addPass(createHexagonISelDag(TM, getOptLevel()));
331 
332   if (!NoOpt) {
333     if (EnableVExtractOpt)
334       addPass(createHexagonVExtract());
335     // Create logical operations on predicate registers.
336     if (EnableGenPred)
337       addPass(createHexagonGenPredicate());
338     // Rotate loops to expose bit-simplification opportunities.
339     if (EnableLoopResched)
340       addPass(createHexagonLoopRescheduling());
341     // Split double registers.
342     if (!DisableHSDR)
343       addPass(createHexagonSplitDoubleRegs());
344     // Bit simplification.
345     if (EnableBitSimplify)
346       addPass(createHexagonBitSimplify());
347     addPass(createHexagonPeephole());
348     // Constant propagation.
349     if (!DisableHCP) {
350       addPass(createHexagonConstPropagationPass());
351       addPass(&UnreachableMachineBlockElimID);
352     }
353     if (EnableGenInsert)
354       addPass(createHexagonGenInsert());
355     if (EnableEarlyIf)
356       addPass(createHexagonEarlyIfConversion());
357   }
358 
359   return false;
360 }
361 
362 void HexagonPassConfig::addPreRegAlloc() {
363   if (getOptLevel() != CodeGenOpt::None) {
364     if (EnableCExtOpt)
365       addPass(createHexagonConstExtenders());
366     if (EnableExpandCondsets)
367       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
368     if (!DisableStoreWidening)
369       addPass(createHexagonStoreWidening());
370     if (!DisableHardwareLoops)
371       addPass(createHexagonHardwareLoops());
372   }
373   if (TM->getOptLevel() >= CodeGenOpt::Default)
374     addPass(&MachinePipelinerID);
375 }
376 
377 void HexagonPassConfig::addPostRegAlloc() {
378   if (getOptLevel() != CodeGenOpt::None) {
379     if (EnableRDFOpt)
380       addPass(createHexagonRDFOpt());
381     if (!DisableHexagonCFGOpt)
382       addPass(createHexagonCFGOptimizer());
383     if (!DisableAModeOpt)
384       addPass(createHexagonOptAddrMode());
385   }
386 }
387 
388 void HexagonPassConfig::addPreSched2() {
389   addPass(createHexagonCopyToCombine());
390   if (getOptLevel() != CodeGenOpt::None)
391     addPass(&IfConverterID);
392   addPass(createHexagonSplitConst32AndConst64());
393 }
394 
395 void HexagonPassConfig::addPreEmitPass() {
396   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
397 
398   if (!NoOpt)
399     addPass(createHexagonNewValueJump());
400 
401   addPass(createHexagonBranchRelaxation());
402 
403   // Create Packets.
404   if (!NoOpt) {
405     if (!DisableHardwareLoops)
406       addPass(createHexagonFixupHwLoops());
407     // Generate MUX from pairs of conditional transfers.
408     if (EnableGenMux)
409       addPass(createHexagonGenMux());
410   }
411 
412   // Create packets for 2 instructions that consitute a gather instruction.
413   // Do this regardless of the opt level.
414   addPass(createHexagonGatherPacketize(), false);
415 
416   if (!NoOpt)
417     addPass(createHexagonPacketizer(), false);
418 
419   if (EnableVectorPrint)
420     addPass(createHexagonVectorPrint(), false);
421 
422   // Add CFI instructions if necessary.
423   addPass(createHexagonCallFrameInformation(), false);
424 }
425