1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 
34 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
35   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 
37 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
39   cl::desc("Disable Hexagon Addressing Mode Optimization"));
40 
41 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon CFG Optimization"));
44 
45 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
46   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
47 
48 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
49   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
50 
51 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
52   cl::init(true), cl::Hidden, cl::ZeroOrMore,
53   cl::desc("Early expansion of MUX"));
54 
55 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
56   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
57 
58 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
59   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
60 
61 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
62   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
63 
64 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
65   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
66 
67 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
68   cl::desc("Enable converting conditional transfers into MUX instructions"));
69 
70 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
71   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
72   "predicate instructions"));
73 
74 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
75   cl::init(false), cl::Hidden, cl::ZeroOrMore,
76   cl::desc("Enable loop data prefetch on Hexagon"));
77 
78 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
79   cl::desc("Disable splitting double registers"));
80 
81 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
82   cl::Hidden, cl::desc("Bit simplification"));
83 
84 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
85   cl::Hidden, cl::desc("Loop rescheduling"));
86 
87 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
88   cl::Hidden, cl::desc("Disable backend optimizations"));
89 
90 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
91   cl::Hidden, cl::ZeroOrMore, cl::init(false),
92   cl::desc("Enable Hexagon Vector print instr pass"));
93 
94 static cl::opt<bool> EnableTrapUnreachable("hexagon-trap-unreachable",
95   cl::Hidden, cl::ZeroOrMore, cl::init(false),
96   cl::desc("Enable generating trap for unreachable"));
97 
98 /// HexagonTargetMachineModule - Note that this is used on hosts that
99 /// cannot link in a library unless there are references into the
100 /// library.  In particular, it seems that it is not possible to get
101 /// things to work on Win32 without this.  Though it is unused, do not
102 /// remove it.
103 extern "C" int HexagonTargetMachineModule;
104 int HexagonTargetMachineModule = 0;
105 
106 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
107   ScheduleDAGMILive *DAG =
108     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
109   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
110   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
111   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
112   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
113   return DAG;
114 }
115 
116 static MachineSchedRegistry
117 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
118                     createVLIWMachineSched);
119 
120 namespace llvm {
121   extern char &HexagonExpandCondsetsID;
122   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
123   void initializeHexagonExpandCondsetsPass(PassRegistry&);
124   void initializeHexagonGenMuxPass(PassRegistry&);
125   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
126   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
127   void initializeHexagonNewValueJumpPass(PassRegistry&);
128   void initializeHexagonOptAddrModePass(PassRegistry&);
129   void initializeHexagonPacketizerPass(PassRegistry&);
130   Pass *createHexagonLoopIdiomPass();
131   Pass *createHexagonVectorLoopCarriedReusePass();
132 
133   FunctionPass *createHexagonBitSimplify();
134   FunctionPass *createHexagonBranchRelaxation();
135   FunctionPass *createHexagonCallFrameInformation();
136   FunctionPass *createHexagonCFGOptimizer();
137   FunctionPass *createHexagonCommonGEP();
138   FunctionPass *createHexagonConstPropagationPass();
139   FunctionPass *createHexagonCopyToCombine();
140   FunctionPass *createHexagonEarlyIfConversion();
141   FunctionPass *createHexagonFixupHwLoops();
142   FunctionPass *createHexagonGenExtract();
143   FunctionPass *createHexagonGenInsert();
144   FunctionPass *createHexagonGenMux();
145   FunctionPass *createHexagonGenPredicate();
146   FunctionPass *createHexagonHardwareLoops();
147   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
148                                      CodeGenOpt::Level OptLevel);
149   FunctionPass *createHexagonLoopRescheduling();
150   FunctionPass *createHexagonNewValueJump();
151   FunctionPass *createHexagonOptimizeSZextends();
152   FunctionPass *createHexagonOptAddrMode();
153   FunctionPass *createHexagonPacketizer();
154   FunctionPass *createHexagonPeephole();
155   FunctionPass *createHexagonRDFOpt();
156   FunctionPass *createHexagonSplitConst32AndConst64();
157   FunctionPass *createHexagonSplitDoubleRegs();
158   FunctionPass *createHexagonStoreWidening();
159   FunctionPass *createHexagonVectorPrint();
160 } // end namespace llvm;
161 
162 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
163   if (!RM.hasValue())
164     return Reloc::Static;
165   return *RM;
166 }
167 
168 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
169   if (CM)
170     return *CM;
171   return CodeModel::Small;
172 }
173 
174 extern "C" void LLVMInitializeHexagonTarget() {
175   // Register the target.
176   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
177 
178   PassRegistry &PR = *PassRegistry::getPassRegistry();
179   initializeHexagonEarlyIfConversionPass(PR);
180   initializeHexagonGenMuxPass(PR);
181   initializeHexagonLoopIdiomRecognizePass(PR);
182   initializeHexagonVectorLoopCarriedReusePass(PR);
183   initializeHexagonNewValueJumpPass(PR);
184   initializeHexagonOptAddrModePass(PR);
185   initializeHexagonPacketizerPass(PR);
186 }
187 
188 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
189                                            StringRef CPU, StringRef FS,
190                                            const TargetOptions &Options,
191                                            Optional<Reloc::Model> RM,
192                                            Optional<CodeModel::Model> CM,
193                                            CodeGenOpt::Level OL, bool JIT)
194     // Specify the vector alignment explicitly. For v512x1, the calculated
195     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
196     // the required minimum of 64 bytes.
197     : LLVMTargetMachine(
198           T,
199           "e-m:e-p:32:32:32-a:0-n16:32-"
200           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
201           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
202           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
203           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
204       TLOF(make_unique<HexagonTargetObjectFile>()) {
205   if (EnableTrapUnreachable)
206     this->Options.TrapUnreachable = true;
207   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
208   initAsmInfo();
209 }
210 
211 const HexagonSubtarget *
212 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
213   AttributeList FnAttrs = F.getAttributes();
214   Attribute CPUAttr =
215       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
216   Attribute FSAttr =
217       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
218 
219   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
220                         ? CPUAttr.getValueAsString().str()
221                         : TargetCPU;
222   std::string FS = !FSAttr.hasAttribute(Attribute::None)
223                        ? FSAttr.getValueAsString().str()
224                        : TargetFS;
225 
226   auto &I = SubtargetMap[CPU + FS];
227   if (!I) {
228     // This needs to be done before we create a new subtarget since any
229     // creation will depend on the TM and the code generation flags on the
230     // function that reside in TargetOptions.
231     resetTargetOptions(F);
232     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
233   }
234   return I.get();
235 }
236 
237 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
238   PMB.addExtension(
239     PassManagerBuilder::EP_LateLoopOptimizations,
240     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
241       PM.add(createHexagonLoopIdiomPass());
242     });
243   PMB.addExtension(
244     PassManagerBuilder::EP_LoopOptimizerEnd,
245     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
246       PM.add(createHexagonVectorLoopCarriedReusePass());
247     });
248 }
249 
250 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
251   return TargetIRAnalysis([this](const Function &F) {
252     return TargetTransformInfo(HexagonTTIImpl(this, F));
253   });
254 }
255 
256 
257 HexagonTargetMachine::~HexagonTargetMachine() {}
258 
259 namespace {
260 /// Hexagon Code Generator Pass Configuration Options.
261 class HexagonPassConfig : public TargetPassConfig {
262 public:
263   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
264     : TargetPassConfig(TM, PM) {}
265 
266   HexagonTargetMachine &getHexagonTargetMachine() const {
267     return getTM<HexagonTargetMachine>();
268   }
269 
270   ScheduleDAGInstrs *
271   createMachineScheduler(MachineSchedContext *C) const override {
272     return createVLIWMachineSched(C);
273   }
274 
275   void addIRPasses() override;
276   bool addInstSelector() override;
277   void addPreRegAlloc() override;
278   void addPostRegAlloc() override;
279   void addPreSched2() override;
280   void addPreEmitPass() override;
281 };
282 } // namespace
283 
284 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
285   return new HexagonPassConfig(*this, PM);
286 }
287 
288 void HexagonPassConfig::addIRPasses() {
289   TargetPassConfig::addIRPasses();
290   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
291 
292   addPass(createAtomicExpandPass());
293   if (!NoOpt) {
294     if (EnableLoopPrefetch)
295       addPass(createLoopDataPrefetchPass());
296     if (EnableCommGEP)
297       addPass(createHexagonCommonGEP());
298     // Replace certain combinations of shifts and ands with extracts.
299     if (EnableGenExtract)
300       addPass(createHexagonGenExtract());
301   }
302 }
303 
304 bool HexagonPassConfig::addInstSelector() {
305   HexagonTargetMachine &TM = getHexagonTargetMachine();
306   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
307 
308   if (!NoOpt)
309     addPass(createHexagonOptimizeSZextends());
310 
311   addPass(createHexagonISelDag(TM, getOptLevel()));
312 
313   if (!NoOpt) {
314     // Create logical operations on predicate registers.
315     if (EnableGenPred)
316       addPass(createHexagonGenPredicate());
317     // Rotate loops to expose bit-simplification opportunities.
318     if (EnableLoopResched)
319       addPass(createHexagonLoopRescheduling());
320     // Split double registers.
321     if (!DisableHSDR)
322       addPass(createHexagonSplitDoubleRegs());
323     // Bit simplification.
324     if (EnableBitSimplify)
325       addPass(createHexagonBitSimplify());
326     addPass(createHexagonPeephole());
327     // Constant propagation.
328     if (!DisableHCP) {
329       addPass(createHexagonConstPropagationPass());
330       addPass(&UnreachableMachineBlockElimID);
331     }
332     if (EnableGenInsert)
333       addPass(createHexagonGenInsert());
334     if (EnableEarlyIf)
335       addPass(createHexagonEarlyIfConversion());
336   }
337 
338   return false;
339 }
340 
341 void HexagonPassConfig::addPreRegAlloc() {
342   if (getOptLevel() != CodeGenOpt::None) {
343     if (EnableExpandCondsets)
344       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
345     if (!DisableStoreWidening)
346       addPass(createHexagonStoreWidening());
347     if (!DisableHardwareLoops)
348       addPass(createHexagonHardwareLoops());
349   }
350   if (TM->getOptLevel() >= CodeGenOpt::Default)
351     addPass(&MachinePipelinerID);
352 }
353 
354 void HexagonPassConfig::addPostRegAlloc() {
355   if (getOptLevel() != CodeGenOpt::None) {
356     if (EnableRDFOpt)
357       addPass(createHexagonRDFOpt());
358     if (!DisableHexagonCFGOpt)
359       addPass(createHexagonCFGOptimizer());
360     if (!DisableAModeOpt)
361       addPass(createHexagonOptAddrMode());
362   }
363 }
364 
365 void HexagonPassConfig::addPreSched2() {
366   addPass(createHexagonCopyToCombine());
367   if (getOptLevel() != CodeGenOpt::None)
368     addPass(&IfConverterID);
369   addPass(createHexagonSplitConst32AndConst64());
370 }
371 
372 void HexagonPassConfig::addPreEmitPass() {
373   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
374 
375   if (!NoOpt)
376     addPass(createHexagonNewValueJump());
377 
378   addPass(createHexagonBranchRelaxation());
379 
380   // Create Packets.
381   if (!NoOpt) {
382     if (!DisableHardwareLoops)
383       addPass(createHexagonFixupHwLoops());
384     // Generate MUX from pairs of conditional transfers.
385     if (EnableGenMux)
386       addPass(createHexagonGenMux());
387 
388     addPass(createHexagonPacketizer(), false);
389   }
390   if (EnableVectorPrint)
391     addPass(createHexagonVectorPrint(), false);
392 
393   // Add CFI instructions if necessary.
394   addPass(createHexagonCallFrameInformation(), false);
395 }
396