1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/Scalar.h"
27 
28 using namespace llvm;
29 
30 
31 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 
34 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
35   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 
37 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
39   cl::desc("Disable Hexagon Addressing Mode Optimization"));
40 
41 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon CFG Optimization"));
44 
45 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
46   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
47 
48 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
49   cl::init(true), cl::Hidden, cl::ZeroOrMore,
50   cl::desc("Early expansion of MUX"));
51 
52 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
53   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
54 
55 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
56   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
57 
58 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
59   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
60 
61 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
63 
64 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
65   cl::desc("Enable converting conditional transfers into MUX instructions"));
66 
67 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
68   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
69   "predicate instructions"));
70 
71 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
72   cl::desc("Disable splitting double registers"));
73 
74 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
75   cl::Hidden, cl::desc("Bit simplification"));
76 
77 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
78   cl::Hidden, cl::desc("Loop rescheduling"));
79 
80 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
81   cl::Hidden, cl::desc("Disable backend optimizations"));
82 
83 /// HexagonTargetMachineModule - Note that this is used on hosts that
84 /// cannot link in a library unless there are references into the
85 /// library.  In particular, it seems that it is not possible to get
86 /// things to work on Win32 without this.  Though it is unused, do not
87 /// remove it.
88 extern "C" int HexagonTargetMachineModule;
89 int HexagonTargetMachineModule = 0;
90 
91 extern "C" void LLVMInitializeHexagonTarget() {
92   // Register the target.
93   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
94 }
95 
96 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
97   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
98 }
99 
100 static MachineSchedRegistry
101 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
102                     createVLIWMachineSched);
103 
104 namespace llvm {
105   FunctionPass *createHexagonBitSimplify();
106   FunctionPass *createHexagonBranchRelaxation();
107   FunctionPass *createHexagonCallFrameInformation();
108   FunctionPass *createHexagonCFGOptimizer();
109   FunctionPass *createHexagonCommonGEP();
110   FunctionPass *createHexagonCopyToCombine();
111   FunctionPass *createHexagonEarlyIfConversion();
112   FunctionPass *createHexagonExpandCondsets();
113   FunctionPass *createHexagonFixupHwLoops();
114   FunctionPass *createHexagonGenExtract();
115   FunctionPass *createHexagonGenInsert();
116   FunctionPass *createHexagonGenMux();
117   FunctionPass *createHexagonGenPredicate();
118   FunctionPass *createHexagonHardwareLoops();
119   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
120                                      CodeGenOpt::Level OptLevel);
121   FunctionPass *createHexagonLoopRescheduling();
122   FunctionPass *createHexagonNewValueJump();
123   FunctionPass *createHexagonOptimizeSZextends();
124   FunctionPass *createHexagonOptAddrMode();
125   FunctionPass *createHexagonPacketizer();
126   FunctionPass *createHexagonPeephole();
127   FunctionPass *createHexagonRDFOpt();
128   FunctionPass *createHexagonSplitConst32AndConst64();
129   FunctionPass *createHexagonSplitDoubleRegs();
130   FunctionPass *createHexagonStoreWidening();
131 } // end namespace llvm;
132 
133 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
134   if (!RM.hasValue())
135     return Reloc::Static;
136   return *RM;
137 }
138 
139 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
140                                            StringRef CPU, StringRef FS,
141                                            const TargetOptions &Options,
142                                            Optional<Reloc::Model> RM,
143                                            CodeModel::Model CM,
144                                            CodeGenOpt::Level OL)
145     // Specify the vector alignment explicitly. For v512x1, the calculated
146     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
147     // the required minimum of 64 bytes.
148     : LLVMTargetMachine(
149           T, "e-m:e-p:32:32:32-a:0-n16:32-"
150              "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
151              "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
152           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
153           (HexagonNoOpt ? CodeGenOpt::None : OL)),
154       TLOF(make_unique<HexagonTargetObjectFile>()) {
155   initAsmInfo();
156 }
157 
158 const HexagonSubtarget *
159 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
160   AttributeSet FnAttrs = F.getAttributes();
161   Attribute CPUAttr =
162       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
163   Attribute FSAttr =
164       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
165 
166   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
167                         ? CPUAttr.getValueAsString().str()
168                         : TargetCPU;
169   std::string FS = !FSAttr.hasAttribute(Attribute::None)
170                        ? FSAttr.getValueAsString().str()
171                        : TargetFS;
172 
173   auto &I = SubtargetMap[CPU + FS];
174   if (!I) {
175     // This needs to be done before we create a new subtarget since any
176     // creation will depend on the TM and the code generation flags on the
177     // function that reside in TargetOptions.
178     resetTargetOptions(F);
179     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
180   }
181   return I.get();
182 }
183 
184 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
185   return TargetIRAnalysis([this](const Function &F) {
186     return TargetTransformInfo(HexagonTTIImpl(this, F));
187   });
188 }
189 
190 
191 HexagonTargetMachine::~HexagonTargetMachine() {}
192 
193 namespace {
194 /// Hexagon Code Generator Pass Configuration Options.
195 class HexagonPassConfig : public TargetPassConfig {
196 public:
197   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
198     : TargetPassConfig(TM, PM) {
199     bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
200     if (!NoOpt) {
201       if (EnableExpandCondsets) {
202         Pass *Exp = createHexagonExpandCondsets();
203         insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
204       }
205     }
206   }
207 
208   HexagonTargetMachine &getHexagonTargetMachine() const {
209     return getTM<HexagonTargetMachine>();
210   }
211 
212   ScheduleDAGInstrs *
213   createMachineScheduler(MachineSchedContext *C) const override {
214     return createVLIWMachineSched(C);
215   }
216 
217   void addIRPasses() override;
218   bool addInstSelector() override;
219   void addPreRegAlloc() override;
220   void addPostRegAlloc() override;
221   void addPreSched2() override;
222   void addPreEmitPass() override;
223 };
224 } // namespace
225 
226 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
227   return new HexagonPassConfig(this, PM);
228 }
229 
230 void HexagonPassConfig::addIRPasses() {
231   TargetPassConfig::addIRPasses();
232   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
233 
234   addPass(createAtomicExpandPass(TM));
235   if (!NoOpt) {
236     if (EnableCommGEP)
237       addPass(createHexagonCommonGEP());
238     // Replace certain combinations of shifts and ands with extracts.
239     if (EnableGenExtract)
240       addPass(createHexagonGenExtract());
241   }
242 }
243 
244 bool HexagonPassConfig::addInstSelector() {
245   HexagonTargetMachine &TM = getHexagonTargetMachine();
246   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
247 
248   if (!NoOpt)
249     addPass(createHexagonOptimizeSZextends());
250 
251   addPass(createHexagonISelDag(TM, getOptLevel()));
252 
253   if (!NoOpt) {
254     // Create logical operations on predicate registers.
255     if (EnableGenPred)
256       addPass(createHexagonGenPredicate(), false);
257     // Rotate loops to expose bit-simplification opportunities.
258     if (EnableLoopResched)
259       addPass(createHexagonLoopRescheduling(), false);
260     // Split double registers.
261     if (!DisableHSDR)
262       addPass(createHexagonSplitDoubleRegs());
263     // Bit simplification.
264     if (EnableBitSimplify)
265       addPass(createHexagonBitSimplify(), false);
266     addPass(createHexagonPeephole());
267     printAndVerify("After hexagon peephole pass");
268     if (EnableGenInsert)
269       addPass(createHexagonGenInsert(), false);
270     if (EnableEarlyIf)
271       addPass(createHexagonEarlyIfConversion(), false);
272   }
273 
274   return false;
275 }
276 
277 void HexagonPassConfig::addPreRegAlloc() {
278   if (getOptLevel() != CodeGenOpt::None) {
279     if (!DisableStoreWidening)
280       addPass(createHexagonStoreWidening(), false);
281     if (!DisableHardwareLoops)
282       addPass(createHexagonHardwareLoops(), false);
283   }
284 }
285 
286 void HexagonPassConfig::addPostRegAlloc() {
287   if (getOptLevel() != CodeGenOpt::None) {
288     if (EnableRDFOpt)
289       addPass(createHexagonRDFOpt());
290     if (!DisableHexagonCFGOpt)
291       addPass(createHexagonCFGOptimizer(), false);
292     if (!DisableAModeOpt)
293       addPass(createHexagonOptAddrMode(), false);
294   }
295 }
296 
297 void HexagonPassConfig::addPreSched2() {
298   addPass(createHexagonCopyToCombine(), false);
299   if (getOptLevel() != CodeGenOpt::None)
300     addPass(&IfConverterID, false);
301   addPass(createHexagonSplitConst32AndConst64());
302 }
303 
304 void HexagonPassConfig::addPreEmitPass() {
305   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
306 
307   if (!NoOpt)
308     addPass(createHexagonNewValueJump(), false);
309 
310   addPass(createHexagonBranchRelaxation(), false);
311 
312   // Create Packets.
313   if (!NoOpt) {
314     if (!DisableHardwareLoops)
315       addPass(createHexagonFixupHwLoops(), false);
316     // Generate MUX from pairs of conditional transfers.
317     if (EnableGenMux)
318       addPass(createHexagonGenMux(), false);
319 
320     addPass(createHexagonPacketizer(), false);
321   }
322 
323   // Add CFI instructions if necessary.
324   addPass(createHexagonCallFrameInformation(), false);
325 }
326