1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
33 
34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
35   cl::init(true), cl::desc("Enable RDF-based optimizations"));
36 
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
39 
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon Addressing Mode Optimization"));
43 
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon CFG Optimization"));
47 
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
50 
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
53 
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55   cl::init(true), cl::Hidden, cl::ZeroOrMore,
56   cl::desc("Early expansion of MUX"));
57 
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
60 
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
63 
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
66 
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
69 
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71   cl::desc("Enable converting conditional transfers into MUX instructions"));
72 
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75   "predicate instructions"));
76 
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78   cl::init(false), cl::Hidden, cl::ZeroOrMore,
79   cl::desc("Enable loop data prefetch on Hexagon"));
80 
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82   cl::desc("Disable splitting double registers"));
83 
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85   cl::Hidden, cl::desc("Bit simplification"));
86 
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88   cl::Hidden, cl::desc("Loop rescheduling"));
89 
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91   cl::Hidden, cl::desc("Disable backend optimizations"));
92 
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94   cl::Hidden, cl::ZeroOrMore, cl::init(false),
95   cl::desc("Enable Hexagon Vector print instr pass"));
96 
97 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
98   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
99 
100 /// HexagonTargetMachineModule - Note that this is used on hosts that
101 /// cannot link in a library unless there are references into the
102 /// library.  In particular, it seems that it is not possible to get
103 /// things to work on Win32 without this.  Though it is unused, do not
104 /// remove it.
105 extern "C" int HexagonTargetMachineModule;
106 int HexagonTargetMachineModule = 0;
107 
108 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
109   ScheduleDAGMILive *DAG =
110     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
111   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
112   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
113   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
114   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
115   return DAG;
116 }
117 
118 static MachineSchedRegistry
119 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
120                     createVLIWMachineSched);
121 
122 namespace llvm {
123   extern char &HexagonExpandCondsetsID;
124   void initializeHexagonConstExtendersPass(PassRegistry&);
125   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
126   void initializeHexagonExpandCondsetsPass(PassRegistry&);
127   void initializeHexagonGenMuxPass(PassRegistry&);
128   void initializeHexagonHardwareLoopsPass(PassRegistry&);
129   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
130   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
131   void initializeHexagonNewValueJumpPass(PassRegistry&);
132   void initializeHexagonOptAddrModePass(PassRegistry&);
133   void initializeHexagonPacketizerPass(PassRegistry&);
134   void initializeHexagonRDFOptPass(PassRegistry&);
135   void initializeHexagonVExtractPass(PassRegistry&);
136   Pass *createHexagonLoopIdiomPass();
137   Pass *createHexagonVectorLoopCarriedReusePass();
138 
139   FunctionPass *createHexagonBitSimplify();
140   FunctionPass *createHexagonBranchRelaxation();
141   FunctionPass *createHexagonCallFrameInformation();
142   FunctionPass *createHexagonCFGOptimizer();
143   FunctionPass *createHexagonCommonGEP();
144   FunctionPass *createHexagonConstExtenders();
145   FunctionPass *createHexagonConstPropagationPass();
146   FunctionPass *createHexagonCopyToCombine();
147   FunctionPass *createHexagonEarlyIfConversion();
148   FunctionPass *createHexagonFixupHwLoops();
149   FunctionPass *createHexagonGatherPacketize();
150   FunctionPass *createHexagonGenExtract();
151   FunctionPass *createHexagonGenInsert();
152   FunctionPass *createHexagonGenMux();
153   FunctionPass *createHexagonGenPredicate();
154   FunctionPass *createHexagonHardwareLoops();
155   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
156                                      CodeGenOpt::Level OptLevel);
157   FunctionPass *createHexagonLoopRescheduling();
158   FunctionPass *createHexagonNewValueJump();
159   FunctionPass *createHexagonOptimizeSZextends();
160   FunctionPass *createHexagonOptAddrMode();
161   FunctionPass *createHexagonPacketizer();
162   FunctionPass *createHexagonPeephole();
163   FunctionPass *createHexagonRDFOpt();
164   FunctionPass *createHexagonSplitConst32AndConst64();
165   FunctionPass *createHexagonSplitDoubleRegs();
166   FunctionPass *createHexagonStoreWidening();
167   FunctionPass *createHexagonVectorPrint();
168   FunctionPass *createHexagonVExtract();
169 } // end namespace llvm;
170 
171 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
172   if (!RM.hasValue())
173     return Reloc::Static;
174   return *RM;
175 }
176 
177 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
178   if (CM)
179     return *CM;
180   return CodeModel::Small;
181 }
182 
183 extern "C" void LLVMInitializeHexagonTarget() {
184   // Register the target.
185   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
186 
187   PassRegistry &PR = *PassRegistry::getPassRegistry();
188   initializeHexagonConstExtendersPass(PR);
189   initializeHexagonEarlyIfConversionPass(PR);
190   initializeHexagonGenMuxPass(PR);
191   initializeHexagonHardwareLoopsPass(PR);
192   initializeHexagonLoopIdiomRecognizePass(PR);
193   initializeHexagonVectorLoopCarriedReusePass(PR);
194   initializeHexagonNewValueJumpPass(PR);
195   initializeHexagonOptAddrModePass(PR);
196   initializeHexagonPacketizerPass(PR);
197   initializeHexagonRDFOptPass(PR);
198   initializeHexagonVExtractPass(PR);
199 }
200 
201 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
202                                            StringRef CPU, StringRef FS,
203                                            const TargetOptions &Options,
204                                            Optional<Reloc::Model> RM,
205                                            Optional<CodeModel::Model> CM,
206                                            CodeGenOpt::Level OL, bool JIT)
207     // Specify the vector alignment explicitly. For v512x1, the calculated
208     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
209     // the required minimum of 64 bytes.
210     : LLVMTargetMachine(
211           T,
212           "e-m:e-p:32:32:32-a:0-n16:32-"
213           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
214           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
215           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
216           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
217       TLOF(make_unique<HexagonTargetObjectFile>()) {
218   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
219   initAsmInfo();
220 }
221 
222 const HexagonSubtarget *
223 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
224   AttributeList FnAttrs = F.getAttributes();
225   Attribute CPUAttr =
226       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
227   Attribute FSAttr =
228       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
229 
230   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
231                         ? CPUAttr.getValueAsString().str()
232                         : TargetCPU;
233   std::string FS = !FSAttr.hasAttribute(Attribute::None)
234                        ? FSAttr.getValueAsString().str()
235                        : TargetFS;
236 
237   auto &I = SubtargetMap[CPU + FS];
238   if (!I) {
239     // This needs to be done before we create a new subtarget since any
240     // creation will depend on the TM and the code generation flags on the
241     // function that reside in TargetOptions.
242     resetTargetOptions(F);
243     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
244   }
245   return I.get();
246 }
247 
248 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
249   PMB.addExtension(
250     PassManagerBuilder::EP_LateLoopOptimizations,
251     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
252       PM.add(createHexagonLoopIdiomPass());
253     });
254   PMB.addExtension(
255     PassManagerBuilder::EP_LoopOptimizerEnd,
256     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
257       PM.add(createHexagonVectorLoopCarriedReusePass());
258     });
259 }
260 
261 TargetTransformInfo
262 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
263   return TargetTransformInfo(HexagonTTIImpl(this, F));
264 }
265 
266 
267 HexagonTargetMachine::~HexagonTargetMachine() {}
268 
269 namespace {
270 /// Hexagon Code Generator Pass Configuration Options.
271 class HexagonPassConfig : public TargetPassConfig {
272 public:
273   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
274     : TargetPassConfig(TM, PM) {}
275 
276   HexagonTargetMachine &getHexagonTargetMachine() const {
277     return getTM<HexagonTargetMachine>();
278   }
279 
280   ScheduleDAGInstrs *
281   createMachineScheduler(MachineSchedContext *C) const override {
282     return createVLIWMachineSched(C);
283   }
284 
285   void addIRPasses() override;
286   bool addInstSelector() override;
287   void addPreRegAlloc() override;
288   void addPostRegAlloc() override;
289   void addPreSched2() override;
290   void addPreEmitPass() override;
291 };
292 } // namespace
293 
294 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
295   return new HexagonPassConfig(*this, PM);
296 }
297 
298 void HexagonPassConfig::addIRPasses() {
299   TargetPassConfig::addIRPasses();
300   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
301 
302   if (!NoOpt) {
303     addPass(createConstantPropagationPass());
304     addPass(createDeadCodeEliminationPass());
305   }
306 
307   addPass(createAtomicExpandPass());
308   if (!NoOpt) {
309     if (EnableLoopPrefetch)
310       addPass(createLoopDataPrefetchPass());
311     if (EnableCommGEP)
312       addPass(createHexagonCommonGEP());
313     // Replace certain combinations of shifts and ands with extracts.
314     if (EnableGenExtract)
315       addPass(createHexagonGenExtract());
316   }
317 }
318 
319 bool HexagonPassConfig::addInstSelector() {
320   HexagonTargetMachine &TM = getHexagonTargetMachine();
321   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
322 
323   if (!NoOpt)
324     addPass(createHexagonOptimizeSZextends());
325 
326   addPass(createHexagonISelDag(TM, getOptLevel()));
327 
328   if (!NoOpt) {
329     if (EnableVExtractOpt)
330       addPass(createHexagonVExtract());
331     // Create logical operations on predicate registers.
332     if (EnableGenPred)
333       addPass(createHexagonGenPredicate());
334     // Rotate loops to expose bit-simplification opportunities.
335     if (EnableLoopResched)
336       addPass(createHexagonLoopRescheduling());
337     // Split double registers.
338     if (!DisableHSDR)
339       addPass(createHexagonSplitDoubleRegs());
340     // Bit simplification.
341     if (EnableBitSimplify)
342       addPass(createHexagonBitSimplify());
343     addPass(createHexagonPeephole());
344     // Constant propagation.
345     if (!DisableHCP) {
346       addPass(createHexagonConstPropagationPass());
347       addPass(&UnreachableMachineBlockElimID);
348     }
349     if (EnableGenInsert)
350       addPass(createHexagonGenInsert());
351     if (EnableEarlyIf)
352       addPass(createHexagonEarlyIfConversion());
353   }
354 
355   return false;
356 }
357 
358 void HexagonPassConfig::addPreRegAlloc() {
359   if (getOptLevel() != CodeGenOpt::None) {
360     if (EnableCExtOpt)
361       addPass(createHexagonConstExtenders());
362     if (EnableExpandCondsets)
363       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
364     if (!DisableStoreWidening)
365       addPass(createHexagonStoreWidening());
366     if (!DisableHardwareLoops)
367       addPass(createHexagonHardwareLoops());
368   }
369   if (TM->getOptLevel() >= CodeGenOpt::Default)
370     addPass(&MachinePipelinerID);
371 }
372 
373 void HexagonPassConfig::addPostRegAlloc() {
374   if (getOptLevel() != CodeGenOpt::None) {
375     if (EnableRDFOpt)
376       addPass(createHexagonRDFOpt());
377     if (!DisableHexagonCFGOpt)
378       addPass(createHexagonCFGOptimizer());
379     if (!DisableAModeOpt)
380       addPass(createHexagonOptAddrMode());
381   }
382 }
383 
384 void HexagonPassConfig::addPreSched2() {
385   addPass(createHexagonCopyToCombine());
386   if (getOptLevel() != CodeGenOpt::None)
387     addPass(&IfConverterID);
388   addPass(createHexagonSplitConst32AndConst64());
389 }
390 
391 void HexagonPassConfig::addPreEmitPass() {
392   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
393 
394   if (!NoOpt)
395     addPass(createHexagonNewValueJump());
396 
397   addPass(createHexagonBranchRelaxation());
398 
399   // Create Packets.
400   if (!NoOpt) {
401     if (!DisableHardwareLoops)
402       addPass(createHexagonFixupHwLoops());
403     // Generate MUX from pairs of conditional transfers.
404     if (EnableGenMux)
405       addPass(createHexagonGenMux());
406   }
407 
408   // Create packets for 2 instructions that consitute a gather instruction.
409   // Do this regardless of the opt level.
410   addPass(createHexagonGatherPacketize(), false);
411 
412   if (!NoOpt)
413     addPass(createHexagonPacketizer(), false);
414 
415   if (EnableVectorPrint)
416     addPass(createHexagonVectorPrint(), false);
417 
418   // Add CFI instructions if necessary.
419   addPass(createHexagonCallFrameInformation(), false);
420 }
421