1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "llvm/Module.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
21 #include "llvm/Transforms/Scalar.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
24 
25 using namespace llvm;
26 
27 static cl::
28 opt<bool> DisableHardwareLoops(
29                         "disable-hexagon-hwloops", cl::Hidden,
30                         cl::desc("Disable Hardware Loops for Hexagon target"));
31 
32 /// HexagonTargetMachineModule - Note that this is used on hosts that
33 /// cannot link in a library unless there are references into the
34 /// library.  In particular, it seems that it is not possible to get
35 /// things to work on Win32 without this.  Though it is unused, do not
36 /// remove it.
37 extern "C" int HexagonTargetMachineModule;
38 int HexagonTargetMachineModule = 0;
39 
40 extern "C" void LLVMInitializeHexagonTarget() {
41   // Register the target.
42   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
43 }
44 
45 
46 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
47 ///
48 
49 /// Hexagon_TODO: Do I need an aggregate alignment?
50 ///
51 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
52                                            StringRef CPU, StringRef FS,
53                                            const TargetOptions &Options,
54                                            Reloc::Model RM,
55                                            CodeModel::Model CM,
56                                            CodeGenOpt::Level OL)
57   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
58     DataLayout("e-p:32:32:32-"
59                 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
60                 "f64:64:64-f32:32:32-a0:0-n32") ,
61     Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
62     TSInfo(*this),
63     FrameLowering(Subtarget),
64     InstrItins(&Subtarget.getInstrItineraryData()) {
65   setMCUseCFI(false);
66 }
67 
68 // addPassesForOptimizations - Allow the backend (target) to add Target
69 // Independent Optimization passes to the Pass Manager.
70 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
71 
72   PM.add(createConstantPropagationPass());
73   PM.add(createLoopSimplifyPass());
74   PM.add(createDeadCodeEliminationPass());
75   PM.add(createConstantPropagationPass());
76   PM.add(createLoopUnrollPass());
77   PM.add(createLoopStrengthReducePass(getTargetLowering()));
78   return true;
79 }
80 
81 namespace {
82 /// Hexagon Code Generator Pass Configuration Options.
83 class HexagonPassConfig : public TargetPassConfig {
84 public:
85   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
86     : TargetPassConfig(TM, PM) {}
87 
88   HexagonTargetMachine &getHexagonTargetMachine() const {
89     return getTM<HexagonTargetMachine>();
90   }
91 
92   virtual bool addInstSelector();
93   virtual bool addPreRegAlloc();
94   virtual bool addPostRegAlloc();
95   virtual bool addPreSched2();
96   virtual bool addPreEmitPass();
97 };
98 } // namespace
99 
100 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
101   return new HexagonPassConfig(this, PM);
102 }
103 
104 bool HexagonPassConfig::addInstSelector() {
105   PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
106   PM->add(createHexagonISelDag(getHexagonTargetMachine()));
107   PM->add(createHexagonPeephole());
108   return false;
109 }
110 
111 
112 bool HexagonPassConfig::addPreRegAlloc() {
113   if (!DisableHardwareLoops) {
114     PM->add(createHexagonHardwareLoops());
115   }
116   return false;
117 }
118 
119 bool HexagonPassConfig::addPostRegAlloc() {
120   PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
121   return true;
122 }
123 
124 
125 bool HexagonPassConfig::addPreSched2() {
126   addPass(IfConverterID);
127   return true;
128 }
129 
130 bool HexagonPassConfig::addPreEmitPass() {
131 
132   if (!DisableHardwareLoops) {
133     PM->add(createHexagonFixupHwLoops());
134   }
135 
136   PM->add(createHexagonNewValueJump());
137 
138   // Expand Spill code for predicate registers.
139   PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
140 
141   // Split up TFRcondsets into conditional transfers.
142   PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
143 
144   // Create Packets.
145   PM->add(createHexagonPacketizer());
146 
147   return false;
148 }
149