1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineScheduler.h"
17 #include "HexagonTargetObjectFile.h"
18 #include "HexagonTargetTransformInfo.h"
19 #include "TargetInfo/HexagonTargetInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
33 
34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
35   cl::init(true), cl::desc("Enable RDF-based optimizations"));
36 
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
39 
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon Addressing Mode Optimization"));
43 
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon CFG Optimization"));
47 
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
50 
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
53 
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55   cl::init(true), cl::Hidden, cl::ZeroOrMore,
56   cl::desc("Early expansion of MUX"));
57 
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
60 
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
63 
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
66 
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
69 
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71   cl::desc("Enable converting conditional transfers into MUX instructions"));
72 
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75   "predicate instructions"));
76 
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78   cl::init(false), cl::Hidden, cl::ZeroOrMore,
79   cl::desc("Enable loop data prefetch on Hexagon"));
80 
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82   cl::desc("Disable splitting double registers"));
83 
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85   cl::Hidden, cl::desc("Bit simplification"));
86 
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88   cl::Hidden, cl::desc("Loop rescheduling"));
89 
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91   cl::Hidden, cl::desc("Disable backend optimizations"));
92 
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94   cl::Hidden, cl::ZeroOrMore, cl::init(false),
95   cl::desc("Enable Hexagon Vector print instr pass"));
96 
97 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
98   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
99 
100 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
101   cl::Hidden, cl::ZeroOrMore, cl::init(true),
102   cl::desc("Simplify the CFG after atomic expansion pass"));
103 
104 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
105                                         cl::ZeroOrMore, cl::init(true),
106                                         cl::desc("Enable instsimplify"));
107 
108 /// HexagonTargetMachineModule - Note that this is used on hosts that
109 /// cannot link in a library unless there are references into the
110 /// library.  In particular, it seems that it is not possible to get
111 /// things to work on Win32 without this.  Though it is unused, do not
112 /// remove it.
113 extern "C" int HexagonTargetMachineModule;
114 int HexagonTargetMachineModule = 0;
115 
116 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
117   ScheduleDAGMILive *DAG =
118     new VLIWMachineScheduler(C, std::make_unique<ConvergingVLIWScheduler>());
119   DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
120   DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
121   DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
122   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
123   return DAG;
124 }
125 
126 static MachineSchedRegistry
127 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
128                     createVLIWMachineSched);
129 
130 namespace llvm {
131   extern char &HexagonExpandCondsetsID;
132   void initializeHexagonBitSimplifyPass(PassRegistry&);
133   void initializeHexagonConstExtendersPass(PassRegistry&);
134   void initializeHexagonConstPropagationPass(PassRegistry&);
135   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
136   void initializeHexagonExpandCondsetsPass(PassRegistry&);
137   void initializeHexagonGenMuxPass(PassRegistry&);
138   void initializeHexagonHardwareLoopsPass(PassRegistry&);
139   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
140   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
141   void initializeHexagonNewValueJumpPass(PassRegistry&);
142   void initializeHexagonOptAddrModePass(PassRegistry&);
143   void initializeHexagonPacketizerPass(PassRegistry&);
144   void initializeHexagonRDFOptPass(PassRegistry&);
145   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
146   void initializeHexagonVExtractPass(PassRegistry&);
147   Pass *createHexagonLoopIdiomPass();
148   Pass *createHexagonVectorLoopCarriedReusePass();
149 
150   FunctionPass *createHexagonBitSimplify();
151   FunctionPass *createHexagonBranchRelaxation();
152   FunctionPass *createHexagonCallFrameInformation();
153   FunctionPass *createHexagonCFGOptimizer();
154   FunctionPass *createHexagonCommonGEP();
155   FunctionPass *createHexagonConstExtenders();
156   FunctionPass *createHexagonConstPropagationPass();
157   FunctionPass *createHexagonCopyToCombine();
158   FunctionPass *createHexagonEarlyIfConversion();
159   FunctionPass *createHexagonFixupHwLoops();
160   FunctionPass *createHexagonGenExtract();
161   FunctionPass *createHexagonGenInsert();
162   FunctionPass *createHexagonGenMux();
163   FunctionPass *createHexagonGenPredicate();
164   FunctionPass *createHexagonHardwareLoops();
165   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
166                                      CodeGenOpt::Level OptLevel);
167   FunctionPass *createHexagonLoopRescheduling();
168   FunctionPass *createHexagonNewValueJump();
169   FunctionPass *createHexagonOptimizeSZextends();
170   FunctionPass *createHexagonOptAddrMode();
171   FunctionPass *createHexagonPacketizer(bool Minimal);
172   FunctionPass *createHexagonPeephole();
173   FunctionPass *createHexagonRDFOpt();
174   FunctionPass *createHexagonSplitConst32AndConst64();
175   FunctionPass *createHexagonSplitDoubleRegs();
176   FunctionPass *createHexagonStoreWidening();
177   FunctionPass *createHexagonVectorPrint();
178   FunctionPass *createHexagonVExtract();
179 } // end namespace llvm;
180 
181 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
182   if (!RM.hasValue())
183     return Reloc::Static;
184   return *RM;
185 }
186 
187 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
188   // Register the target.
189   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
190 
191   PassRegistry &PR = *PassRegistry::getPassRegistry();
192   initializeHexagonBitSimplifyPass(PR);
193   initializeHexagonConstExtendersPass(PR);
194   initializeHexagonConstPropagationPass(PR);
195   initializeHexagonEarlyIfConversionPass(PR);
196   initializeHexagonGenMuxPass(PR);
197   initializeHexagonHardwareLoopsPass(PR);
198   initializeHexagonLoopIdiomRecognizePass(PR);
199   initializeHexagonVectorLoopCarriedReusePass(PR);
200   initializeHexagonNewValueJumpPass(PR);
201   initializeHexagonOptAddrModePass(PR);
202   initializeHexagonPacketizerPass(PR);
203   initializeHexagonRDFOptPass(PR);
204   initializeHexagonSplitDoubleRegsPass(PR);
205   initializeHexagonVExtractPass(PR);
206 }
207 
208 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
209                                            StringRef CPU, StringRef FS,
210                                            const TargetOptions &Options,
211                                            Optional<Reloc::Model> RM,
212                                            Optional<CodeModel::Model> CM,
213                                            CodeGenOpt::Level OL, bool JIT)
214     // Specify the vector alignment explicitly. For v512x1, the calculated
215     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
216     // the required minimum of 64 bytes.
217     : LLVMTargetMachine(
218           T,
219           "e-m:e-p:32:32:32-a:0-n16:32-"
220           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
221           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
222           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
223           getEffectiveCodeModel(CM, CodeModel::Small),
224           (HexagonNoOpt ? CodeGenOpt::None : OL)),
225       TLOF(std::make_unique<HexagonTargetObjectFile>()) {
226   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
227   initAsmInfo();
228 }
229 
230 const HexagonSubtarget *
231 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
232   AttributeList FnAttrs = F.getAttributes();
233   Attribute CPUAttr =
234       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
235   Attribute FSAttr =
236       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
237 
238   std::string CPU =
239       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
240   std::string FS =
241       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
242   // Append the preexisting target features last, so that +mattr overrides
243   // the "unsafe-fp-math" function attribute.
244   // Creating a separate target feature is not strictly necessary, it only
245   // exists to make "unsafe-fp-math" force creating a new subtarget.
246 
247   if (FnAttrs.hasFnAttribute("unsafe-fp-math") &&
248       F.getFnAttribute("unsafe-fp-math").getValueAsString() == "true")
249     FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
250 
251   auto &I = SubtargetMap[CPU + FS];
252   if (!I) {
253     // This needs to be done before we create a new subtarget since any
254     // creation will depend on the TM and the code generation flags on the
255     // function that reside in TargetOptions.
256     resetTargetOptions(F);
257     I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
258   }
259   return I.get();
260 }
261 
262 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
263   PMB.addExtension(
264     PassManagerBuilder::EP_LateLoopOptimizations,
265     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
266       PM.add(createHexagonLoopIdiomPass());
267     });
268   PMB.addExtension(
269     PassManagerBuilder::EP_LoopOptimizerEnd,
270     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
271       PM.add(createHexagonVectorLoopCarriedReusePass());
272     });
273 }
274 
275 TargetTransformInfo
276 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
277   return TargetTransformInfo(HexagonTTIImpl(this, F));
278 }
279 
280 
281 HexagonTargetMachine::~HexagonTargetMachine() {}
282 
283 namespace {
284 /// Hexagon Code Generator Pass Configuration Options.
285 class HexagonPassConfig : public TargetPassConfig {
286 public:
287   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
288     : TargetPassConfig(TM, PM) {}
289 
290   HexagonTargetMachine &getHexagonTargetMachine() const {
291     return getTM<HexagonTargetMachine>();
292   }
293 
294   ScheduleDAGInstrs *
295   createMachineScheduler(MachineSchedContext *C) const override {
296     return createVLIWMachineSched(C);
297   }
298 
299   void addIRPasses() override;
300   bool addInstSelector() override;
301   void addPreRegAlloc() override;
302   void addPostRegAlloc() override;
303   void addPreSched2() override;
304   void addPreEmitPass() override;
305 };
306 } // namespace
307 
308 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
309   return new HexagonPassConfig(*this, PM);
310 }
311 
312 void HexagonPassConfig::addIRPasses() {
313   TargetPassConfig::addIRPasses();
314   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
315 
316   if (!NoOpt) {
317     if (EnableInstSimplify)
318       addPass(createInstSimplifyLegacyPass());
319     addPass(createDeadCodeEliminationPass());
320   }
321 
322   addPass(createAtomicExpandPass());
323 
324   if (!NoOpt) {
325     if (EnableInitialCFGCleanup)
326       addPass(createCFGSimplificationPass(SimplifyCFGOptions()
327                                               .forwardSwitchCondToPhi(true)
328                                               .convertSwitchToLookupTable(true)
329                                               .needCanonicalLoops(false)
330                                               .sinkCommonInsts(true)));
331     if (EnableLoopPrefetch)
332       addPass(createLoopDataPrefetchPass());
333     if (EnableCommGEP)
334       addPass(createHexagonCommonGEP());
335     // Replace certain combinations of shifts and ands with extracts.
336     if (EnableGenExtract)
337       addPass(createHexagonGenExtract());
338   }
339 }
340 
341 bool HexagonPassConfig::addInstSelector() {
342   HexagonTargetMachine &TM = getHexagonTargetMachine();
343   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
344 
345   if (!NoOpt)
346     addPass(createHexagonOptimizeSZextends());
347 
348   addPass(createHexagonISelDag(TM, getOptLevel()));
349 
350   if (!NoOpt) {
351     if (EnableVExtractOpt)
352       addPass(createHexagonVExtract());
353     // Create logical operations on predicate registers.
354     if (EnableGenPred)
355       addPass(createHexagonGenPredicate());
356     // Rotate loops to expose bit-simplification opportunities.
357     if (EnableLoopResched)
358       addPass(createHexagonLoopRescheduling());
359     // Split double registers.
360     if (!DisableHSDR)
361       addPass(createHexagonSplitDoubleRegs());
362     // Bit simplification.
363     if (EnableBitSimplify)
364       addPass(createHexagonBitSimplify());
365     addPass(createHexagonPeephole());
366     // Constant propagation.
367     if (!DisableHCP) {
368       addPass(createHexagonConstPropagationPass());
369       addPass(&UnreachableMachineBlockElimID);
370     }
371     if (EnableGenInsert)
372       addPass(createHexagonGenInsert());
373     if (EnableEarlyIf)
374       addPass(createHexagonEarlyIfConversion());
375   }
376 
377   return false;
378 }
379 
380 void HexagonPassConfig::addPreRegAlloc() {
381   if (getOptLevel() != CodeGenOpt::None) {
382     if (EnableCExtOpt)
383       addPass(createHexagonConstExtenders());
384     if (EnableExpandCondsets)
385       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
386     if (!DisableStoreWidening)
387       addPass(createHexagonStoreWidening());
388     if (!DisableHardwareLoops)
389       addPass(createHexagonHardwareLoops());
390   }
391   if (TM->getOptLevel() >= CodeGenOpt::Default)
392     addPass(&MachinePipelinerID);
393 }
394 
395 void HexagonPassConfig::addPostRegAlloc() {
396   if (getOptLevel() != CodeGenOpt::None) {
397     if (EnableRDFOpt)
398       addPass(createHexagonRDFOpt());
399     if (!DisableHexagonCFGOpt)
400       addPass(createHexagonCFGOptimizer());
401     if (!DisableAModeOpt)
402       addPass(createHexagonOptAddrMode());
403   }
404 }
405 
406 void HexagonPassConfig::addPreSched2() {
407   addPass(createHexagonCopyToCombine());
408   if (getOptLevel() != CodeGenOpt::None)
409     addPass(&IfConverterID);
410   addPass(createHexagonSplitConst32AndConst64());
411 }
412 
413 void HexagonPassConfig::addPreEmitPass() {
414   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
415 
416   if (!NoOpt)
417     addPass(createHexagonNewValueJump());
418 
419   addPass(createHexagonBranchRelaxation());
420 
421   if (!NoOpt) {
422     if (!DisableHardwareLoops)
423       addPass(createHexagonFixupHwLoops());
424     // Generate MUX from pairs of conditional transfers.
425     if (EnableGenMux)
426       addPass(createHexagonGenMux());
427   }
428 
429   // Packetization is mandatory: it handles gather/scatter at all opt levels.
430   addPass(createHexagonPacketizer(NoOpt), false);
431 
432   if (EnableVectorPrint)
433     addPass(createHexagonVectorPrint(), false);
434 
435   // Add CFI instructions if necessary.
436   addPass(createHexagonCallFrameInformation(), false);
437 }
438