1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/IR/Module.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
25 #include "llvm/Transforms/Scalar.h"
26 
27 using namespace llvm;
28 
29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
31 
32 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
33   cl::Hidden, cl::ZeroOrMore, cl::init(false),
34   cl::desc("Disable Hexagon CFG Optimization"));
35 
36 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
37   cl::init(true), cl::Hidden, cl::ZeroOrMore,
38   cl::desc("Early expansion of MUX"));
39 
40 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
41   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
42 
43 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
44   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
45 
46 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
47   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
48 
49 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
50   cl::desc("Enable converting conditional transfers into MUX instructions"));
51 
52 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
53   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
54   "predicate instructions"));
55 
56 /// HexagonTargetMachineModule - Note that this is used on hosts that
57 /// cannot link in a library unless there are references into the
58 /// library.  In particular, it seems that it is not possible to get
59 /// things to work on Win32 without this.  Though it is unused, do not
60 /// remove it.
61 extern "C" int HexagonTargetMachineModule;
62 int HexagonTargetMachineModule = 0;
63 
64 extern "C" void LLVMInitializeHexagonTarget() {
65   // Register the target.
66   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
67 }
68 
69 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
70   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
71 }
72 
73 static MachineSchedRegistry
74 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
75                     createVLIWMachineSched);
76 
77 namespace llvm {
78   FunctionPass *createHexagonCFGOptimizer();
79   FunctionPass *createHexagonCommonGEP();
80   FunctionPass *createHexagonCopyToCombine();
81   FunctionPass *createHexagonExpandCondsets();
82   FunctionPass *createHexagonExpandPredSpillCode();
83   FunctionPass *createHexagonFixupHwLoops();
84   FunctionPass *createHexagonGenExtract();
85   FunctionPass *createHexagonGenInsert();
86   FunctionPass *createHexagonGenMux();
87   FunctionPass *createHexagonGenPredicate();
88   FunctionPass *createHexagonHardwareLoops();
89   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
90                                      CodeGenOpt::Level OptLevel);
91   FunctionPass *createHexagonNewValueJump();
92   FunctionPass *createHexagonPacketizer();
93   FunctionPass *createHexagonPeephole();
94   FunctionPass *createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM);
95   FunctionPass *createHexagonSplitConst32AndConst64();
96 } // end namespace llvm;
97 
98 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
99 ///
100 
101 /// Hexagon_TODO: Do I need an aggregate alignment?
102 ///
103 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
104                                            StringRef CPU, StringRef FS,
105                                            const TargetOptions &Options,
106                                            Reloc::Model RM, CodeModel::Model CM,
107                                            CodeGenOpt::Level OL)
108     : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
109                         Options, RM, CM, OL),
110       TLOF(make_unique<HexagonTargetObjectFile>()),
111       Subtarget(TT, CPU, FS, *this) {
112     initAsmInfo();
113 }
114 
115 HexagonTargetMachine::~HexagonTargetMachine() {}
116 
117 namespace {
118 /// Hexagon Code Generator Pass Configuration Options.
119 class HexagonPassConfig : public TargetPassConfig {
120 public:
121   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
122     : TargetPassConfig(TM, PM) {
123     bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
124     if (!NoOpt) {
125       if (EnableExpandCondsets) {
126         Pass *Exp = createHexagonExpandCondsets();
127         insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
128       }
129     }
130   }
131 
132   HexagonTargetMachine &getHexagonTargetMachine() const {
133     return getTM<HexagonTargetMachine>();
134   }
135 
136   ScheduleDAGInstrs *
137   createMachineScheduler(MachineSchedContext *C) const override {
138     return createVLIWMachineSched(C);
139   }
140 
141   void addIRPasses() override;
142   bool addInstSelector() override;
143   void addPreRegAlloc() override;
144   void addPostRegAlloc() override;
145   void addPreSched2() override;
146   void addPreEmitPass() override;
147 };
148 } // namespace
149 
150 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
151   return new HexagonPassConfig(this, PM);
152 }
153 
154 void HexagonPassConfig::addIRPasses() {
155   TargetPassConfig::addIRPasses();
156   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
157 
158   addPass(createAtomicExpandPass(TM));
159   if (!NoOpt) {
160     if (EnableCommGEP)
161       addPass(createHexagonCommonGEP());
162     // Replace certain combinations of shifts and ands with extracts.
163     if (EnableGenExtract)
164       addPass(createHexagonGenExtract());
165   }
166 }
167 
168 bool HexagonPassConfig::addInstSelector() {
169   HexagonTargetMachine &TM = getHexagonTargetMachine();
170   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
171 
172   if (!NoOpt)
173     addPass(createHexagonRemoveExtendArgs(TM));
174 
175   addPass(createHexagonISelDag(TM, getOptLevel()));
176 
177   if (!NoOpt) {
178     // Create logical operations on predicate registers.
179     if (EnableGenPred)
180       addPass(createHexagonGenPredicate(), false);
181     addPass(createHexagonPeephole());
182     printAndVerify("After hexagon peephole pass");
183     if (EnableGenInsert)
184       addPass(createHexagonGenInsert(), false);
185   }
186 
187   return false;
188 }
189 
190 void HexagonPassConfig::addPreRegAlloc() {
191   if (getOptLevel() != CodeGenOpt::None)
192     if (!DisableHardwareLoops)
193       addPass(createHexagonHardwareLoops(), false);
194 }
195 
196 void HexagonPassConfig::addPostRegAlloc() {
197   if (getOptLevel() != CodeGenOpt::None)
198     if (!DisableHexagonCFGOpt)
199       addPass(createHexagonCFGOptimizer(), false);
200 }
201 
202 void HexagonPassConfig::addPreSched2() {
203   addPass(createHexagonCopyToCombine(), false);
204   if (getOptLevel() != CodeGenOpt::None)
205     addPass(&IfConverterID, false);
206   addPass(createHexagonSplitConst32AndConst64());
207 }
208 
209 void HexagonPassConfig::addPreEmitPass() {
210   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
211 
212   if (!NoOpt)
213     addPass(createHexagonNewValueJump(), false);
214 
215   // Expand Spill code for predicate registers.
216   addPass(createHexagonExpandPredSpillCode(), false);
217 
218   // Create Packets.
219   if (!NoOpt) {
220     if (!DisableHardwareLoops)
221       addPass(createHexagonFixupHwLoops(), false);
222     // Generate MUX from pairs of conditional transfers.
223     if (EnableGenMux)
224       addPass(createHexagonGenMux(), false);
225 
226     addPass(createHexagonPacketizer(), false);
227   }
228 }
229