1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/Scalar.h"
27 
28 using namespace llvm;
29 
30 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
31   cl::init(true), cl::desc("Enable RDF-based optimizations"));
32 
33 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
34   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
35 
36 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
37   cl::Hidden, cl::ZeroOrMore, cl::init(false),
38   cl::desc("Disable Hexagon Addressing Mode Optimization"));
39 
40 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon CFG Optimization"));
43 
44 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
45   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
46 
47 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
48   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
49 
50 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
51   cl::init(true), cl::Hidden, cl::ZeroOrMore,
52   cl::desc("Early expansion of MUX"));
53 
54 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
55   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
56 
57 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
58   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
59 
60 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
61   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
62 
63 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
64   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
65 
66 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
67   cl::desc("Enable converting conditional transfers into MUX instructions"));
68 
69 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
70   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
71   "predicate instructions"));
72 
73 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
74   cl::init(false), cl::Hidden, cl::ZeroOrMore,
75   cl::desc("Enable loop data prefetch on Hexagon"));
76 
77 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
78   cl::desc("Disable splitting double registers"));
79 
80 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
81   cl::Hidden, cl::desc("Bit simplification"));
82 
83 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
84   cl::Hidden, cl::desc("Loop rescheduling"));
85 
86 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
87   cl::Hidden, cl::desc("Disable backend optimizations"));
88 
89 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
90   cl::Hidden, cl::ZeroOrMore, cl::init(false),
91   cl::desc("Enable Hexagon Vector print instr pass"));
92 
93 /// HexagonTargetMachineModule - Note that this is used on hosts that
94 /// cannot link in a library unless there are references into the
95 /// library.  In particular, it seems that it is not possible to get
96 /// things to work on Win32 without this.  Though it is unused, do not
97 /// remove it.
98 extern "C" int HexagonTargetMachineModule;
99 int HexagonTargetMachineModule = 0;
100 
101 extern "C" void LLVMInitializeHexagonTarget() {
102   // Register the target.
103   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
104 }
105 
106 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
107   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
108 }
109 
110 static MachineSchedRegistry
111 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
112                     createVLIWMachineSched);
113 
114 namespace llvm {
115   extern char &HexagonExpandCondsetsID;
116   void initializeHexagonExpandCondsetsPass(PassRegistry&);
117 
118   FunctionPass *createHexagonBitSimplify();
119   FunctionPass *createHexagonBranchRelaxation();
120   FunctionPass *createHexagonCallFrameInformation();
121   FunctionPass *createHexagonCFGOptimizer();
122   FunctionPass *createHexagonCommonGEP();
123   FunctionPass *createHexagonConstPropagationPass();
124   FunctionPass *createHexagonCopyToCombine();
125   FunctionPass *createHexagonEarlyIfConversion();
126   FunctionPass *createHexagonFixupHwLoops();
127   FunctionPass *createHexagonGenExtract();
128   FunctionPass *createHexagonGenInsert();
129   FunctionPass *createHexagonGenMux();
130   FunctionPass *createHexagonGenPredicate();
131   FunctionPass *createHexagonHardwareLoops();
132   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
133                                      CodeGenOpt::Level OptLevel);
134   FunctionPass *createHexagonLoopRescheduling();
135   FunctionPass *createHexagonNewValueJump();
136   FunctionPass *createHexagonOptimizeSZextends();
137   FunctionPass *createHexagonOptAddrMode();
138   FunctionPass *createHexagonPacketizer();
139   FunctionPass *createHexagonPeephole();
140   FunctionPass *createHexagonRDFOpt();
141   FunctionPass *createHexagonSplitConst32AndConst64();
142   FunctionPass *createHexagonSplitDoubleRegs();
143   FunctionPass *createHexagonStoreWidening();
144   FunctionPass *createHexagonVectorPrint();
145 } // end namespace llvm;
146 
147 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
148   if (!RM.hasValue())
149     return Reloc::Static;
150   return *RM;
151 }
152 
153 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
154                                            StringRef CPU, StringRef FS,
155                                            const TargetOptions &Options,
156                                            Optional<Reloc::Model> RM,
157                                            CodeModel::Model CM,
158                                            CodeGenOpt::Level OL)
159     // Specify the vector alignment explicitly. For v512x1, the calculated
160     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
161     // the required minimum of 64 bytes.
162     : LLVMTargetMachine(
163           T, "e-m:e-p:32:32:32-a:0-n16:32-"
164              "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
165              "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
166           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
167           (HexagonNoOpt ? CodeGenOpt::None : OL)),
168       TLOF(make_unique<HexagonTargetObjectFile>()) {
169   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
170   initAsmInfo();
171 }
172 
173 const HexagonSubtarget *
174 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
175   AttributeSet FnAttrs = F.getAttributes();
176   Attribute CPUAttr =
177       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
178   Attribute FSAttr =
179       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
180 
181   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
182                         ? CPUAttr.getValueAsString().str()
183                         : TargetCPU;
184   std::string FS = !FSAttr.hasAttribute(Attribute::None)
185                        ? FSAttr.getValueAsString().str()
186                        : TargetFS;
187 
188   auto &I = SubtargetMap[CPU + FS];
189   if (!I) {
190     // This needs to be done before we create a new subtarget since any
191     // creation will depend on the TM and the code generation flags on the
192     // function that reside in TargetOptions.
193     resetTargetOptions(F);
194     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
195   }
196   return I.get();
197 }
198 
199 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
200   return TargetIRAnalysis([this](const Function &F) {
201     return TargetTransformInfo(HexagonTTIImpl(this, F));
202   });
203 }
204 
205 
206 HexagonTargetMachine::~HexagonTargetMachine() {}
207 
208 namespace {
209 /// Hexagon Code Generator Pass Configuration Options.
210 class HexagonPassConfig : public TargetPassConfig {
211 public:
212   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
213     : TargetPassConfig(TM, PM) {}
214 
215   HexagonTargetMachine &getHexagonTargetMachine() const {
216     return getTM<HexagonTargetMachine>();
217   }
218 
219   ScheduleDAGInstrs *
220   createMachineScheduler(MachineSchedContext *C) const override {
221     return createVLIWMachineSched(C);
222   }
223 
224   void addIRPasses() override;
225   bool addInstSelector() override;
226   void addPreRegAlloc() override;
227   void addPostRegAlloc() override;
228   void addPreSched2() override;
229   void addPreEmitPass() override;
230 };
231 } // namespace
232 
233 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
234   return new HexagonPassConfig(this, PM);
235 }
236 
237 void HexagonPassConfig::addIRPasses() {
238   TargetPassConfig::addIRPasses();
239   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
240 
241   addPass(createAtomicExpandPass(TM));
242   if (!NoOpt) {
243     if (EnableLoopPrefetch)
244       addPass(createLoopDataPrefetchPass());
245     if (EnableCommGEP)
246       addPass(createHexagonCommonGEP());
247     // Replace certain combinations of shifts and ands with extracts.
248     if (EnableGenExtract)
249       addPass(createHexagonGenExtract());
250   }
251 }
252 
253 bool HexagonPassConfig::addInstSelector() {
254   HexagonTargetMachine &TM = getHexagonTargetMachine();
255   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
256 
257   if (!NoOpt)
258     addPass(createHexagonOptimizeSZextends());
259 
260   addPass(createHexagonISelDag(TM, getOptLevel()));
261 
262   if (!NoOpt) {
263     // Create logical operations on predicate registers.
264     if (EnableGenPred)
265       addPass(createHexagonGenPredicate(), false);
266     // Rotate loops to expose bit-simplification opportunities.
267     if (EnableLoopResched)
268       addPass(createHexagonLoopRescheduling(), false);
269     // Split double registers.
270     if (!DisableHSDR)
271       addPass(createHexagonSplitDoubleRegs());
272     // Bit simplification.
273     if (EnableBitSimplify)
274       addPass(createHexagonBitSimplify(), false);
275     addPass(createHexagonPeephole());
276     printAndVerify("After hexagon peephole pass");
277     // Constant propagation.
278     if (!DisableHCP) {
279       addPass(createHexagonConstPropagationPass(), false);
280       addPass(&UnreachableMachineBlockElimID, false);
281     }
282     if (EnableGenInsert)
283       addPass(createHexagonGenInsert(), false);
284     if (EnableEarlyIf)
285       addPass(createHexagonEarlyIfConversion(), false);
286   }
287 
288   return false;
289 }
290 
291 void HexagonPassConfig::addPreRegAlloc() {
292   if (getOptLevel() != CodeGenOpt::None) {
293     if (EnableExpandCondsets)
294       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
295     if (!DisableStoreWidening)
296       addPass(createHexagonStoreWidening(), false);
297     if (!DisableHardwareLoops)
298       addPass(createHexagonHardwareLoops(), false);
299   }
300   if (TM->getOptLevel() >= CodeGenOpt::Default)
301     addPass(&MachinePipelinerID);
302 }
303 
304 void HexagonPassConfig::addPostRegAlloc() {
305   if (getOptLevel() != CodeGenOpt::None) {
306     if (EnableRDFOpt)
307       addPass(createHexagonRDFOpt());
308     if (!DisableHexagonCFGOpt)
309       addPass(createHexagonCFGOptimizer(), false);
310     if (!DisableAModeOpt)
311       addPass(createHexagonOptAddrMode(), false);
312   }
313 }
314 
315 void HexagonPassConfig::addPreSched2() {
316   addPass(createHexagonCopyToCombine(), false);
317   if (getOptLevel() != CodeGenOpt::None)
318     addPass(&IfConverterID, false);
319   addPass(createHexagonSplitConst32AndConst64());
320 }
321 
322 void HexagonPassConfig::addPreEmitPass() {
323   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
324 
325   if (!NoOpt)
326     addPass(createHexagonNewValueJump(), false);
327 
328   addPass(createHexagonBranchRelaxation(), false);
329 
330   // Create Packets.
331   if (!NoOpt) {
332     if (!DisableHardwareLoops)
333       addPass(createHexagonFixupHwLoops(), false);
334     // Generate MUX from pairs of conditional transfers.
335     if (EnableGenMux)
336       addPass(createHexagonGenMux(), false);
337 
338     addPass(createHexagonPacketizer(), false);
339   }
340   if (EnableVectorPrint)
341     addPass(createHexagonVectorPrint(), false);
342 
343   // Add CFI instructions if necessary.
344   addPass(createHexagonCallFrameInformation(), false);
345 }
346