1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/Scalar.h"
27 
28 using namespace llvm;
29 
30 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
31   cl::init(true), cl::desc("Enable RDF-based optimizations"));
32 
33 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
34   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
35 
36 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
37   cl::Hidden, cl::ZeroOrMore, cl::init(false),
38   cl::desc("Disable Hexagon Addressing Mode Optimization"));
39 
40 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon CFG Optimization"));
43 
44 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
45   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
46 
47 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
48   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
49 
50 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
51   cl::init(true), cl::Hidden, cl::ZeroOrMore,
52   cl::desc("Early expansion of MUX"));
53 
54 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
55   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
56 
57 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
58   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
59 
60 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
61   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
62 
63 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
64   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
65 
66 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
67   cl::desc("Enable converting conditional transfers into MUX instructions"));
68 
69 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
70   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
71   "predicate instructions"));
72 
73 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
74   cl::init(false), cl::Hidden, cl::ZeroOrMore,
75   cl::desc("Enable loop data prefetch on Hexagon"));
76 
77 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
78   cl::desc("Disable splitting double registers"));
79 
80 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
81   cl::Hidden, cl::desc("Bit simplification"));
82 
83 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
84   cl::Hidden, cl::desc("Loop rescheduling"));
85 
86 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
87   cl::Hidden, cl::desc("Disable backend optimizations"));
88 
89 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
90   cl::Hidden, cl::ZeroOrMore, cl::init(false),
91   cl::desc("Enable Hexagon Vector print instr pass"));
92 
93 /// HexagonTargetMachineModule - Note that this is used on hosts that
94 /// cannot link in a library unless there are references into the
95 /// library.  In particular, it seems that it is not possible to get
96 /// things to work on Win32 without this.  Though it is unused, do not
97 /// remove it.
98 extern "C" int HexagonTargetMachineModule;
99 int HexagonTargetMachineModule = 0;
100 
101 extern "C" void LLVMInitializeHexagonTarget() {
102   // Register the target.
103   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
104 }
105 
106 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
107   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
108 }
109 
110 static MachineSchedRegistry
111 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
112                     createVLIWMachineSched);
113 
114 namespace llvm {
115   FunctionPass *createHexagonBitSimplify();
116   FunctionPass *createHexagonBranchRelaxation();
117   FunctionPass *createHexagonCallFrameInformation();
118   FunctionPass *createHexagonCFGOptimizer();
119   FunctionPass *createHexagonCommonGEP();
120   FunctionPass *createHexagonConstPropagationPass();
121   FunctionPass *createHexagonCopyToCombine();
122   FunctionPass *createHexagonEarlyIfConversion();
123   FunctionPass *createHexagonExpandCondsets();
124   FunctionPass *createHexagonFixupHwLoops();
125   FunctionPass *createHexagonGenExtract();
126   FunctionPass *createHexagonGenInsert();
127   FunctionPass *createHexagonGenMux();
128   FunctionPass *createHexagonGenPredicate();
129   FunctionPass *createHexagonHardwareLoops();
130   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
131                                      CodeGenOpt::Level OptLevel);
132   FunctionPass *createHexagonLoopRescheduling();
133   FunctionPass *createHexagonNewValueJump();
134   FunctionPass *createHexagonOptimizeSZextends();
135   FunctionPass *createHexagonOptAddrMode();
136   FunctionPass *createHexagonPacketizer();
137   FunctionPass *createHexagonPeephole();
138   FunctionPass *createHexagonRDFOpt();
139   FunctionPass *createHexagonSplitConst32AndConst64();
140   FunctionPass *createHexagonSplitDoubleRegs();
141   FunctionPass *createHexagonStoreWidening();
142   FunctionPass *createHexagonVectorPrint();
143 } // end namespace llvm;
144 
145 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
146   if (!RM.hasValue())
147     return Reloc::Static;
148   return *RM;
149 }
150 
151 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
152                                            StringRef CPU, StringRef FS,
153                                            const TargetOptions &Options,
154                                            Optional<Reloc::Model> RM,
155                                            CodeModel::Model CM,
156                                            CodeGenOpt::Level OL)
157     // Specify the vector alignment explicitly. For v512x1, the calculated
158     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
159     // the required minimum of 64 bytes.
160     : LLVMTargetMachine(
161           T, "e-m:e-p:32:32:32-a:0-n16:32-"
162              "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
163              "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
164           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
165           (HexagonNoOpt ? CodeGenOpt::None : OL)),
166       TLOF(make_unique<HexagonTargetObjectFile>()) {
167   initAsmInfo();
168 }
169 
170 const HexagonSubtarget *
171 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
172   AttributeSet FnAttrs = F.getAttributes();
173   Attribute CPUAttr =
174       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
175   Attribute FSAttr =
176       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
177 
178   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
179                         ? CPUAttr.getValueAsString().str()
180                         : TargetCPU;
181   std::string FS = !FSAttr.hasAttribute(Attribute::None)
182                        ? FSAttr.getValueAsString().str()
183                        : TargetFS;
184 
185   auto &I = SubtargetMap[CPU + FS];
186   if (!I) {
187     // This needs to be done before we create a new subtarget since any
188     // creation will depend on the TM and the code generation flags on the
189     // function that reside in TargetOptions.
190     resetTargetOptions(F);
191     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
192   }
193   return I.get();
194 }
195 
196 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
197   return TargetIRAnalysis([this](const Function &F) {
198     return TargetTransformInfo(HexagonTTIImpl(this, F));
199   });
200 }
201 
202 
203 HexagonTargetMachine::~HexagonTargetMachine() {}
204 
205 namespace {
206 /// Hexagon Code Generator Pass Configuration Options.
207 class HexagonPassConfig : public TargetPassConfig {
208 public:
209   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
210     : TargetPassConfig(TM, PM) {}
211 
212   HexagonTargetMachine &getHexagonTargetMachine() const {
213     return getTM<HexagonTargetMachine>();
214   }
215 
216   ScheduleDAGInstrs *
217   createMachineScheduler(MachineSchedContext *C) const override {
218     return createVLIWMachineSched(C);
219   }
220 
221   void addIRPasses() override;
222   bool addInstSelector() override;
223   void addPreRegAlloc() override;
224   void addPostRegAlloc() override;
225   void addPreSched2() override;
226   void addPreEmitPass() override;
227 };
228 } // namespace
229 
230 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
231   return new HexagonPassConfig(this, PM);
232 }
233 
234 void HexagonPassConfig::addIRPasses() {
235   TargetPassConfig::addIRPasses();
236   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
237 
238   addPass(createAtomicExpandPass(TM));
239   if (!NoOpt) {
240     if (EnableLoopPrefetch)
241       addPass(createLoopDataPrefetchPass());
242     if (EnableCommGEP)
243       addPass(createHexagonCommonGEP());
244     // Replace certain combinations of shifts and ands with extracts.
245     if (EnableGenExtract)
246       addPass(createHexagonGenExtract());
247   }
248 }
249 
250 bool HexagonPassConfig::addInstSelector() {
251   HexagonTargetMachine &TM = getHexagonTargetMachine();
252   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
253 
254   if (!NoOpt)
255     addPass(createHexagonOptimizeSZextends());
256 
257   addPass(createHexagonISelDag(TM, getOptLevel()));
258 
259   if (!NoOpt) {
260     // Create logical operations on predicate registers.
261     if (EnableGenPred)
262       addPass(createHexagonGenPredicate(), false);
263     // Rotate loops to expose bit-simplification opportunities.
264     if (EnableLoopResched)
265       addPass(createHexagonLoopRescheduling(), false);
266     // Split double registers.
267     if (!DisableHSDR)
268       addPass(createHexagonSplitDoubleRegs());
269     // Bit simplification.
270     if (EnableBitSimplify)
271       addPass(createHexagonBitSimplify(), false);
272     addPass(createHexagonPeephole());
273     printAndVerify("After hexagon peephole pass");
274     // Constant propagation.
275     if (!DisableHCP) {
276       addPass(createHexagonConstPropagationPass(), false);
277       addPass(&UnreachableMachineBlockElimID, false);
278     }
279     if (EnableGenInsert)
280       addPass(createHexagonGenInsert(), false);
281     if (EnableEarlyIf)
282       addPass(createHexagonEarlyIfConversion(), false);
283   }
284 
285   return false;
286 }
287 
288 void HexagonPassConfig::addPreRegAlloc() {
289   if (getOptLevel() != CodeGenOpt::None) {
290     if (EnableExpandCondsets) {
291       Pass *Exp = createHexagonExpandCondsets();
292       insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
293     }
294     if (!DisableStoreWidening)
295       addPass(createHexagonStoreWidening(), false);
296     if (!DisableHardwareLoops)
297       addPass(createHexagonHardwareLoops(), false);
298   }
299   if (TM->getOptLevel() >= CodeGenOpt::Default)
300     addPass(&MachinePipelinerID);
301 }
302 
303 void HexagonPassConfig::addPostRegAlloc() {
304   if (getOptLevel() != CodeGenOpt::None) {
305     if (EnableRDFOpt)
306       addPass(createHexagonRDFOpt());
307     if (!DisableHexagonCFGOpt)
308       addPass(createHexagonCFGOptimizer(), false);
309     if (!DisableAModeOpt)
310       addPass(createHexagonOptAddrMode(), false);
311   }
312 }
313 
314 void HexagonPassConfig::addPreSched2() {
315   addPass(createHexagonCopyToCombine(), false);
316   if (getOptLevel() != CodeGenOpt::None)
317     addPass(&IfConverterID, false);
318   addPass(createHexagonSplitConst32AndConst64());
319 }
320 
321 void HexagonPassConfig::addPreEmitPass() {
322   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
323 
324   if (!NoOpt)
325     addPass(createHexagonNewValueJump(), false);
326 
327   addPass(createHexagonBranchRelaxation(), false);
328 
329   // Create Packets.
330   if (!NoOpt) {
331     if (!DisableHardwareLoops)
332       addPass(createHexagonFixupHwLoops(), false);
333     // Generate MUX from pairs of conditional transfers.
334     if (EnableGenMux)
335       addPass(createHexagonGenMux(), false);
336 
337     addPass(createHexagonPacketizer(), false);
338   }
339   if (EnableVectorPrint)
340     addPass(createHexagonVectorPrint(), false);
341 
342   // Add CFI instructions if necessary.
343   addPass(createHexagonCallFrameInformation(), false);
344 }
345