1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 
34 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
35   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 
37 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
39   cl::desc("Disable Hexagon Addressing Mode Optimization"));
40 
41 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon CFG Optimization"));
44 
45 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
46   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
47 
48 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
49   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
50 
51 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
52   cl::init(true), cl::Hidden, cl::ZeroOrMore,
53   cl::desc("Early expansion of MUX"));
54 
55 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
56   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
57 
58 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
59   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
60 
61 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
62   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
63 
64 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
65   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
66 
67 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
68   cl::desc("Enable converting conditional transfers into MUX instructions"));
69 
70 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
71   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
72   "predicate instructions"));
73 
74 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
75   cl::init(false), cl::Hidden, cl::ZeroOrMore,
76   cl::desc("Enable loop data prefetch on Hexagon"));
77 
78 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
79   cl::desc("Disable splitting double registers"));
80 
81 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
82   cl::Hidden, cl::desc("Bit simplification"));
83 
84 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
85   cl::Hidden, cl::desc("Loop rescheduling"));
86 
87 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
88   cl::Hidden, cl::desc("Disable backend optimizations"));
89 
90 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
91   cl::Hidden, cl::ZeroOrMore, cl::init(false),
92   cl::desc("Enable Hexagon Vector print instr pass"));
93 
94 /// HexagonTargetMachineModule - Note that this is used on hosts that
95 /// cannot link in a library unless there are references into the
96 /// library.  In particular, it seems that it is not possible to get
97 /// things to work on Win32 without this.  Though it is unused, do not
98 /// remove it.
99 extern "C" int HexagonTargetMachineModule;
100 int HexagonTargetMachineModule = 0;
101 
102 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
103   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
104 }
105 
106 static MachineSchedRegistry
107 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
108                     createVLIWMachineSched);
109 
110 namespace llvm {
111   extern char &HexagonExpandCondsetsID;
112   void initializeHexagonExpandCondsetsPass(PassRegistry&);
113   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
114   void initializeHexagonGenMuxPass(PassRegistry&);
115   void initializeHexagonOptAddrModePass(PassRegistry&);
116   Pass *createHexagonLoopIdiomPass();
117 
118   FunctionPass *createHexagonBitSimplify();
119   FunctionPass *createHexagonBranchRelaxation();
120   FunctionPass *createHexagonCallFrameInformation();
121   FunctionPass *createHexagonCFGOptimizer();
122   FunctionPass *createHexagonCommonGEP();
123   FunctionPass *createHexagonConstPropagationPass();
124   FunctionPass *createHexagonCopyToCombine();
125   FunctionPass *createHexagonEarlyIfConversion();
126   FunctionPass *createHexagonFixupHwLoops();
127   FunctionPass *createHexagonGenExtract();
128   FunctionPass *createHexagonGenInsert();
129   FunctionPass *createHexagonGenMux();
130   FunctionPass *createHexagonGenPredicate();
131   FunctionPass *createHexagonHardwareLoops();
132   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
133                                      CodeGenOpt::Level OptLevel);
134   FunctionPass *createHexagonLoopRescheduling();
135   FunctionPass *createHexagonNewValueJump();
136   FunctionPass *createHexagonOptimizeSZextends();
137   FunctionPass *createHexagonOptAddrMode();
138   FunctionPass *createHexagonPacketizer();
139   FunctionPass *createHexagonPeephole();
140   FunctionPass *createHexagonRDFOpt();
141   FunctionPass *createHexagonSplitConst32AndConst64();
142   FunctionPass *createHexagonSplitDoubleRegs();
143   FunctionPass *createHexagonStoreWidening();
144   FunctionPass *createHexagonVectorPrint();
145 } // end namespace llvm;
146 
147 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
148   if (!RM.hasValue())
149     return Reloc::Static;
150   return *RM;
151 }
152 
153 extern "C" void LLVMInitializeHexagonTarget() {
154   // Register the target.
155   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
156 
157   PassRegistry &PR = *PassRegistry::getPassRegistry();
158   initializeHexagonLoopIdiomRecognizePass(PR);
159   initializeHexagonGenMuxPass(PR);
160   initializeHexagonOptAddrModePass(PR);
161 }
162 
163 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
164                                            StringRef CPU, StringRef FS,
165                                            const TargetOptions &Options,
166                                            Optional<Reloc::Model> RM,
167                                            CodeModel::Model CM,
168                                            CodeGenOpt::Level OL)
169     // Specify the vector alignment explicitly. For v512x1, the calculated
170     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
171     // the required minimum of 64 bytes.
172     : LLVMTargetMachine(
173           T, "e-m:e-p:32:32:32-a:0-n16:32-"
174              "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
175              "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
176           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
177           (HexagonNoOpt ? CodeGenOpt::None : OL)),
178       TLOF(make_unique<HexagonTargetObjectFile>()) {
179   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
180   initAsmInfo();
181 }
182 
183 const HexagonSubtarget *
184 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
185   AttributeList FnAttrs = F.getAttributes();
186   Attribute CPUAttr =
187       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
188   Attribute FSAttr =
189       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
190 
191   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
192                         ? CPUAttr.getValueAsString().str()
193                         : TargetCPU;
194   std::string FS = !FSAttr.hasAttribute(Attribute::None)
195                        ? FSAttr.getValueAsString().str()
196                        : TargetFS;
197 
198   auto &I = SubtargetMap[CPU + FS];
199   if (!I) {
200     // This needs to be done before we create a new subtarget since any
201     // creation will depend on the TM and the code generation flags on the
202     // function that reside in TargetOptions.
203     resetTargetOptions(F);
204     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
205   }
206   return I.get();
207 }
208 
209 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
210   PMB.addExtension(
211     PassManagerBuilder::EP_LateLoopOptimizations,
212     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
213       PM.add(createHexagonLoopIdiomPass());
214     });
215 }
216 
217 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
218   return TargetIRAnalysis([this](const Function &F) {
219     return TargetTransformInfo(HexagonTTIImpl(this, F));
220   });
221 }
222 
223 
224 HexagonTargetMachine::~HexagonTargetMachine() {}
225 
226 namespace {
227 /// Hexagon Code Generator Pass Configuration Options.
228 class HexagonPassConfig : public TargetPassConfig {
229 public:
230   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
231     : TargetPassConfig(TM, PM) {}
232 
233   HexagonTargetMachine &getHexagonTargetMachine() const {
234     return getTM<HexagonTargetMachine>();
235   }
236 
237   ScheduleDAGInstrs *
238   createMachineScheduler(MachineSchedContext *C) const override {
239     return createVLIWMachineSched(C);
240   }
241 
242   void addIRPasses() override;
243   bool addInstSelector() override;
244   void addPreRegAlloc() override;
245   void addPostRegAlloc() override;
246   void addPreSched2() override;
247   void addPreEmitPass() override;
248 };
249 } // namespace
250 
251 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
252   return new HexagonPassConfig(*this, PM);
253 }
254 
255 void HexagonPassConfig::addIRPasses() {
256   TargetPassConfig::addIRPasses();
257   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
258 
259   addPass(createAtomicExpandPass());
260   if (!NoOpt) {
261     if (EnableLoopPrefetch)
262       addPass(createLoopDataPrefetchPass());
263     if (EnableCommGEP)
264       addPass(createHexagonCommonGEP());
265     // Replace certain combinations of shifts and ands with extracts.
266     if (EnableGenExtract)
267       addPass(createHexagonGenExtract());
268   }
269 }
270 
271 bool HexagonPassConfig::addInstSelector() {
272   HexagonTargetMachine &TM = getHexagonTargetMachine();
273   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
274 
275   if (!NoOpt)
276     addPass(createHexagonOptimizeSZextends());
277 
278   addPass(createHexagonISelDag(TM, getOptLevel()));
279 
280   if (!NoOpt) {
281     // Create logical operations on predicate registers.
282     if (EnableGenPred)
283       addPass(createHexagonGenPredicate());
284     // Rotate loops to expose bit-simplification opportunities.
285     if (EnableLoopResched)
286       addPass(createHexagonLoopRescheduling());
287     // Split double registers.
288     if (!DisableHSDR)
289       addPass(createHexagonSplitDoubleRegs());
290     // Bit simplification.
291     if (EnableBitSimplify)
292       addPass(createHexagonBitSimplify());
293     addPass(createHexagonPeephole());
294     // Constant propagation.
295     if (!DisableHCP) {
296       addPass(createHexagonConstPropagationPass());
297       addPass(&UnreachableMachineBlockElimID);
298     }
299     if (EnableGenInsert)
300       addPass(createHexagonGenInsert());
301     if (EnableEarlyIf)
302       addPass(createHexagonEarlyIfConversion());
303   }
304 
305   return false;
306 }
307 
308 void HexagonPassConfig::addPreRegAlloc() {
309   if (getOptLevel() != CodeGenOpt::None) {
310     if (EnableExpandCondsets)
311       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
312     if (!DisableStoreWidening)
313       addPass(createHexagonStoreWidening());
314     if (!DisableHardwareLoops)
315       addPass(createHexagonHardwareLoops());
316   }
317   if (TM->getOptLevel() >= CodeGenOpt::Default)
318     addPass(&MachinePipelinerID);
319 }
320 
321 void HexagonPassConfig::addPostRegAlloc() {
322   if (getOptLevel() != CodeGenOpt::None) {
323     if (EnableRDFOpt)
324       addPass(createHexagonRDFOpt());
325     if (!DisableHexagonCFGOpt)
326       addPass(createHexagonCFGOptimizer());
327     if (!DisableAModeOpt)
328       addPass(createHexagonOptAddrMode());
329   }
330 }
331 
332 void HexagonPassConfig::addPreSched2() {
333   addPass(createHexagonCopyToCombine());
334   if (getOptLevel() != CodeGenOpt::None)
335     addPass(&IfConverterID);
336   addPass(createHexagonSplitConst32AndConst64());
337 }
338 
339 void HexagonPassConfig::addPreEmitPass() {
340   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
341 
342   if (!NoOpt)
343     addPass(createHexagonNewValueJump());
344 
345   addPass(createHexagonBranchRelaxation());
346 
347   // Create Packets.
348   if (!NoOpt) {
349     if (!DisableHardwareLoops)
350       addPass(createHexagonFixupHwLoops());
351     // Generate MUX from pairs of conditional transfers.
352     if (EnableGenMux)
353       addPass(createHexagonGenMux());
354 
355     addPass(createHexagonPacketizer(), false);
356   }
357   if (EnableVectorPrint)
358     addPass(createHexagonVectorPrint(), false);
359 
360   // Add CFI instructions if necessary.
361   addPass(createHexagonCallFrameInformation(), false);
362 }
363