1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
16 #include "HexagonLoopIdiomRecognition.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "HexagonVectorLoopCarriedReuse.h"
21 #include "TargetInfo/HexagonTargetInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/CodeGen/VLIWMachineScheduler.h"
25 #include "llvm/IR/LegacyPassManager.h"
26 #include "llvm/IR/Module.h"
27 #include "llvm/MC/TargetRegistry.h"
28 #include "llvm/Passes/PassBuilder.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
31 #include "llvm/Transforms/Scalar.h"
32 
33 using namespace llvm;
34 
35 static cl::opt<bool>
36     EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true),
37                   cl::desc("Enable Hexagon constant-extender optimization"));
38 
39 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true),
40                                   cl::desc("Enable RDF-based optimizations"));
41 
42 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
43   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
44 
45 static cl::opt<bool>
46     DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
47                     cl::desc("Disable Hexagon Addressing Mode Optimization"));
48 
49 static cl::opt<bool>
50     DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
51                          cl::desc("Disable Hexagon CFG Optimization"));
52 
53 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
54   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
55 
56 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
57   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
58 
59 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
60                                           cl::init(true), cl::Hidden,
61                                           cl::desc("Early expansion of MUX"));
62 
63 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
64   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
65 
66 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
67   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
68 
69 static cl::opt<bool>
70     EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden,
71                   cl::desc("Enable commoning of GEP instructions"));
72 
73 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
74   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
75 
76 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
77   cl::desc("Enable converting conditional transfers into MUX instructions"));
78 
79 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
80   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
81   "predicate instructions"));
82 
83 static cl::opt<bool>
84     EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
85                        cl::desc("Enable loop data prefetch on Hexagon"));
86 
87 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
88   cl::desc("Disable splitting double registers"));
89 
90 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
91   cl::Hidden, cl::desc("Bit simplification"));
92 
93 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
94   cl::Hidden, cl::desc("Loop rescheduling"));
95 
96 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
97   cl::Hidden, cl::desc("Disable backend optimizations"));
98 
99 static cl::opt<bool>
100     EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
101                       cl::desc("Enable Hexagon Vector print instr pass"));
102 
103 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
104   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
105 
106 static cl::opt<bool> EnableVectorCombine("hexagon-vector-combine", cl::Hidden,
107   cl::ZeroOrMore, cl::init(true), cl::desc("Enable HVX vector combining"));
108 
109 static cl::opt<bool> EnableInitialCFGCleanup(
110     "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true),
111     cl::desc("Simplify the CFG after atomic expansion pass"));
112 
113 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
114                                         cl::ZeroOrMore, cl::init(true),
115                                         cl::desc("Enable instsimplify"));
116 
117 /// HexagonTargetMachineModule - Note that this is used on hosts that
118 /// cannot link in a library unless there are references into the
119 /// library.  In particular, it seems that it is not possible to get
120 /// things to work on Win32 without this.  Though it is unused, do not
121 /// remove it.
122 extern "C" int HexagonTargetMachineModule;
123 int HexagonTargetMachineModule = 0;
124 
125 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
126   ScheduleDAGMILive *DAG = new VLIWMachineScheduler(
127       C, std::make_unique<HexagonConvergingVLIWScheduler>());
128   DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
129   DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
130   DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
131   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
132   return DAG;
133 }
134 
135 static MachineSchedRegistry
136 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
137                     createVLIWMachineSched);
138 
139 namespace llvm {
140   extern char &HexagonExpandCondsetsID;
141   void initializeHexagonBitSimplifyPass(PassRegistry&);
142   void initializeHexagonConstExtendersPass(PassRegistry&);
143   void initializeHexagonConstPropagationPass(PassRegistry&);
144   void initializeHexagonCopyToCombinePass(PassRegistry&);
145   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
146   void initializeHexagonExpandCondsetsPass(PassRegistry&);
147   void initializeHexagonGenMuxPass(PassRegistry&);
148   void initializeHexagonHardwareLoopsPass(PassRegistry&);
149   void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &);
150   void initializeHexagonNewValueJumpPass(PassRegistry&);
151   void initializeHexagonOptAddrModePass(PassRegistry&);
152   void initializeHexagonPacketizerPass(PassRegistry&);
153   void initializeHexagonRDFOptPass(PassRegistry&);
154   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
155   void initializeHexagonVectorCombineLegacyPass(PassRegistry&);
156   void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &);
157   void initializeHexagonVExtractPass(PassRegistry&);
158   Pass *createHexagonLoopIdiomPass();
159   Pass *createHexagonVectorLoopCarriedReuseLegacyPass();
160 
161   FunctionPass *createHexagonBitSimplify();
162   FunctionPass *createHexagonBranchRelaxation();
163   FunctionPass *createHexagonCallFrameInformation();
164   FunctionPass *createHexagonCFGOptimizer();
165   FunctionPass *createHexagonCommonGEP();
166   FunctionPass *createHexagonConstExtenders();
167   FunctionPass *createHexagonConstPropagationPass();
168   FunctionPass *createHexagonCopyToCombine();
169   FunctionPass *createHexagonEarlyIfConversion();
170   FunctionPass *createHexagonFixupHwLoops();
171   FunctionPass *createHexagonGenExtract();
172   FunctionPass *createHexagonGenInsert();
173   FunctionPass *createHexagonGenMux();
174   FunctionPass *createHexagonGenPredicate();
175   FunctionPass *createHexagonHardwareLoops();
176   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
177                                      CodeGenOpt::Level OptLevel);
178   FunctionPass *createHexagonLoopRescheduling();
179   FunctionPass *createHexagonNewValueJump();
180   FunctionPass *createHexagonOptAddrMode();
181   FunctionPass *createHexagonOptimizeSZextends();
182   FunctionPass *createHexagonPacketizer(bool Minimal);
183   FunctionPass *createHexagonPeephole();
184   FunctionPass *createHexagonRDFOpt();
185   FunctionPass *createHexagonSplitConst32AndConst64();
186   FunctionPass *createHexagonSplitDoubleRegs();
187   FunctionPass *createHexagonStoreWidening();
188   FunctionPass *createHexagonVectorCombineLegacyPass();
189   FunctionPass *createHexagonVectorPrint();
190   FunctionPass *createHexagonVExtract();
191 } // end namespace llvm;
192 
193 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
194   return RM.getValueOr(Reloc::Static);
195 }
196 
197 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() {
198   // Register the target.
199   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
200 
201   PassRegistry &PR = *PassRegistry::getPassRegistry();
202   initializeHexagonBitSimplifyPass(PR);
203   initializeHexagonConstExtendersPass(PR);
204   initializeHexagonConstPropagationPass(PR);
205   initializeHexagonCopyToCombinePass(PR);
206   initializeHexagonEarlyIfConversionPass(PR);
207   initializeHexagonGenMuxPass(PR);
208   initializeHexagonHardwareLoopsPass(PR);
209   initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR);
210   initializeHexagonNewValueJumpPass(PR);
211   initializeHexagonOptAddrModePass(PR);
212   initializeHexagonPacketizerPass(PR);
213   initializeHexagonRDFOptPass(PR);
214   initializeHexagonSplitDoubleRegsPass(PR);
215   initializeHexagonVectorCombineLegacyPass(PR);
216   initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR);
217   initializeHexagonVExtractPass(PR);
218 }
219 
220 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
221                                            StringRef CPU, StringRef FS,
222                                            const TargetOptions &Options,
223                                            Optional<Reloc::Model> RM,
224                                            Optional<CodeModel::Model> CM,
225                                            CodeGenOpt::Level OL, bool JIT)
226     // Specify the vector alignment explicitly. For v512x1, the calculated
227     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
228     // the required minimum of 64 bytes.
229     : LLVMTargetMachine(
230           T,
231           "e-m:e-p:32:32:32-a:0-n16:32-"
232           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
233           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
234           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
235           getEffectiveCodeModel(CM, CodeModel::Small),
236           (HexagonNoOpt ? CodeGenOpt::None : OL)),
237       TLOF(std::make_unique<HexagonTargetObjectFile>()) {
238   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
239   initAsmInfo();
240 }
241 
242 const HexagonSubtarget *
243 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
244   AttributeList FnAttrs = F.getAttributes();
245   Attribute CPUAttr =
246       FnAttrs.getFnAttr("target-cpu");
247   Attribute FSAttr =
248       FnAttrs.getFnAttr("target-features");
249 
250   std::string CPU =
251       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
252   std::string FS =
253       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
254   // Append the preexisting target features last, so that +mattr overrides
255   // the "unsafe-fp-math" function attribute.
256   // Creating a separate target feature is not strictly necessary, it only
257   // exists to make "unsafe-fp-math" force creating a new subtarget.
258 
259   if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
260     FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
261 
262   auto &I = SubtargetMap[CPU + FS];
263   if (!I) {
264     // This needs to be done before we create a new subtarget since any
265     // creation will depend on the TM and the code generation flags on the
266     // function that reside in TargetOptions.
267     resetTargetOptions(F);
268     I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
269   }
270   return I.get();
271 }
272 
273 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
274   PMB.addExtension(
275     PassManagerBuilder::EP_LateLoopOptimizations,
276     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
277       PM.add(createHexagonLoopIdiomPass());
278     });
279   PMB.addExtension(
280       PassManagerBuilder::EP_LoopOptimizerEnd,
281       [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
282         PM.add(createHexagonVectorLoopCarriedReuseLegacyPass());
283       });
284 }
285 
286 void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
287   PB.registerLateLoopOptimizationsEPCallback(
288       [=](LoopPassManager &LPM, OptimizationLevel Level) {
289         LPM.addPass(HexagonLoopIdiomRecognitionPass());
290       });
291   PB.registerLoopOptimizerEndEPCallback(
292       [=](LoopPassManager &LPM, OptimizationLevel Level) {
293         LPM.addPass(HexagonVectorLoopCarriedReusePass());
294       });
295 }
296 
297 TargetTransformInfo
298 HexagonTargetMachine::getTargetTransformInfo(const Function &F) const {
299   return TargetTransformInfo(HexagonTTIImpl(this, F));
300 }
301 
302 HexagonTargetMachine::~HexagonTargetMachine() = default;
303 
304 namespace {
305 /// Hexagon Code Generator Pass Configuration Options.
306 class HexagonPassConfig : public TargetPassConfig {
307 public:
308   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
309     : TargetPassConfig(TM, PM) {}
310 
311   HexagonTargetMachine &getHexagonTargetMachine() const {
312     return getTM<HexagonTargetMachine>();
313   }
314 
315   ScheduleDAGInstrs *
316   createMachineScheduler(MachineSchedContext *C) const override {
317     return createVLIWMachineSched(C);
318   }
319 
320   void addIRPasses() override;
321   bool addInstSelector() override;
322   void addPreRegAlloc() override;
323   void addPostRegAlloc() override;
324   void addPreSched2() override;
325   void addPreEmitPass() override;
326 };
327 } // namespace
328 
329 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
330   return new HexagonPassConfig(*this, PM);
331 }
332 
333 void HexagonPassConfig::addIRPasses() {
334   TargetPassConfig::addIRPasses();
335   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
336 
337   if (!NoOpt) {
338     if (EnableInstSimplify)
339       addPass(createInstSimplifyLegacyPass());
340     addPass(createDeadCodeEliminationPass());
341   }
342 
343   addPass(createAtomicExpandPass());
344 
345   if (!NoOpt) {
346     if (EnableInitialCFGCleanup)
347       addPass(createCFGSimplificationPass(SimplifyCFGOptions()
348                                               .forwardSwitchCondToPhi(true)
349                                               .convertSwitchRangeToICmp(true)
350                                               .convertSwitchToLookupTable(true)
351                                               .needCanonicalLoops(false)
352                                               .hoistCommonInsts(true)
353                                               .sinkCommonInsts(true)));
354     if (EnableLoopPrefetch)
355       addPass(createLoopDataPrefetchPass());
356     if (EnableVectorCombine)
357       addPass(createHexagonVectorCombineLegacyPass());
358     if (EnableCommGEP)
359       addPass(createHexagonCommonGEP());
360     // Replace certain combinations of shifts and ands with extracts.
361     if (EnableGenExtract)
362       addPass(createHexagonGenExtract());
363   }
364 }
365 
366 bool HexagonPassConfig::addInstSelector() {
367   HexagonTargetMachine &TM = getHexagonTargetMachine();
368   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
369 
370   if (!NoOpt)
371     addPass(createHexagonOptimizeSZextends());
372 
373   addPass(createHexagonISelDag(TM, getOptLevel()));
374 
375   if (!NoOpt) {
376     if (EnableVExtractOpt)
377       addPass(createHexagonVExtract());
378     // Create logical operations on predicate registers.
379     if (EnableGenPred)
380       addPass(createHexagonGenPredicate());
381     // Rotate loops to expose bit-simplification opportunities.
382     if (EnableLoopResched)
383       addPass(createHexagonLoopRescheduling());
384     // Split double registers.
385     if (!DisableHSDR)
386       addPass(createHexagonSplitDoubleRegs());
387     // Bit simplification.
388     if (EnableBitSimplify)
389       addPass(createHexagonBitSimplify());
390     addPass(createHexagonPeephole());
391     // Constant propagation.
392     if (!DisableHCP) {
393       addPass(createHexagonConstPropagationPass());
394       addPass(&UnreachableMachineBlockElimID);
395     }
396     if (EnableGenInsert)
397       addPass(createHexagonGenInsert());
398     if (EnableEarlyIf)
399       addPass(createHexagonEarlyIfConversion());
400   }
401 
402   return false;
403 }
404 
405 void HexagonPassConfig::addPreRegAlloc() {
406   if (getOptLevel() != CodeGenOpt::None) {
407     if (EnableCExtOpt)
408       addPass(createHexagonConstExtenders());
409     if (EnableExpandCondsets)
410       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
411     if (!DisableStoreWidening)
412       addPass(createHexagonStoreWidening());
413     if (!DisableHardwareLoops)
414       addPass(createHexagonHardwareLoops());
415   }
416   if (TM->getOptLevel() >= CodeGenOpt::Default)
417     addPass(&MachinePipelinerID);
418 }
419 
420 void HexagonPassConfig::addPostRegAlloc() {
421   if (getOptLevel() != CodeGenOpt::None) {
422     if (EnableRDFOpt)
423       addPass(createHexagonRDFOpt());
424     if (!DisableHexagonCFGOpt)
425       addPass(createHexagonCFGOptimizer());
426     if (!DisableAModeOpt)
427       addPass(createHexagonOptAddrMode());
428   }
429 }
430 
431 void HexagonPassConfig::addPreSched2() {
432   addPass(createHexagonCopyToCombine());
433   if (getOptLevel() != CodeGenOpt::None)
434     addPass(&IfConverterID);
435   addPass(createHexagonSplitConst32AndConst64());
436 }
437 
438 void HexagonPassConfig::addPreEmitPass() {
439   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
440 
441   if (!NoOpt)
442     addPass(createHexagonNewValueJump());
443 
444   addPass(createHexagonBranchRelaxation());
445 
446   if (!NoOpt) {
447     if (!DisableHardwareLoops)
448       addPass(createHexagonFixupHwLoops());
449     // Generate MUX from pairs of conditional transfers.
450     if (EnableGenMux)
451       addPass(createHexagonGenMux());
452   }
453 
454   // Packetization is mandatory: it handles gather/scatter at all opt levels.
455   addPass(createHexagonPacketizer(NoOpt));
456 
457   if (EnableVectorPrint)
458     addPass(createHexagonVectorPrint());
459 
460   // Add CFI instructions if necessary.
461   addPass(createHexagonCallFrameInformation());
462 }
463