1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
33 
34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
35   cl::init(true), cl::desc("Enable RDF-based optimizations"));
36 
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
39 
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon Addressing Mode Optimization"));
43 
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon CFG Optimization"));
47 
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
50 
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
53 
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55   cl::init(true), cl::Hidden, cl::ZeroOrMore,
56   cl::desc("Early expansion of MUX"));
57 
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
60 
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
63 
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
66 
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
69 
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71   cl::desc("Enable converting conditional transfers into MUX instructions"));
72 
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75   "predicate instructions"));
76 
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78   cl::init(false), cl::Hidden, cl::ZeroOrMore,
79   cl::desc("Enable loop data prefetch on Hexagon"));
80 
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82   cl::desc("Disable splitting double registers"));
83 
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85   cl::Hidden, cl::desc("Bit simplification"));
86 
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88   cl::Hidden, cl::desc("Loop rescheduling"));
89 
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91   cl::Hidden, cl::desc("Disable backend optimizations"));
92 
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94   cl::Hidden, cl::ZeroOrMore, cl::init(false),
95   cl::desc("Enable Hexagon Vector print instr pass"));
96 
97 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
98   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
99 
100 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
101   cl::Hidden, cl::ZeroOrMore, cl::init(true),
102   cl::desc("Simplify the CFG after atomic expansion pass"));
103 
104 /// HexagonTargetMachineModule - Note that this is used on hosts that
105 /// cannot link in a library unless there are references into the
106 /// library.  In particular, it seems that it is not possible to get
107 /// things to work on Win32 without this.  Though it is unused, do not
108 /// remove it.
109 extern "C" int HexagonTargetMachineModule;
110 int HexagonTargetMachineModule = 0;
111 
112 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
113   ScheduleDAGMILive *DAG =
114     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
115   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
116   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
117   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
118   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
119   return DAG;
120 }
121 
122 static MachineSchedRegistry
123 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
124                     createVLIWMachineSched);
125 
126 namespace llvm {
127   extern char &HexagonExpandCondsetsID;
128   void initializeHexagonBitSimplifyPass(PassRegistry&);
129   void initializeHexagonConstExtendersPass(PassRegistry&);
130   void initializeHexagonConstPropagationPass(PassRegistry&);
131   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
132   void initializeHexagonExpandCondsetsPass(PassRegistry&);
133   void initializeHexagonGenMuxPass(PassRegistry&);
134   void initializeHexagonHardwareLoopsPass(PassRegistry&);
135   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
136   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
137   void initializeHexagonNewValueJumpPass(PassRegistry&);
138   void initializeHexagonOptAddrModePass(PassRegistry&);
139   void initializeHexagonPacketizerPass(PassRegistry&);
140   void initializeHexagonRDFOptPass(PassRegistry&);
141   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
142   void initializeHexagonVExtractPass(PassRegistry&);
143   Pass *createHexagonLoopIdiomPass();
144   Pass *createHexagonVectorLoopCarriedReusePass();
145 
146   FunctionPass *createHexagonBitSimplify();
147   FunctionPass *createHexagonBranchRelaxation();
148   FunctionPass *createHexagonCallFrameInformation();
149   FunctionPass *createHexagonCFGOptimizer();
150   FunctionPass *createHexagonCommonGEP();
151   FunctionPass *createHexagonConstExtenders();
152   FunctionPass *createHexagonConstPropagationPass();
153   FunctionPass *createHexagonCopyToCombine();
154   FunctionPass *createHexagonEarlyIfConversion();
155   FunctionPass *createHexagonFixupHwLoops();
156   FunctionPass *createHexagonGenExtract();
157   FunctionPass *createHexagonGenInsert();
158   FunctionPass *createHexagonGenMux();
159   FunctionPass *createHexagonGenPredicate();
160   FunctionPass *createHexagonHardwareLoops();
161   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
162                                      CodeGenOpt::Level OptLevel);
163   FunctionPass *createHexagonLoopRescheduling();
164   FunctionPass *createHexagonNewValueJump();
165   FunctionPass *createHexagonOptimizeSZextends();
166   FunctionPass *createHexagonOptAddrMode();
167   FunctionPass *createHexagonPacketizer(bool Minimal);
168   FunctionPass *createHexagonPeephole();
169   FunctionPass *createHexagonRDFOpt();
170   FunctionPass *createHexagonSplitConst32AndConst64();
171   FunctionPass *createHexagonSplitDoubleRegs();
172   FunctionPass *createHexagonStoreWidening();
173   FunctionPass *createHexagonVectorPrint();
174   FunctionPass *createHexagonVExtract();
175 } // end namespace llvm;
176 
177 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
178   if (!RM.hasValue())
179     return Reloc::Static;
180   return *RM;
181 }
182 
183 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
184   if (CM)
185     return *CM;
186   return CodeModel::Small;
187 }
188 
189 extern "C" void LLVMInitializeHexagonTarget() {
190   // Register the target.
191   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
192 
193   PassRegistry &PR = *PassRegistry::getPassRegistry();
194   initializeHexagonBitSimplifyPass(PR);
195   initializeHexagonConstExtendersPass(PR);
196   initializeHexagonConstPropagationPass(PR);
197   initializeHexagonEarlyIfConversionPass(PR);
198   initializeHexagonGenMuxPass(PR);
199   initializeHexagonHardwareLoopsPass(PR);
200   initializeHexagonLoopIdiomRecognizePass(PR);
201   initializeHexagonVectorLoopCarriedReusePass(PR);
202   initializeHexagonNewValueJumpPass(PR);
203   initializeHexagonOptAddrModePass(PR);
204   initializeHexagonPacketizerPass(PR);
205   initializeHexagonRDFOptPass(PR);
206   initializeHexagonSplitDoubleRegsPass(PR);
207   initializeHexagonVExtractPass(PR);
208 }
209 
210 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
211                                            StringRef CPU, StringRef FS,
212                                            const TargetOptions &Options,
213                                            Optional<Reloc::Model> RM,
214                                            Optional<CodeModel::Model> CM,
215                                            CodeGenOpt::Level OL, bool JIT)
216     // Specify the vector alignment explicitly. For v512x1, the calculated
217     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
218     // the required minimum of 64 bytes.
219     : LLVMTargetMachine(
220           T,
221           "e-m:e-p:32:32:32-a:0-n16:32-"
222           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
223           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
224           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
225           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
226       TLOF(make_unique<HexagonTargetObjectFile>()) {
227   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
228   initAsmInfo();
229 }
230 
231 const HexagonSubtarget *
232 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
233   AttributeList FnAttrs = F.getAttributes();
234   Attribute CPUAttr =
235       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
236   Attribute FSAttr =
237       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
238 
239   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
240                         ? CPUAttr.getValueAsString().str()
241                         : TargetCPU;
242   std::string FS = !FSAttr.hasAttribute(Attribute::None)
243                        ? FSAttr.getValueAsString().str()
244                        : TargetFS;
245 
246   auto &I = SubtargetMap[CPU + FS];
247   if (!I) {
248     // This needs to be done before we create a new subtarget since any
249     // creation will depend on the TM and the code generation flags on the
250     // function that reside in TargetOptions.
251     resetTargetOptions(F);
252     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
253   }
254   return I.get();
255 }
256 
257 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
258   PMB.addExtension(
259     PassManagerBuilder::EP_LateLoopOptimizations,
260     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
261       PM.add(createHexagonLoopIdiomPass());
262     });
263   PMB.addExtension(
264     PassManagerBuilder::EP_LoopOptimizerEnd,
265     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
266       PM.add(createHexagonVectorLoopCarriedReusePass());
267     });
268 }
269 
270 TargetTransformInfo
271 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
272   return TargetTransformInfo(HexagonTTIImpl(this, F));
273 }
274 
275 
276 HexagonTargetMachine::~HexagonTargetMachine() {}
277 
278 namespace {
279 /// Hexagon Code Generator Pass Configuration Options.
280 class HexagonPassConfig : public TargetPassConfig {
281 public:
282   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
283     : TargetPassConfig(TM, PM) {}
284 
285   HexagonTargetMachine &getHexagonTargetMachine() const {
286     return getTM<HexagonTargetMachine>();
287   }
288 
289   ScheduleDAGInstrs *
290   createMachineScheduler(MachineSchedContext *C) const override {
291     return createVLIWMachineSched(C);
292   }
293 
294   void addIRPasses() override;
295   bool addInstSelector() override;
296   void addPreRegAlloc() override;
297   void addPostRegAlloc() override;
298   void addPreSched2() override;
299   void addPreEmitPass() override;
300 };
301 } // namespace
302 
303 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
304   return new HexagonPassConfig(*this, PM);
305 }
306 
307 void HexagonPassConfig::addIRPasses() {
308   TargetPassConfig::addIRPasses();
309   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
310 
311   if (!NoOpt) {
312     addPass(createConstantPropagationPass());
313     addPass(createDeadCodeEliminationPass());
314   }
315 
316   addPass(createAtomicExpandPass());
317 
318   if (!NoOpt) {
319     if (EnableInitialCFGCleanup)
320       addPass(createCFGSimplificationPass(1, true, true, false, true));
321     if (EnableLoopPrefetch)
322       addPass(createLoopDataPrefetchPass());
323     if (EnableCommGEP)
324       addPass(createHexagonCommonGEP());
325     // Replace certain combinations of shifts and ands with extracts.
326     if (EnableGenExtract)
327       addPass(createHexagonGenExtract());
328   }
329 }
330 
331 bool HexagonPassConfig::addInstSelector() {
332   HexagonTargetMachine &TM = getHexagonTargetMachine();
333   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
334 
335   if (!NoOpt)
336     addPass(createHexagonOptimizeSZextends());
337 
338   addPass(createHexagonISelDag(TM, getOptLevel()));
339 
340   if (!NoOpt) {
341     if (EnableVExtractOpt)
342       addPass(createHexagonVExtract());
343     // Create logical operations on predicate registers.
344     if (EnableGenPred)
345       addPass(createHexagonGenPredicate());
346     // Rotate loops to expose bit-simplification opportunities.
347     if (EnableLoopResched)
348       addPass(createHexagonLoopRescheduling());
349     // Split double registers.
350     if (!DisableHSDR)
351       addPass(createHexagonSplitDoubleRegs());
352     // Bit simplification.
353     if (EnableBitSimplify)
354       addPass(createHexagonBitSimplify());
355     addPass(createHexagonPeephole());
356     // Constant propagation.
357     if (!DisableHCP) {
358       addPass(createHexagonConstPropagationPass());
359       addPass(&UnreachableMachineBlockElimID);
360     }
361     if (EnableGenInsert)
362       addPass(createHexagonGenInsert());
363     if (EnableEarlyIf)
364       addPass(createHexagonEarlyIfConversion());
365   }
366 
367   return false;
368 }
369 
370 void HexagonPassConfig::addPreRegAlloc() {
371   if (getOptLevel() != CodeGenOpt::None) {
372     if (EnableCExtOpt)
373       addPass(createHexagonConstExtenders());
374     if (EnableExpandCondsets)
375       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
376     if (!DisableStoreWidening)
377       addPass(createHexagonStoreWidening());
378     if (!DisableHardwareLoops)
379       addPass(createHexagonHardwareLoops());
380   }
381   if (TM->getOptLevel() >= CodeGenOpt::Default)
382     addPass(&MachinePipelinerID);
383 }
384 
385 void HexagonPassConfig::addPostRegAlloc() {
386   if (getOptLevel() != CodeGenOpt::None) {
387     if (EnableRDFOpt)
388       addPass(createHexagonRDFOpt());
389     if (!DisableHexagonCFGOpt)
390       addPass(createHexagonCFGOptimizer());
391     if (!DisableAModeOpt)
392       addPass(createHexagonOptAddrMode());
393   }
394 }
395 
396 void HexagonPassConfig::addPreSched2() {
397   addPass(createHexagonCopyToCombine());
398   if (getOptLevel() != CodeGenOpt::None)
399     addPass(&IfConverterID);
400   addPass(createHexagonSplitConst32AndConst64());
401 }
402 
403 void HexagonPassConfig::addPreEmitPass() {
404   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
405 
406   if (!NoOpt)
407     addPass(createHexagonNewValueJump());
408 
409   addPass(createHexagonBranchRelaxation());
410 
411   if (!NoOpt) {
412     if (!DisableHardwareLoops)
413       addPass(createHexagonFixupHwLoops());
414     // Generate MUX from pairs of conditional transfers.
415     if (EnableGenMux)
416       addPass(createHexagonGenMux());
417   }
418 
419   // Packetization is mandatory: it handles gather/scatter at all opt levels.
420   addPass(createHexagonPacketizer(NoOpt), false);
421 
422   if (EnableVectorPrint)
423     addPass(createHexagonVectorPrint(), false);
424 
425   // Add CFI instructions if necessary.
426   addPass(createHexagonCallFrameInformation(), false);
427 }
428