1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 
34 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
35   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 
37 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
39   cl::desc("Disable Hexagon Addressing Mode Optimization"));
40 
41 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon CFG Optimization"));
44 
45 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
46   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
47 
48 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
49   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
50 
51 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
52   cl::init(true), cl::Hidden, cl::ZeroOrMore,
53   cl::desc("Early expansion of MUX"));
54 
55 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
56   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
57 
58 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
59   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
60 
61 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
62   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
63 
64 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
65   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
66 
67 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
68   cl::desc("Enable converting conditional transfers into MUX instructions"));
69 
70 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
71   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
72   "predicate instructions"));
73 
74 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
75   cl::init(false), cl::Hidden, cl::ZeroOrMore,
76   cl::desc("Enable loop data prefetch on Hexagon"));
77 
78 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
79   cl::desc("Disable splitting double registers"));
80 
81 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
82   cl::Hidden, cl::desc("Bit simplification"));
83 
84 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
85   cl::Hidden, cl::desc("Loop rescheduling"));
86 
87 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
88   cl::Hidden, cl::desc("Disable backend optimizations"));
89 
90 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
91   cl::Hidden, cl::ZeroOrMore, cl::init(false),
92   cl::desc("Enable Hexagon Vector print instr pass"));
93 
94 /// HexagonTargetMachineModule - Note that this is used on hosts that
95 /// cannot link in a library unless there are references into the
96 /// library.  In particular, it seems that it is not possible to get
97 /// things to work on Win32 without this.  Though it is unused, do not
98 /// remove it.
99 extern "C" int HexagonTargetMachineModule;
100 int HexagonTargetMachineModule = 0;
101 
102 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
103   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
104 }
105 
106 static MachineSchedRegistry
107 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
108                     createVLIWMachineSched);
109 
110 namespace llvm {
111   extern char &HexagonExpandCondsetsID;
112   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
113   void initializeHexagonExpandCondsetsPass(PassRegistry&);
114   void initializeHexagonGenMuxPass(PassRegistry&);
115   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
116   void initializeHexagonNewValueJumpPass(PassRegistry&);
117   void initializeHexagonOptAddrModePass(PassRegistry&);
118   void initializeHexagonPacketizerPass(PassRegistry&);
119   Pass *createHexagonLoopIdiomPass();
120 
121   FunctionPass *createHexagonBitSimplify();
122   FunctionPass *createHexagonBranchRelaxation();
123   FunctionPass *createHexagonCallFrameInformation();
124   FunctionPass *createHexagonCFGOptimizer();
125   FunctionPass *createHexagonCommonGEP();
126   FunctionPass *createHexagonConstPropagationPass();
127   FunctionPass *createHexagonCopyToCombine();
128   FunctionPass *createHexagonEarlyIfConversion();
129   FunctionPass *createHexagonFixupHwLoops();
130   FunctionPass *createHexagonGenExtract();
131   FunctionPass *createHexagonGenInsert();
132   FunctionPass *createHexagonGenMux();
133   FunctionPass *createHexagonGenPredicate();
134   FunctionPass *createHexagonHardwareLoops();
135   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
136                                      CodeGenOpt::Level OptLevel);
137   FunctionPass *createHexagonLoopRescheduling();
138   FunctionPass *createHexagonNewValueJump();
139   FunctionPass *createHexagonOptimizeSZextends();
140   FunctionPass *createHexagonOptAddrMode();
141   FunctionPass *createHexagonPacketizer();
142   FunctionPass *createHexagonPeephole();
143   FunctionPass *createHexagonRDFOpt();
144   FunctionPass *createHexagonSplitConst32AndConst64();
145   FunctionPass *createHexagonSplitDoubleRegs();
146   FunctionPass *createHexagonStoreWidening();
147   FunctionPass *createHexagonVectorPrint();
148 } // end namespace llvm;
149 
150 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
151   if (!RM.hasValue())
152     return Reloc::Static;
153   return *RM;
154 }
155 
156 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
157   if (CM)
158     return *CM;
159   return CodeModel::Small;
160 }
161 
162 extern "C" void LLVMInitializeHexagonTarget() {
163   // Register the target.
164   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
165 
166   PassRegistry &PR = *PassRegistry::getPassRegistry();
167   initializeHexagonEarlyIfConversionPass(PR);
168   initializeHexagonGenMuxPass(PR);
169   initializeHexagonLoopIdiomRecognizePass(PR);
170   initializeHexagonNewValueJumpPass(PR);
171   initializeHexagonOptAddrModePass(PR);
172   initializeHexagonPacketizerPass(PR);
173 }
174 
175 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
176                                            StringRef CPU, StringRef FS,
177                                            const TargetOptions &Options,
178                                            Optional<Reloc::Model> RM,
179                                            Optional<CodeModel::Model> CM,
180                                            CodeGenOpt::Level OL, bool JIT)
181     // Specify the vector alignment explicitly. For v512x1, the calculated
182     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
183     // the required minimum of 64 bytes.
184     : LLVMTargetMachine(
185           T,
186           "e-m:e-p:32:32:32-a:0-n16:32-"
187           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
188           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
189           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
190           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
191       TLOF(make_unique<HexagonTargetObjectFile>()) {
192   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
193   initAsmInfo();
194 }
195 
196 const HexagonSubtarget *
197 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
198   AttributeList FnAttrs = F.getAttributes();
199   Attribute CPUAttr =
200       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
201   Attribute FSAttr =
202       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
203 
204   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
205                         ? CPUAttr.getValueAsString().str()
206                         : TargetCPU;
207   std::string FS = !FSAttr.hasAttribute(Attribute::None)
208                        ? FSAttr.getValueAsString().str()
209                        : TargetFS;
210 
211   auto &I = SubtargetMap[CPU + FS];
212   if (!I) {
213     // This needs to be done before we create a new subtarget since any
214     // creation will depend on the TM and the code generation flags on the
215     // function that reside in TargetOptions.
216     resetTargetOptions(F);
217     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
218   }
219   return I.get();
220 }
221 
222 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
223   PMB.addExtension(
224     PassManagerBuilder::EP_LateLoopOptimizations,
225     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
226       PM.add(createHexagonLoopIdiomPass());
227     });
228 }
229 
230 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
231   return TargetIRAnalysis([this](const Function &F) {
232     return TargetTransformInfo(HexagonTTIImpl(this, F));
233   });
234 }
235 
236 
237 HexagonTargetMachine::~HexagonTargetMachine() {}
238 
239 namespace {
240 /// Hexagon Code Generator Pass Configuration Options.
241 class HexagonPassConfig : public TargetPassConfig {
242 public:
243   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
244     : TargetPassConfig(TM, PM) {}
245 
246   HexagonTargetMachine &getHexagonTargetMachine() const {
247     return getTM<HexagonTargetMachine>();
248   }
249 
250   ScheduleDAGInstrs *
251   createMachineScheduler(MachineSchedContext *C) const override {
252     return createVLIWMachineSched(C);
253   }
254 
255   void addIRPasses() override;
256   bool addInstSelector() override;
257   void addPreRegAlloc() override;
258   void addPostRegAlloc() override;
259   void addPreSched2() override;
260   void addPreEmitPass() override;
261 };
262 } // namespace
263 
264 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
265   return new HexagonPassConfig(*this, PM);
266 }
267 
268 void HexagonPassConfig::addIRPasses() {
269   TargetPassConfig::addIRPasses();
270   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
271 
272   addPass(createAtomicExpandPass());
273   if (!NoOpt) {
274     if (EnableLoopPrefetch)
275       addPass(createLoopDataPrefetchPass());
276     if (EnableCommGEP)
277       addPass(createHexagonCommonGEP());
278     // Replace certain combinations of shifts and ands with extracts.
279     if (EnableGenExtract)
280       addPass(createHexagonGenExtract());
281   }
282 }
283 
284 bool HexagonPassConfig::addInstSelector() {
285   HexagonTargetMachine &TM = getHexagonTargetMachine();
286   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
287 
288   if (!NoOpt)
289     addPass(createHexagonOptimizeSZextends());
290 
291   addPass(createHexagonISelDag(TM, getOptLevel()));
292 
293   if (!NoOpt) {
294     // Create logical operations on predicate registers.
295     if (EnableGenPred)
296       addPass(createHexagonGenPredicate());
297     // Rotate loops to expose bit-simplification opportunities.
298     if (EnableLoopResched)
299       addPass(createHexagonLoopRescheduling());
300     // Split double registers.
301     if (!DisableHSDR)
302       addPass(createHexagonSplitDoubleRegs());
303     // Bit simplification.
304     if (EnableBitSimplify)
305       addPass(createHexagonBitSimplify());
306     addPass(createHexagonPeephole());
307     // Constant propagation.
308     if (!DisableHCP) {
309       addPass(createHexagonConstPropagationPass());
310       addPass(&UnreachableMachineBlockElimID);
311     }
312     if (EnableGenInsert)
313       addPass(createHexagonGenInsert());
314     if (EnableEarlyIf)
315       addPass(createHexagonEarlyIfConversion());
316   }
317 
318   return false;
319 }
320 
321 void HexagonPassConfig::addPreRegAlloc() {
322   if (getOptLevel() != CodeGenOpt::None) {
323     if (EnableExpandCondsets)
324       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
325     if (!DisableStoreWidening)
326       addPass(createHexagonStoreWidening());
327     if (!DisableHardwareLoops)
328       addPass(createHexagonHardwareLoops());
329   }
330   if (TM->getOptLevel() >= CodeGenOpt::Default)
331     addPass(&MachinePipelinerID);
332 }
333 
334 void HexagonPassConfig::addPostRegAlloc() {
335   if (getOptLevel() != CodeGenOpt::None) {
336     if (EnableRDFOpt)
337       addPass(createHexagonRDFOpt());
338     if (!DisableHexagonCFGOpt)
339       addPass(createHexagonCFGOptimizer());
340     if (!DisableAModeOpt)
341       addPass(createHexagonOptAddrMode());
342   }
343 }
344 
345 void HexagonPassConfig::addPreSched2() {
346   addPass(createHexagonCopyToCombine());
347   if (getOptLevel() != CodeGenOpt::None)
348     addPass(&IfConverterID);
349   addPass(createHexagonSplitConst32AndConst64());
350 }
351 
352 void HexagonPassConfig::addPreEmitPass() {
353   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
354 
355   if (!NoOpt)
356     addPass(createHexagonNewValueJump());
357 
358   addPass(createHexagonBranchRelaxation());
359 
360   // Create Packets.
361   if (!NoOpt) {
362     if (!DisableHardwareLoops)
363       addPass(createHexagonFixupHwLoops());
364     // Generate MUX from pairs of conditional transfers.
365     if (EnableGenMux)
366       addPass(createHexagonGenMux());
367 
368     addPass(createHexagonPacketizer(), false);
369   }
370   if (EnableVectorPrint)
371     addPass(createHexagonVectorPrint(), false);
372 
373   // Add CFI instructions if necessary.
374   addPass(createHexagonCallFrameInformation(), false);
375 }
376