1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 
34 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
35   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 
37 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38   cl::Hidden, cl::ZeroOrMore, cl::init(false),
39   cl::desc("Disable Hexagon Addressing Mode Optimization"));
40 
41 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42   cl::Hidden, cl::ZeroOrMore, cl::init(false),
43   cl::desc("Disable Hexagon CFG Optimization"));
44 
45 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
46   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
47 
48 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
49   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
50 
51 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
52   cl::init(true), cl::Hidden, cl::ZeroOrMore,
53   cl::desc("Early expansion of MUX"));
54 
55 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
56   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
57 
58 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
59   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
60 
61 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
62   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
63 
64 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
65   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
66 
67 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
68   cl::desc("Enable converting conditional transfers into MUX instructions"));
69 
70 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
71   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
72   "predicate instructions"));
73 
74 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
75   cl::init(false), cl::Hidden, cl::ZeroOrMore,
76   cl::desc("Enable loop data prefetch on Hexagon"));
77 
78 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
79   cl::desc("Disable splitting double registers"));
80 
81 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
82   cl::Hidden, cl::desc("Bit simplification"));
83 
84 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
85   cl::Hidden, cl::desc("Loop rescheduling"));
86 
87 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
88   cl::Hidden, cl::desc("Disable backend optimizations"));
89 
90 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
91   cl::Hidden, cl::ZeroOrMore, cl::init(false),
92   cl::desc("Enable Hexagon Vector print instr pass"));
93 
94 /// HexagonTargetMachineModule - Note that this is used on hosts that
95 /// cannot link in a library unless there are references into the
96 /// library.  In particular, it seems that it is not possible to get
97 /// things to work on Win32 without this.  Though it is unused, do not
98 /// remove it.
99 extern "C" int HexagonTargetMachineModule;
100 int HexagonTargetMachineModule = 0;
101 
102 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
103   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
104 }
105 
106 static MachineSchedRegistry
107 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
108                     createVLIWMachineSched);
109 
110 namespace llvm {
111   extern char &HexagonExpandCondsetsID;
112   void initializeHexagonExpandCondsetsPass(PassRegistry&);
113   void initializeHexagonGenMuxPass(PassRegistry&);
114   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
115   void initializeHexagonNewValueJumpPass(PassRegistry&);
116   void initializeHexagonOptAddrModePass(PassRegistry&);
117   void initializeHexagonPacketizerPass(PassRegistry&);
118   Pass *createHexagonLoopIdiomPass();
119 
120   FunctionPass *createHexagonBitSimplify();
121   FunctionPass *createHexagonBranchRelaxation();
122   FunctionPass *createHexagonCallFrameInformation();
123   FunctionPass *createHexagonCFGOptimizer();
124   FunctionPass *createHexagonCommonGEP();
125   FunctionPass *createHexagonConstPropagationPass();
126   FunctionPass *createHexagonCopyToCombine();
127   FunctionPass *createHexagonEarlyIfConversion();
128   FunctionPass *createHexagonFixupHwLoops();
129   FunctionPass *createHexagonGenExtract();
130   FunctionPass *createHexagonGenInsert();
131   FunctionPass *createHexagonGenMux();
132   FunctionPass *createHexagonGenPredicate();
133   FunctionPass *createHexagonHardwareLoops();
134   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
135                                      CodeGenOpt::Level OptLevel);
136   FunctionPass *createHexagonLoopRescheduling();
137   FunctionPass *createHexagonNewValueJump();
138   FunctionPass *createHexagonOptimizeSZextends();
139   FunctionPass *createHexagonOptAddrMode();
140   FunctionPass *createHexagonPacketizer();
141   FunctionPass *createHexagonPeephole();
142   FunctionPass *createHexagonRDFOpt();
143   FunctionPass *createHexagonSplitConst32AndConst64();
144   FunctionPass *createHexagonSplitDoubleRegs();
145   FunctionPass *createHexagonStoreWidening();
146   FunctionPass *createHexagonVectorPrint();
147 } // end namespace llvm;
148 
149 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
150   if (!RM.hasValue())
151     return Reloc::Static;
152   return *RM;
153 }
154 
155 extern "C" void LLVMInitializeHexagonTarget() {
156   // Register the target.
157   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
158 
159   PassRegistry &PR = *PassRegistry::getPassRegistry();
160   initializeHexagonGenMuxPass(PR);
161   initializeHexagonLoopIdiomRecognizePass(PR);
162   initializeHexagonNewValueJumpPass(PR);
163   initializeHexagonOptAddrModePass(PR);
164   initializeHexagonPacketizerPass(PR);
165 }
166 
167 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
168                                            StringRef CPU, StringRef FS,
169                                            const TargetOptions &Options,
170                                            Optional<Reloc::Model> RM,
171                                            CodeModel::Model CM,
172                                            CodeGenOpt::Level OL)
173     // Specify the vector alignment explicitly. For v512x1, the calculated
174     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
175     // the required minimum of 64 bytes.
176     : LLVMTargetMachine(
177           T, "e-m:e-p:32:32:32-a:0-n16:32-"
178              "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
179              "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
180           TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
181           (HexagonNoOpt ? CodeGenOpt::None : OL)),
182       TLOF(make_unique<HexagonTargetObjectFile>()) {
183   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
184   initAsmInfo();
185 }
186 
187 const HexagonSubtarget *
188 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
189   AttributeList FnAttrs = F.getAttributes();
190   Attribute CPUAttr =
191       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
192   Attribute FSAttr =
193       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
194 
195   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
196                         ? CPUAttr.getValueAsString().str()
197                         : TargetCPU;
198   std::string FS = !FSAttr.hasAttribute(Attribute::None)
199                        ? FSAttr.getValueAsString().str()
200                        : TargetFS;
201 
202   auto &I = SubtargetMap[CPU + FS];
203   if (!I) {
204     // This needs to be done before we create a new subtarget since any
205     // creation will depend on the TM and the code generation flags on the
206     // function that reside in TargetOptions.
207     resetTargetOptions(F);
208     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
209   }
210   return I.get();
211 }
212 
213 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
214   PMB.addExtension(
215     PassManagerBuilder::EP_LateLoopOptimizations,
216     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
217       PM.add(createHexagonLoopIdiomPass());
218     });
219 }
220 
221 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
222   return TargetIRAnalysis([this](const Function &F) {
223     return TargetTransformInfo(HexagonTTIImpl(this, F));
224   });
225 }
226 
227 
228 HexagonTargetMachine::~HexagonTargetMachine() {}
229 
230 namespace {
231 /// Hexagon Code Generator Pass Configuration Options.
232 class HexagonPassConfig : public TargetPassConfig {
233 public:
234   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
235     : TargetPassConfig(TM, PM) {}
236 
237   HexagonTargetMachine &getHexagonTargetMachine() const {
238     return getTM<HexagonTargetMachine>();
239   }
240 
241   ScheduleDAGInstrs *
242   createMachineScheduler(MachineSchedContext *C) const override {
243     return createVLIWMachineSched(C);
244   }
245 
246   void addIRPasses() override;
247   bool addInstSelector() override;
248   void addPreRegAlloc() override;
249   void addPostRegAlloc() override;
250   void addPreSched2() override;
251   void addPreEmitPass() override;
252 };
253 } // namespace
254 
255 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
256   return new HexagonPassConfig(*this, PM);
257 }
258 
259 void HexagonPassConfig::addIRPasses() {
260   TargetPassConfig::addIRPasses();
261   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
262 
263   addPass(createAtomicExpandPass());
264   if (!NoOpt) {
265     if (EnableLoopPrefetch)
266       addPass(createLoopDataPrefetchPass());
267     if (EnableCommGEP)
268       addPass(createHexagonCommonGEP());
269     // Replace certain combinations of shifts and ands with extracts.
270     if (EnableGenExtract)
271       addPass(createHexagonGenExtract());
272   }
273 }
274 
275 bool HexagonPassConfig::addInstSelector() {
276   HexagonTargetMachine &TM = getHexagonTargetMachine();
277   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
278 
279   if (!NoOpt)
280     addPass(createHexagonOptimizeSZextends());
281 
282   addPass(createHexagonISelDag(TM, getOptLevel()));
283 
284   if (!NoOpt) {
285     // Create logical operations on predicate registers.
286     if (EnableGenPred)
287       addPass(createHexagonGenPredicate());
288     // Rotate loops to expose bit-simplification opportunities.
289     if (EnableLoopResched)
290       addPass(createHexagonLoopRescheduling());
291     // Split double registers.
292     if (!DisableHSDR)
293       addPass(createHexagonSplitDoubleRegs());
294     // Bit simplification.
295     if (EnableBitSimplify)
296       addPass(createHexagonBitSimplify());
297     addPass(createHexagonPeephole());
298     // Constant propagation.
299     if (!DisableHCP) {
300       addPass(createHexagonConstPropagationPass());
301       addPass(&UnreachableMachineBlockElimID);
302     }
303     if (EnableGenInsert)
304       addPass(createHexagonGenInsert());
305     if (EnableEarlyIf)
306       addPass(createHexagonEarlyIfConversion());
307   }
308 
309   return false;
310 }
311 
312 void HexagonPassConfig::addPreRegAlloc() {
313   if (getOptLevel() != CodeGenOpt::None) {
314     if (EnableExpandCondsets)
315       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
316     if (!DisableStoreWidening)
317       addPass(createHexagonStoreWidening());
318     if (!DisableHardwareLoops)
319       addPass(createHexagonHardwareLoops());
320   }
321   if (TM->getOptLevel() >= CodeGenOpt::Default)
322     addPass(&MachinePipelinerID);
323 }
324 
325 void HexagonPassConfig::addPostRegAlloc() {
326   if (getOptLevel() != CodeGenOpt::None) {
327     if (EnableRDFOpt)
328       addPass(createHexagonRDFOpt());
329     if (!DisableHexagonCFGOpt)
330       addPass(createHexagonCFGOptimizer());
331     if (!DisableAModeOpt)
332       addPass(createHexagonOptAddrMode());
333   }
334 }
335 
336 void HexagonPassConfig::addPreSched2() {
337   addPass(createHexagonCopyToCombine());
338   if (getOptLevel() != CodeGenOpt::None)
339     addPass(&IfConverterID);
340   addPass(createHexagonSplitConst32AndConst64());
341 }
342 
343 void HexagonPassConfig::addPreEmitPass() {
344   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
345 
346   if (!NoOpt)
347     addPass(createHexagonNewValueJump());
348 
349   addPass(createHexagonBranchRelaxation());
350 
351   // Create Packets.
352   if (!NoOpt) {
353     if (!DisableHardwareLoops)
354       addPass(createHexagonFixupHwLoops());
355     // Generate MUX from pairs of conditional transfers.
356     if (EnableGenMux)
357       addPass(createHexagonGenMux());
358 
359     addPass(createHexagonPacketizer(), false);
360   }
361   if (EnableVectorPrint)
362     addPass(createHexagonVectorPrint(), false);
363 
364   // Add CFI instructions if necessary.
365   addPass(createHexagonCallFrameInformation(), false);
366 }
367