1 //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // When the compiler is invoked with no small data, for instance, with the -G0
11 // command line option, then all CONST32_* opcodes should be broken down into
12 // appropriate LO and HI instructions. This splitting is done by this pass.
13 // The only reason this is not done in the DAG lowering itself is that there
14 // is no simple way of getting the register allocator to allot the same hard
15 // register to the result of LO and HI instructions. This pass is always
16 // scheduled after register allocation.
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #include "HexagonMachineFunctionInfo.h"
21 #include "HexagonSubtarget.h"
22 #include "HexagonTargetMachine.h"
23 #include "HexagonTargetObjectFile.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/CodeGen/LatencyPriorityQueue.h"
26 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLoopInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include <map>
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "xfer"
47 
48 namespace {
49 
50 class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
51   const HexagonTargetMachine &QTM;
52 
53  public:
54     static char ID;
55     HexagonSplitConst32AndConst64(const HexagonTargetMachine &TM)
56         : MachineFunctionPass(ID), QTM(TM) {}
57 
58     const char *getPassName() const override {
59       return "Hexagon Split Const32s and Const64s";
60     }
61     bool runOnMachineFunction(MachineFunction &Fn) override;
62 };
63 
64 
65 char HexagonSplitConst32AndConst64::ID = 0;
66 
67 
68 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
69 
70   const HexagonTargetObjectFile &TLOF =
71       (const HexagonTargetObjectFile &)QTM.getSubtargetImpl()
72           ->getTargetLowering()
73           ->getObjFileLowering();
74   if (TLOF.IsSmallDataEnabled())
75     return true;
76 
77   const TargetInstrInfo *TII = QTM.getSubtargetImpl()->getInstrInfo();
78 
79   // Loop over all of the basic blocks
80   for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
81        MBBb != MBBe; ++MBBb) {
82     MachineBasicBlock* MBB = MBBb;
83     // Traverse the basic block
84     MachineBasicBlock::iterator MII = MBB->begin();
85     MachineBasicBlock::iterator MIE = MBB->end ();
86     while (MII != MIE) {
87       MachineInstr *MI = MII;
88       int Opc = MI->getOpcode();
89       if (Opc == Hexagon::CONST32_set) {
90         int DestReg = MI->getOperand(0).getReg();
91         MachineOperand &Symbol = MI->getOperand (1);
92 
93         BuildMI (*MBB, MII, MI->getDebugLoc(),
94                  TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
95         BuildMI (*MBB, MII, MI->getDebugLoc(),
96                  TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
97         // MBB->erase returns the iterator to the next instruction, which is the
98         // one we want to process next
99         MII = MBB->erase (MI);
100         continue;
101       }
102       else if (Opc == Hexagon::CONST32_set_jt) {
103         int DestReg = MI->getOperand(0).getReg();
104         MachineOperand &Symbol = MI->getOperand (1);
105 
106         BuildMI (*MBB, MII, MI->getDebugLoc(),
107                  TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
108         BuildMI (*MBB, MII, MI->getDebugLoc(),
109                  TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
110         // MBB->erase returns the iterator to the next instruction, which is the
111         // one we want to process next
112         MII = MBB->erase (MI);
113         continue;
114       }
115       else if (Opc == Hexagon::CONST32_Label) {
116         int DestReg = MI->getOperand(0).getReg();
117         MachineOperand &Symbol = MI->getOperand (1);
118 
119         BuildMI (*MBB, MII, MI->getDebugLoc(),
120                  TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
121         BuildMI (*MBB, MII, MI->getDebugLoc(),
122                  TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
123         // MBB->erase returns the iterator to the next instruction, which is the
124         // one we want to process next
125         MII = MBB->erase (MI);
126         continue;
127       }
128       else if (Opc == Hexagon::CONST32_Int_Real) {
129         int DestReg = MI->getOperand(0).getReg();
130         int64_t ImmValue = MI->getOperand(1).getImm ();
131 
132         BuildMI (*MBB, MII, MI->getDebugLoc(),
133                  TII->get(Hexagon::LOi), DestReg).addImm(ImmValue);
134         BuildMI (*MBB, MII, MI->getDebugLoc(),
135                  TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
136         MII = MBB->erase (MI);
137         continue;
138       }
139       else if (Opc == Hexagon::CONST64_Int_Real) {
140         int DestReg = MI->getOperand(0).getReg();
141         int64_t ImmValue = MI->getOperand(1).getImm ();
142         unsigned DestLo = QTM.getSubtargetImpl()->getRegisterInfo()->getSubReg(
143             DestReg, Hexagon::subreg_loreg);
144         unsigned DestHi = QTM.getSubtargetImpl()->getRegisterInfo()->getSubReg(
145             DestReg, Hexagon::subreg_hireg);
146 
147         int32_t LowWord = (ImmValue & 0xFFFFFFFF);
148         int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
149 
150         // Lower Registers Lower Half
151         BuildMI (*MBB, MII, MI->getDebugLoc(),
152                  TII->get(Hexagon::LOi), DestLo).addImm(LowWord);
153         // Lower Registers Higher Half
154         BuildMI (*MBB, MII, MI->getDebugLoc(),
155                  TII->get(Hexagon::HIi), DestLo).addImm(LowWord);
156         // Higher Registers Lower Half
157         BuildMI (*MBB, MII, MI->getDebugLoc(),
158                  TII->get(Hexagon::LOi), DestHi).addImm(HighWord);
159         // Higher Registers Higher Half.
160         BuildMI (*MBB, MII, MI->getDebugLoc(),
161                  TII->get(Hexagon::HIi), DestHi).addImm(HighWord);
162         MII = MBB->erase (MI);
163         continue;
164        }
165       ++MII;
166     }
167   }
168 
169   return true;
170 }
171 
172 }
173 
174 //===----------------------------------------------------------------------===//
175 //                         Public Constructor Functions
176 //===----------------------------------------------------------------------===//
177 
178 FunctionPass *
179 llvm::createHexagonSplitConst32AndConst64(const HexagonTargetMachine &TM) {
180   return new HexagonSplitConst32AndConst64(TM);
181 }
182