1 //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // When the compiler is invoked with no small data, for instance, with the -G0
11 // command line option, then all CONST32_* opcodes should be broken down into
12 // appropriate LO and HI instructions. This splitting is done by this pass.
13 // The only reason this is not done in the DAG lowering itself is that there
14 // is no simple way of getting the register allocator to allot the same hard
15 // register to the result of LO and HI instructions. This pass is always
16 // scheduled after register allocation.
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #define DEBUG_TYPE "xfer"
21 
22 #include "HexagonTargetMachine.h"
23 #include "HexagonMachineFunctionInfo.h"
24 #include "HexagonSubtarget.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/CodeGen/LatencyPriorityQueue.h"
27 #include "llvm/CodeGen/MachineDominators.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLoopInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
34 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
35 #include "llvm/CodeGen/SchedulerRegistry.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include <map>
44 
45 using namespace llvm;
46 
47 namespace {
48 
49 class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
50     const HexagonTargetMachine& QTM;
51     const HexagonSubtarget &QST;
52 
53  public:
54     static char ID;
55     HexagonSplitConst32AndConst64(const HexagonTargetMachine& TM)
56       : MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
57 
58     const char *getPassName() const {
59       return "Hexagon Split Const32s and Const64s";
60     }
61     bool runOnMachineFunction(MachineFunction &Fn);
62 };
63 
64 
65 char HexagonSplitConst32AndConst64::ID = 0;
66 
67 
68 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
69 
70   const TargetInstrInfo *TII = QTM.getInstrInfo();
71 
72   // Loop over all of the basic blocks
73   for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
74        MBBb != MBBe; ++MBBb) {
75     MachineBasicBlock* MBB = MBBb;
76     // Traverse the basic block
77     MachineBasicBlock::iterator MII = MBB->begin();
78     MachineBasicBlock::iterator MIE = MBB->end ();
79     while (MII != MIE) {
80       MachineInstr *MI = MII;
81       int Opc = MI->getOpcode();
82       if (Opc == Hexagon::CONST32_set) {
83         int DestReg = MI->getOperand(0).getReg();
84         MachineOperand &Symbol = MI->getOperand (1);
85 
86         BuildMI (*MBB, MII, MI->getDebugLoc(),
87                  TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
88         BuildMI (*MBB, MII, MI->getDebugLoc(),
89                  TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
90         // MBB->erase returns the iterator to the next instruction, which is the
91         // one we want to process next
92         MII = MBB->erase (MI);
93         continue;
94       }
95       else if (Opc == Hexagon::CONST32_set_jt) {
96         int DestReg = MI->getOperand(0).getReg();
97         MachineOperand &Symbol = MI->getOperand (1);
98 
99         BuildMI (*MBB, MII, MI->getDebugLoc(),
100                  TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
101         BuildMI (*MBB, MII, MI->getDebugLoc(),
102                  TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
103         // MBB->erase returns the iterator to the next instruction, which is the
104         // one we want to process next
105         MII = MBB->erase (MI);
106         continue;
107       }
108       else if (Opc == Hexagon::CONST32_Label) {
109         int DestReg = MI->getOperand(0).getReg();
110         MachineOperand &Symbol = MI->getOperand (1);
111 
112         BuildMI (*MBB, MII, MI->getDebugLoc(),
113                  TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
114         BuildMI (*MBB, MII, MI->getDebugLoc(),
115                  TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
116         // MBB->erase returns the iterator to the next instruction, which is the
117         // one we want to process next
118         MII = MBB->erase (MI);
119         continue;
120       }
121       else if (Opc == Hexagon::CONST32_Int_Real) {
122         int DestReg = MI->getOperand(0).getReg();
123         int64_t ImmValue = MI->getOperand(1).getImm ();
124 
125         BuildMI (*MBB, MII, MI->getDebugLoc(),
126                  TII->get(Hexagon::LOi), DestReg).addImm(ImmValue);
127         BuildMI (*MBB, MII, MI->getDebugLoc(),
128                  TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
129         MII = MBB->erase (MI);
130         continue;
131       }
132       else if (Opc == Hexagon::CONST64_Int_Real) {
133         int DestReg = MI->getOperand(0).getReg();
134         int64_t ImmValue = MI->getOperand(1).getImm ();
135         unsigned DestLo =
136           QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_loreg);
137         unsigned DestHi =
138           QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_hireg);
139 
140         int32_t LowWord = (ImmValue & 0xFFFFFFFF);
141         int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
142 
143         // Lower Registers Lower Half
144         BuildMI (*MBB, MII, MI->getDebugLoc(),
145                  TII->get(Hexagon::LOi), DestLo).addImm(LowWord);
146         // Lower Registers Higher Half
147         BuildMI (*MBB, MII, MI->getDebugLoc(),
148                  TII->get(Hexagon::HIi), DestLo).addImm(LowWord);
149         // Higher Registers Lower Half
150         BuildMI (*MBB, MII, MI->getDebugLoc(),
151                  TII->get(Hexagon::LOi), DestHi).addImm(HighWord);
152         // Higher Registers Higher Half.
153         BuildMI (*MBB, MII, MI->getDebugLoc(),
154                  TII->get(Hexagon::HIi), DestHi).addImm(HighWord);
155         MII = MBB->erase (MI);
156         continue;
157        }
158       ++MII;
159     }
160   }
161 
162   return true;
163 }
164 
165 }
166 
167 //===----------------------------------------------------------------------===//
168 //                         Public Constructor Functions
169 //===----------------------------------------------------------------------===//
170 
171 FunctionPass *
172 llvm::createHexagonSplitConst32AndConst64(const HexagonTargetMachine &TM) {
173   return new HexagonSplitConst32AndConst64(TM);
174 }
175