1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonRegisterInfo.h"
16 #include "Hexagon.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/MC/MachineLocation.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 
39 #define GET_REGINFO_TARGET_DESC
40 #include "HexagonGenRegisterInfo.inc"
41 
42 using namespace llvm;
43 
44 HexagonRegisterInfo::HexagonRegisterInfo()
45     : HexagonGenRegisterInfo(Hexagon::R31) {}
46 
47 
48 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const {
49   return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
50          R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
51 }
52 
53 bool HexagonRegisterInfo::isCalleeSaveReg(unsigned Reg) const {
54   return Hexagon::R16 <= Reg && Reg <= Hexagon::R27;
55 }
56 
57 
58 const MCPhysReg *
59 HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF,
60       const TargetRegisterClass *RC) const {
61   using namespace Hexagon;
62 
63   static const MCPhysReg Int32[] = {
64     R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
65   };
66   static const MCPhysReg Int64[] = {
67     D0, D1, D2, D3, D4, D5, D6, D7, 0
68   };
69   static const MCPhysReg Pred[] = {
70     P0, P1, P2, P3, 0
71   };
72   static const MCPhysReg VecSgl[] = {
73      V0,  V1,  V2,  V3,  V4,  V5,  V6,  V7,  V8,  V9, V10, V11, V12, V13,
74     V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
75     V28, V29, V30, V31,   0
76   };
77   static const MCPhysReg VecDbl[] = {
78     W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
79   };
80 
81   switch (RC->getID()) {
82     case IntRegsRegClassID:
83       return Int32;
84     case DoubleRegsRegClassID:
85       return Int64;
86     case PredRegsRegClassID:
87       return Pred;
88     case VectorRegsRegClassID:
89     case VectorRegs128BRegClassID:
90       return VecSgl;
91     case VecDblRegsRegClassID:
92     case VecDblRegs128BRegClassID:
93       return VecDbl;
94     default:
95       break;
96   }
97 
98   static const MCPhysReg Empty[] = { 0 };
99 #ifndef NDEBUG
100   dbgs() << "Register class: " << getRegClassName(RC) << "\n";
101 #endif
102   llvm_unreachable("Unexpected register class");
103   return Empty;
104 }
105 
106 
107 const MCPhysReg *
108 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
109   static const MCPhysReg CalleeSavedRegsV3[] = {
110     Hexagon::R16,   Hexagon::R17,   Hexagon::R18,   Hexagon::R19,
111     Hexagon::R20,   Hexagon::R21,   Hexagon::R22,   Hexagon::R23,
112     Hexagon::R24,   Hexagon::R25,   Hexagon::R26,   Hexagon::R27, 0
113   };
114 
115   // Functions that contain a call to __builtin_eh_return also save the first 4
116   // parameter registers.
117   static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
118     Hexagon::R0,    Hexagon::R1,    Hexagon::R2,    Hexagon::R3,
119     Hexagon::R16,   Hexagon::R17,   Hexagon::R18,   Hexagon::R19,
120     Hexagon::R20,   Hexagon::R21,   Hexagon::R22,   Hexagon::R23,
121     Hexagon::R24,   Hexagon::R25,   Hexagon::R26,   Hexagon::R27, 0
122   };
123 
124   bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
125 
126   switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
127   case HexagonSubtarget::V4:
128   case HexagonSubtarget::V5:
129   case HexagonSubtarget::V55:
130   case HexagonSubtarget::V60:
131   case HexagonSubtarget::V62:
132     return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
133   }
134 
135   llvm_unreachable("Callee saved registers requested for unknown architecture "
136                    "version");
137 }
138 
139 
140 const uint32_t *HexagonRegisterInfo::getCallPreservedMask(
141       const MachineFunction &MF, CallingConv::ID) const {
142   return HexagonCSR_RegMask;
143 }
144 
145 
146 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
147   const {
148   BitVector Reserved(getNumRegs());
149   Reserved.set(Hexagon::R29);
150   Reserved.set(Hexagon::R30);
151   Reserved.set(Hexagon::R31);
152   // Control registers.
153   Reserved.set(Hexagon::SA0);         // C0
154   Reserved.set(Hexagon::LC0);         // C1
155   Reserved.set(Hexagon::SA1);         // C2
156   Reserved.set(Hexagon::LC1);         // C3
157   Reserved.set(Hexagon::P3_0);        // C4
158   Reserved.set(Hexagon::USR);         // C8
159   Reserved.set(Hexagon::PC);          // C9
160   Reserved.set(Hexagon::UGP);         // C10
161   Reserved.set(Hexagon::GP);          // C11
162   Reserved.set(Hexagon::CS0);         // C12
163   Reserved.set(Hexagon::CS1);         // C13
164   Reserved.set(Hexagon::UPCYCLELO);   // C14
165   Reserved.set(Hexagon::UPCYCLEHI);   // C15
166   Reserved.set(Hexagon::FRAMELIMIT);  // C16
167   Reserved.set(Hexagon::FRAMEKEY);    // C17
168   Reserved.set(Hexagon::PKTCOUNTLO);  // C18
169   Reserved.set(Hexagon::PKTCOUNTHI);  // C19
170   Reserved.set(Hexagon::UTIMERLO);    // C30
171   Reserved.set(Hexagon::UTIMERHI);    // C31
172   // Out of the control registers, only C8 is explicitly defined in
173   // HexagonRegisterInfo.td. If others are defined, make sure to add
174   // them here as well.
175   Reserved.set(Hexagon::C8);
176   Reserved.set(Hexagon::USR_OVF);
177 
178   for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x))
179     markSuperRegs(Reserved, x);
180 
181   return Reserved;
182 }
183 
184 
185 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
186                                               int SPAdj, unsigned FIOp,
187                                               RegScavenger *RS) const {
188   //
189   // Hexagon_TODO: Do we need to enforce this for Hexagon?
190   assert(SPAdj == 0 && "Unexpected");
191 
192   MachineInstr &MI = *II;
193   MachineBasicBlock &MB = *MI.getParent();
194   MachineFunction &MF = *MB.getParent();
195   auto &HST = MF.getSubtarget<HexagonSubtarget>();
196   auto &HII = *HST.getInstrInfo();
197   auto &HFI = *HST.getFrameLowering();
198 
199   unsigned BP = 0;
200   int FI = MI.getOperand(FIOp).getIndex();
201   // Select the base pointer (BP) and calculate the actual offset from BP
202   // to the beginning of the object at index FI.
203   int Offset = HFI.getFrameIndexReference(MF, FI, BP);
204   // Add the offset from the instruction.
205   int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
206   bool IsKill = false;
207 
208   unsigned Opc = MI.getOpcode();
209   switch (Opc) {
210     case Hexagon::PS_fia:
211       MI.setDesc(HII.get(Hexagon::A2_addi));
212       MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
213       MI.RemoveOperand(FIOp+1);
214       return;
215     case Hexagon::PS_fi:
216       // Set up the instruction for updating below.
217       MI.setDesc(HII.get(Hexagon::A2_addi));
218       break;
219   }
220 
221   if (!HII.isValidOffset(Opc, RealOffset)) {
222     // If the offset is not valid, calculate the address in a temporary
223     // register and use it with offset 0.
224     auto &MRI = MF.getRegInfo();
225     unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
226     const DebugLoc &DL = MI.getDebugLoc();
227     BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
228       .addReg(BP)
229       .addImm(RealOffset);
230     BP = TmpR;
231     RealOffset = 0;
232     IsKill = true;
233   }
234 
235   MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
236   MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
237 }
238 
239 
240 unsigned HexagonRegisterInfo::getRARegister() const {
241   return Hexagon::R31;
242 }
243 
244 
245 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
246                                                &MF) const {
247   const HexagonFrameLowering *TFI = getFrameLowering(MF);
248   if (TFI->hasFP(MF))
249     return getFrameRegister();
250   return getStackRegister();
251 }
252 
253 
254 unsigned HexagonRegisterInfo::getFrameRegister() const {
255   return Hexagon::R30;
256 }
257 
258 
259 unsigned HexagonRegisterInfo::getStackRegister() const {
260   return Hexagon::R29;
261 }
262 
263 
264 unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
265       const TargetRegisterClass *RC, unsigned GenIdx) const {
266   assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
267 
268   static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
269   static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
270 
271   switch (RC->getID()) {
272     case Hexagon::CtrRegs64RegClassID:
273     case Hexagon::DoubleRegsRegClassID:
274       return ISub[GenIdx];
275     case Hexagon::VecDblRegsRegClassID:
276     case Hexagon::VecDblRegs128BRegClassID:
277       return VSub[GenIdx];
278   }
279 
280   if (const TargetRegisterClass *SuperRC = *RC->getSuperClasses())
281     return getHexagonSubRegIndex(SuperRC, GenIdx);
282 
283   llvm_unreachable("Invalid register class");
284 }
285 
286 bool HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF)
287       const {
288   return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
289 }
290 
291 
292 unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const {
293   return Hexagon::R6;
294 }
295 
296