1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonRegisterInfo.h"
16 #include "Hexagon.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/MC/MachineLocation.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 
40 using namespace llvm;
41 
42 HexagonRegisterInfo::HexagonRegisterInfo()
43     : HexagonGenRegisterInfo(Hexagon::R31) {}
44 
45 
46 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const {
47   return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
48          R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
49 }
50 
51 bool HexagonRegisterInfo::isCalleeSaveReg(unsigned Reg) const {
52   return Hexagon::R16 <= Reg && Reg <= Hexagon::R27;
53 }
54 
55 
56 const MCPhysReg *
57 HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF) const {
58   static const MCPhysReg CallerSavedRegsV4[] = {
59     Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
60     Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
61     Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
62     Hexagon::R15, 0
63   };
64 
65   switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
66   case HexagonSubtarget::V4:
67   case HexagonSubtarget::V5:
68   case HexagonSubtarget::V55:
69   case HexagonSubtarget::V60:
70     return CallerSavedRegsV4;
71   }
72   llvm_unreachable(
73     "Callee saved registers requested for unknown archtecture version");
74 }
75 
76 
77 const MCPhysReg *
78 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
79   static const MCPhysReg CalleeSavedRegsV3[] = {
80     Hexagon::R16,   Hexagon::R17,   Hexagon::R18,   Hexagon::R19,
81     Hexagon::R20,   Hexagon::R21,   Hexagon::R22,   Hexagon::R23,
82     Hexagon::R24,   Hexagon::R25,   Hexagon::R26,   Hexagon::R27, 0
83   };
84 
85   // Functions that contain a call to __builtin_eh_return also save the first 4
86   // parameter registers.
87   static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
88     Hexagon::R0,    Hexagon::R1,    Hexagon::R2,    Hexagon::R3,
89     Hexagon::R16,   Hexagon::R17,   Hexagon::R18,   Hexagon::R19,
90     Hexagon::R20,   Hexagon::R21,   Hexagon::R22,   Hexagon::R23,
91     Hexagon::R24,   Hexagon::R25,   Hexagon::R26,   Hexagon::R27, 0
92   };
93 
94   bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
95 
96   switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
97   case HexagonSubtarget::V4:
98   case HexagonSubtarget::V5:
99   case HexagonSubtarget::V55:
100   case HexagonSubtarget::V60:
101     return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
102   }
103 
104   llvm_unreachable("Callee saved registers requested for unknown architecture "
105                    "version");
106 }
107 
108 
109 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
110   const {
111   BitVector Reserved(getNumRegs());
112   Reserved.set(HEXAGON_RESERVED_REG_1);
113   Reserved.set(HEXAGON_RESERVED_REG_2);
114   Reserved.set(Hexagon::R29);
115   Reserved.set(Hexagon::R30);
116   Reserved.set(Hexagon::R31);
117   Reserved.set(Hexagon::PC);
118   Reserved.set(Hexagon::D14);
119   Reserved.set(Hexagon::D15);
120   Reserved.set(Hexagon::LC0);
121   Reserved.set(Hexagon::LC1);
122   Reserved.set(Hexagon::SA0);
123   Reserved.set(Hexagon::SA1);
124   Reserved.set(Hexagon::UGP);
125   Reserved.set(Hexagon::GP);
126   Reserved.set(Hexagon::CS0);
127   Reserved.set(Hexagon::CS1);
128   Reserved.set(Hexagon::CS);
129   return Reserved;
130 }
131 
132 
133 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
134                                               int SPAdj, unsigned FIOp,
135                                               RegScavenger *RS) const {
136   //
137   // Hexagon_TODO: Do we need to enforce this for Hexagon?
138   assert(SPAdj == 0 && "Unexpected");
139 
140   MachineInstr &MI = *II;
141   MachineBasicBlock &MB = *MI.getParent();
142   MachineFunction &MF = *MB.getParent();
143   auto &HST = MF.getSubtarget<HexagonSubtarget>();
144   auto &HII = *HST.getInstrInfo();
145   auto &HFI = *HST.getFrameLowering();
146 
147   unsigned BP = 0;
148   int FI = MI.getOperand(FIOp).getIndex();
149   // Select the base pointer (BP) and calculate the actual offset from BP
150   // to the beginning of the object at index FI.
151   int Offset = HFI.getFrameIndexReference(MF, FI, BP);
152   // Add the offset from the instruction.
153   int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
154   bool IsKill = false;
155 
156   unsigned Opc = MI.getOpcode();
157   switch (Opc) {
158     case Hexagon::TFR_FIA:
159       MI.setDesc(HII.get(Hexagon::A2_addi));
160       MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
161       MI.RemoveOperand(FIOp+1);
162       return;
163     case Hexagon::TFR_FI:
164       // Set up the instruction for updating below.
165       MI.setDesc(HII.get(Hexagon::A2_addi));
166       break;
167   }
168 
169   if (!HII.isValidOffset(Opc, RealOffset)) {
170     // If the offset is not valid, calculate the address in a temporary
171     // register and use it with offset 0.
172     auto &MRI = MF.getRegInfo();
173     unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
174     DebugLoc DL = MI.getDebugLoc();
175     BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
176       .addReg(BP)
177       .addImm(RealOffset);
178     BP = TmpR;
179     RealOffset = 0;
180     IsKill = true;
181   }
182 
183   MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
184   MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
185 }
186 
187 
188 unsigned HexagonRegisterInfo::getRARegister() const {
189   return Hexagon::R31;
190 }
191 
192 
193 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
194                                                &MF) const {
195   const HexagonFrameLowering *TFI = getFrameLowering(MF);
196   if (TFI->hasFP(MF))
197     return getFrameRegister();
198   return getStackRegister();
199 }
200 
201 
202 unsigned HexagonRegisterInfo::getFrameRegister() const {
203   return Hexagon::R30;
204 }
205 
206 
207 unsigned HexagonRegisterInfo::getStackRegister() const {
208   return Hexagon::R29;
209 }
210 
211 
212 bool HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF)
213       const {
214   return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
215 }
216 
217 
218 unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const {
219   return Hexagon::R6;
220 }
221 
222 
223 #define GET_REGINFO_TARGET_DESC
224 #include "HexagonGenRegisterInfo.inc"
225