1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements NewValueJump pass in Hexagon. 11 // Ideally, we should merge this as a Peephole pass prior to register 12 // allocation, but because we have a spill in between the feeder and new value 13 // jump instructions, we are forced to write after register allocation. 14 // Having said that, we should re-attempt to pull this earlier at some point 15 // in future. 16 17 // The basic approach looks for sequence of predicated jump, compare instruciton 18 // that genereates the predicate and, the feeder to the predicate. Once it finds 19 // all, it collapses compare and jump instruction into a new valu jump 20 // intstructions. 21 // 22 // 23 //===----------------------------------------------------------------------===// 24 #include "Hexagon.h" 25 #include "HexagonInstrInfo.h" 26 #include "HexagonMachineFunctionInfo.h" 27 #include "HexagonRegisterInfo.h" 28 #include "HexagonSubtarget.h" 29 #include "HexagonTargetMachine.h" 30 #include "llvm/ADT/Statistic.h" 31 #include "llvm/CodeGen/LiveVariables.h" 32 #include "llvm/CodeGen/MachineFunctionPass.h" 33 #include "llvm/CodeGen/MachineInstrBuilder.h" 34 #include "llvm/CodeGen/MachineRegisterInfo.h" 35 #include "llvm/CodeGen/Passes.h" 36 #include "llvm/CodeGen/ScheduleDAGInstrs.h" 37 #include "llvm/PassSupport.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/raw_ostream.h" 41 #include "llvm/Target/TargetInstrInfo.h" 42 #include "llvm/Target/TargetMachine.h" 43 #include "llvm/Target/TargetRegisterInfo.h" 44 using namespace llvm; 45 46 #define DEBUG_TYPE "hexagon-nvj" 47 48 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created"); 49 50 static cl::opt<int> 51 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc( 52 "Maximum number of predicated jumps to be converted to New Value Jump")); 53 54 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden, 55 cl::ZeroOrMore, cl::init(false), 56 cl::desc("Disable New Value Jumps")); 57 58 namespace llvm { 59 FunctionPass *createHexagonNewValueJump(); 60 void initializeHexagonNewValueJumpPass(PassRegistry&); 61 } 62 63 64 namespace { 65 struct HexagonNewValueJump : public MachineFunctionPass { 66 const HexagonInstrInfo *QII; 67 const HexagonRegisterInfo *QRI; 68 69 public: 70 static char ID; 71 72 HexagonNewValueJump() : MachineFunctionPass(ID) { 73 initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry()); 74 } 75 76 void getAnalysisUsage(AnalysisUsage &AU) const override { 77 AU.addRequired<MachineBranchProbabilityInfo>(); 78 MachineFunctionPass::getAnalysisUsage(AU); 79 } 80 81 StringRef getPassName() const override { return "Hexagon NewValueJump"; } 82 83 bool runOnMachineFunction(MachineFunction &Fn) override; 84 MachineFunctionProperties getRequiredProperties() const override { 85 return MachineFunctionProperties().set( 86 MachineFunctionProperties::Property::NoVRegs); 87 } 88 89 private: 90 /// \brief A handle to the branch probability pass. 91 const MachineBranchProbabilityInfo *MBPI; 92 93 bool isNewValueJumpCandidate(const MachineInstr &MI) const; 94 }; 95 96 } // end of anonymous namespace 97 98 char HexagonNewValueJump::ID = 0; 99 100 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", 101 "Hexagon NewValueJump", false, false) 102 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) 103 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj", 104 "Hexagon NewValueJump", false, false) 105 106 107 // We have identified this II could be feeder to NVJ, 108 // verify that it can be. 109 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, 110 const TargetRegisterInfo *TRI, 111 MachineBasicBlock::iterator II, 112 MachineBasicBlock::iterator end, 113 MachineBasicBlock::iterator skip, 114 MachineFunction &MF) { 115 116 // Predicated instruction can not be feeder to NVJ. 117 if (QII->isPredicated(*II)) 118 return false; 119 120 // Bail out if feederReg is a paired register (double regs in 121 // our case). One would think that we can check to see if a given 122 // register cmpReg1 or cmpReg2 is a sub register of feederReg 123 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic 124 // before the callsite of this function 125 // But we can not as it comes in the following fashion. 126 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> 127 // %R0<def> = KILL %R0, %D0<imp-use,kill> 128 // %P0<def> = CMPEQri %R0<kill>, 0 129 // Hence, we need to check if it's a KILL instruction. 130 if (II->getOpcode() == TargetOpcode::KILL) 131 return false; 132 133 if (II->isImplicitDef()) 134 return false; 135 136 // Make sure there there is no 'def' or 'use' of any of the uses of 137 // feeder insn between it's definition, this MI and jump, jmpInst 138 // skipping compare, cmpInst. 139 // Here's the example. 140 // r21=memub(r22+r24<<#0) 141 // p0 = cmp.eq(r21, #0) 142 // r4=memub(r3+r21<<#0) 143 // if (p0.new) jump:t .LBB29_45 144 // Without this check, it will be converted into 145 // r4=memub(r3+r21<<#0) 146 // r21=memub(r22+r24<<#0) 147 // p0 = cmp.eq(r21, #0) 148 // if (p0.new) jump:t .LBB29_45 149 // and result WAR hazards if converted to New Value Jump. 150 151 for (unsigned i = 0; i < II->getNumOperands(); ++i) { 152 if (II->getOperand(i).isReg() && 153 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { 154 MachineBasicBlock::iterator localII = II; 155 ++localII; 156 unsigned Reg = II->getOperand(i).getReg(); 157 for (MachineBasicBlock::iterator localBegin = localII; 158 localBegin != end; ++localBegin) { 159 if (localBegin == skip ) continue; 160 // Check for Subregisters too. 161 if (localBegin->modifiesRegister(Reg, TRI) || 162 localBegin->readsRegister(Reg, TRI)) 163 return false; 164 } 165 } 166 } 167 return true; 168 } 169 170 // These are the common checks that need to performed 171 // to determine if 172 // 1. compare instruction can be moved before jump. 173 // 2. feeder to the compare instruction can be moved before jump. 174 static bool commonChecksToProhibitNewValueJump(bool afterRA, 175 MachineBasicBlock::iterator MII) { 176 177 // If store in path, bail out. 178 if (MII->getDesc().mayStore()) 179 return false; 180 181 // if call in path, bail out. 182 if (MII->isCall()) 183 return false; 184 185 // if NVJ is running prior to RA, do the following checks. 186 if (!afterRA) { 187 // The following Target Opcode instructions are spurious 188 // to new value jump. If they are in the path, bail out. 189 // KILL sets kill flag on the opcode. It also sets up a 190 // single register, out of pair. 191 // %D0<def> = S2_lsr_r_p %D0<kill>, %R2<kill> 192 // %R0<def> = KILL %R0, %D0<imp-use,kill> 193 // %P0<def> = C2_cmpeqi %R0<kill>, 0 194 // PHI can be anything after RA. 195 // COPY can remateriaze things in between feeder, compare and nvj. 196 if (MII->getOpcode() == TargetOpcode::KILL || 197 MII->getOpcode() == TargetOpcode::PHI || 198 MII->getOpcode() == TargetOpcode::COPY) 199 return false; 200 201 // The following pseudo Hexagon instructions sets "use" and "def" 202 // of registers by individual passes in the backend. At this time, 203 // we don't know the scope of usage and definitions of these 204 // instructions. 205 if (MII->getOpcode() == Hexagon::LDriw_pred || 206 MII->getOpcode() == Hexagon::STriw_pred) 207 return false; 208 } 209 210 return true; 211 } 212 213 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, 214 const TargetRegisterInfo *TRI, 215 MachineBasicBlock::iterator II, 216 unsigned pReg, 217 bool secondReg, 218 bool optLocation, 219 MachineBasicBlock::iterator end, 220 MachineFunction &MF) { 221 222 MachineInstr &MI = *II; 223 224 // If the second operand of the compare is an imm, make sure it's in the 225 // range specified by the arch. 226 if (!secondReg) { 227 int64_t v = MI.getOperand(2).getImm(); 228 bool Valid = false; 229 230 switch (MI.getOpcode()) { 231 case Hexagon::C2_cmpeqi: 232 case Hexagon::C2_cmpgti: 233 Valid = (isUInt<5>(v) || v == -1); 234 break; 235 case Hexagon::C2_cmpgtui: 236 Valid = isUInt<5>(v); 237 break; 238 case Hexagon::S2_tstbit_i: 239 case Hexagon::S4_ntstbit_i: 240 Valid = (v == 0); 241 break; 242 } 243 244 if (!Valid) 245 return false; 246 } 247 248 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning. 249 cmpReg1 = MI.getOperand(1).getReg(); 250 251 if (secondReg) { 252 cmpOp2 = MI.getOperand(2).getReg(); 253 254 // If the same register appears as both operands, we cannot generate a new 255 // value compare. Only one operand may use the .new suffix. 256 if (cmpReg1 == cmpOp2) 257 return false; 258 259 // Make sure that that second register is not from COPY 260 // At machine code level, we don't need this, but if we decide 261 // to move new value jump prior to RA, we would be needing this. 262 MachineRegisterInfo &MRI = MF.getRegInfo(); 263 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) { 264 MachineInstr *def = MRI.getVRegDef(cmpOp2); 265 if (def->getOpcode() == TargetOpcode::COPY) 266 return false; 267 } 268 } 269 270 // Walk the instructions after the compare (predicate def) to the jump, 271 // and satisfy the following conditions. 272 ++II ; 273 for (MachineBasicBlock::iterator localII = II; localII != end; 274 ++localII) { 275 if (localII->isDebugValue()) 276 continue; 277 278 // Check 1. 279 // If "common" checks fail, bail out. 280 if (!commonChecksToProhibitNewValueJump(optLocation, localII)) 281 return false; 282 283 // Check 2. 284 // If there is a def or use of predicate (result of compare), bail out. 285 if (localII->modifiesRegister(pReg, TRI) || 286 localII->readsRegister(pReg, TRI)) 287 return false; 288 289 // Check 3. 290 // If there is a def of any of the use of the compare (operands of compare), 291 // bail out. 292 // Eg. 293 // p0 = cmp.eq(r2, r0) 294 // r2 = r4 295 // if (p0.new) jump:t .LBB28_3 296 if (localII->modifiesRegister(cmpReg1, TRI) || 297 (secondReg && localII->modifiesRegister(cmpOp2, TRI))) 298 return false; 299 } 300 return true; 301 } 302 303 304 // Given a compare operator, return a matching New Value Jump compare operator. 305 // Make sure that MI here is included in isNewValueJumpCandidate. 306 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, 307 bool secondRegNewified, 308 MachineBasicBlock *jmpTarget, 309 const MachineBranchProbabilityInfo 310 *MBPI) { 311 bool taken = false; 312 MachineBasicBlock *Src = MI->getParent(); 313 const BranchProbability Prediction = 314 MBPI->getEdgeProbability(Src, jmpTarget); 315 316 if (Prediction >= BranchProbability(1,2)) 317 taken = true; 318 319 switch (MI->getOpcode()) { 320 case Hexagon::C2_cmpeq: 321 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t 322 : Hexagon::J4_cmpeq_t_jumpnv_nt; 323 324 case Hexagon::C2_cmpeqi: { 325 if (reg >= 0) 326 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t 327 : Hexagon::J4_cmpeqi_t_jumpnv_nt; 328 else 329 return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t 330 : Hexagon::J4_cmpeqn1_t_jumpnv_nt; 331 } 332 333 case Hexagon::C2_cmpgt: { 334 if (secondRegNewified) 335 return taken ? Hexagon::J4_cmplt_t_jumpnv_t 336 : Hexagon::J4_cmplt_t_jumpnv_nt; 337 else 338 return taken ? Hexagon::J4_cmpgt_t_jumpnv_t 339 : Hexagon::J4_cmpgt_t_jumpnv_nt; 340 } 341 342 case Hexagon::C2_cmpgti: { 343 if (reg >= 0) 344 return taken ? Hexagon::J4_cmpgti_t_jumpnv_t 345 : Hexagon::J4_cmpgti_t_jumpnv_nt; 346 else 347 return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t 348 : Hexagon::J4_cmpgtn1_t_jumpnv_nt; 349 } 350 351 case Hexagon::C2_cmpgtu: { 352 if (secondRegNewified) 353 return taken ? Hexagon::J4_cmpltu_t_jumpnv_t 354 : Hexagon::J4_cmpltu_t_jumpnv_nt; 355 else 356 return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t 357 : Hexagon::J4_cmpgtu_t_jumpnv_nt; 358 } 359 360 case Hexagon::C2_cmpgtui: 361 return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t 362 : Hexagon::J4_cmpgtui_t_jumpnv_nt; 363 364 case Hexagon::C4_cmpneq: 365 return taken ? Hexagon::J4_cmpeq_f_jumpnv_t 366 : Hexagon::J4_cmpeq_f_jumpnv_nt; 367 368 case Hexagon::C4_cmplte: 369 if (secondRegNewified) 370 return taken ? Hexagon::J4_cmplt_f_jumpnv_t 371 : Hexagon::J4_cmplt_f_jumpnv_nt; 372 return taken ? Hexagon::J4_cmpgt_f_jumpnv_t 373 : Hexagon::J4_cmpgt_f_jumpnv_nt; 374 375 case Hexagon::C4_cmplteu: 376 if (secondRegNewified) 377 return taken ? Hexagon::J4_cmpltu_f_jumpnv_t 378 : Hexagon::J4_cmpltu_f_jumpnv_nt; 379 return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t 380 : Hexagon::J4_cmpgtu_f_jumpnv_nt; 381 382 default: 383 llvm_unreachable("Could not find matching New Value Jump instruction."); 384 } 385 // return *some value* to avoid compiler warning 386 return 0; 387 } 388 389 bool HexagonNewValueJump::isNewValueJumpCandidate( 390 const MachineInstr &MI) const { 391 switch (MI.getOpcode()) { 392 case Hexagon::C2_cmpeq: 393 case Hexagon::C2_cmpeqi: 394 case Hexagon::C2_cmpgt: 395 case Hexagon::C2_cmpgti: 396 case Hexagon::C2_cmpgtu: 397 case Hexagon::C2_cmpgtui: 398 case Hexagon::C4_cmpneq: 399 case Hexagon::C4_cmplte: 400 case Hexagon::C4_cmplteu: 401 return true; 402 403 default: 404 return false; 405 } 406 } 407 408 409 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { 410 411 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" 412 << "********** Function: " 413 << MF.getName() << "\n"); 414 415 if (skipFunction(*MF.getFunction())) 416 return false; 417 418 // If we move NewValueJump before register allocation we'll need live variable 419 // analysis here too. 420 421 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); 422 QRI = static_cast<const HexagonRegisterInfo *>( 423 MF.getSubtarget().getRegisterInfo()); 424 MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); 425 426 if (DisableNewValueJumps) { 427 return false; 428 } 429 430 int nvjCount = DbgNVJCount; 431 int nvjGenerated = 0; 432 433 // Loop through all the bb's of the function 434 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); 435 MBBb != MBBe; ++MBBb) { 436 MachineBasicBlock *MBB = &*MBBb; 437 438 DEBUG(dbgs() << "** dumping bb ** " 439 << MBB->getNumber() << "\n"); 440 DEBUG(MBB->dump()); 441 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n"); 442 bool foundJump = false; 443 bool foundCompare = false; 444 bool invertPredicate = false; 445 unsigned predReg = 0; // predicate reg of the jump. 446 unsigned cmpReg1 = 0; 447 int cmpOp2 = 0; 448 bool MO1IsKill = false; 449 bool MO2IsKill = false; 450 MachineBasicBlock::iterator jmpPos; 451 MachineBasicBlock::iterator cmpPos; 452 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr; 453 MachineBasicBlock *jmpTarget = nullptr; 454 bool afterRA = false; 455 bool isSecondOpReg = false; 456 bool isSecondOpNewified = false; 457 // Traverse the basic block - bottom up 458 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin(); 459 MII != E;) { 460 MachineInstr &MI = *--MII; 461 if (MI.isDebugValue()) { 462 continue; 463 } 464 465 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated)) 466 break; 467 468 DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n"); 469 470 if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt || 471 MI.getOpcode() == Hexagon::J2_jumptpt || 472 MI.getOpcode() == Hexagon::J2_jumpf || 473 MI.getOpcode() == Hexagon::J2_jumpfpt || 474 MI.getOpcode() == Hexagon::J2_jumptnewpt || 475 MI.getOpcode() == Hexagon::J2_jumptnew || 476 MI.getOpcode() == Hexagon::J2_jumpfnewpt || 477 MI.getOpcode() == Hexagon::J2_jumpfnew)) { 478 // This is where you would insert your compare and 479 // instr that feeds compare 480 jmpPos = MII; 481 jmpInstr = &MI; 482 predReg = MI.getOperand(0).getReg(); 483 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg); 484 485 // If ifconverter had not messed up with the kill flags of the 486 // operands, the following check on the kill flag would suffice. 487 // if(!jmpInstr->getOperand(0).isKill()) break; 488 489 // This predicate register is live out out of BB 490 // this would only work if we can actually use Live 491 // variable analysis on phy regs - but LLVM does not 492 // provide LV analysis on phys regs. 493 //if(LVs.isLiveOut(predReg, *MBB)) break; 494 495 // Get all the successors of this block - which will always 496 // be 2. Check if the predicate register is live-in in those 497 // successor. If yes, we can not delete the predicate - 498 // I am doing this only because LLVM does not provide LiveOut 499 // at the BB level. 500 bool predLive = false; 501 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(), 502 SIE = MBB->succ_end(); SI != SIE; ++SI) { 503 MachineBasicBlock* succMBB = *SI; 504 if (succMBB->isLiveIn(predReg)) { 505 predLive = true; 506 } 507 } 508 if (predLive) 509 break; 510 511 if (!MI.getOperand(1).isMBB()) 512 continue; 513 jmpTarget = MI.getOperand(1).getMBB(); 514 foundJump = true; 515 if (MI.getOpcode() == Hexagon::J2_jumpf || 516 MI.getOpcode() == Hexagon::J2_jumpfnewpt || 517 MI.getOpcode() == Hexagon::J2_jumpfnew) { 518 invertPredicate = true; 519 } 520 continue; 521 } 522 523 // No new value jump if there is a barrier. A barrier has to be in its 524 // own packet. A barrier has zero operands. We conservatively bail out 525 // here if we see any instruction with zero operands. 526 if (foundJump && MI.getNumOperands() == 0) 527 break; 528 529 if (foundJump && !foundCompare && MI.getOperand(0).isReg() && 530 MI.getOperand(0).getReg() == predReg) { 531 532 // Not all compares can be new value compare. Arch Spec: 7.6.1.1 533 if (isNewValueJumpCandidate(MI)) { 534 535 assert( 536 (MI.getDesc().isCompare()) && 537 "Only compare instruction can be collapsed into New Value Jump"); 538 isSecondOpReg = MI.getOperand(2).isReg(); 539 540 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg, 541 afterRA, jmpPos, MF)) 542 break; 543 544 cmpInstr = &MI; 545 cmpPos = MII; 546 foundCompare = true; 547 548 // We need cmpReg1 and cmpOp2(imm or reg) while building 549 // new value jump instruction. 550 cmpReg1 = MI.getOperand(1).getReg(); 551 if (MI.getOperand(1).isKill()) 552 MO1IsKill = true; 553 554 if (isSecondOpReg) { 555 cmpOp2 = MI.getOperand(2).getReg(); 556 if (MI.getOperand(2).isKill()) 557 MO2IsKill = true; 558 } else 559 cmpOp2 = MI.getOperand(2).getImm(); 560 continue; 561 } 562 } 563 564 if (foundCompare && foundJump) { 565 566 // If "common" checks fail, bail out on this BB. 567 if (!commonChecksToProhibitNewValueJump(afterRA, MII)) 568 break; 569 570 bool foundFeeder = false; 571 MachineBasicBlock::iterator feederPos = MII; 572 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && 573 (MI.getOperand(0).getReg() == cmpReg1 || 574 (isSecondOpReg && 575 MI.getOperand(0).getReg() == (unsigned)cmpOp2))) { 576 577 unsigned feederReg = MI.getOperand(0).getReg(); 578 579 // First try to see if we can get the feeder from the first operand 580 // of the compare. If we can not, and if secondOpReg is true 581 // (second operand of the compare is also register), try that one. 582 // TODO: Try to come up with some heuristic to figure out which 583 // feeder would benefit. 584 585 if (feederReg == cmpReg1) { 586 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) { 587 if (!isSecondOpReg) 588 break; 589 else 590 continue; 591 } else 592 foundFeeder = true; 593 } 594 595 if (!foundFeeder && 596 isSecondOpReg && 597 feederReg == (unsigned) cmpOp2) 598 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) 599 break; 600 601 if (isSecondOpReg) { 602 // In case of CMPLT, or CMPLTU, or EQ with the second register 603 // to newify, swap the operands. 604 unsigned COp = cmpInstr->getOpcode(); 605 if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) && 606 (feederReg == (unsigned) cmpOp2)) { 607 unsigned tmp = cmpReg1; 608 bool tmpIsKill = MO1IsKill; 609 cmpReg1 = cmpOp2; 610 MO1IsKill = MO2IsKill; 611 cmpOp2 = tmp; 612 MO2IsKill = tmpIsKill; 613 } 614 615 // Now we have swapped the operands, all we need to check is, 616 // if the second operand (after swap) is the feeder. 617 // And if it is, make a note. 618 if (feederReg == (unsigned)cmpOp2) 619 isSecondOpNewified = true; 620 } 621 622 // Now that we are moving feeder close the jump, 623 // make sure we are respecting the kill values of 624 // the operands of the feeder. 625 626 bool updatedIsKill = false; 627 for (unsigned i = 0; i < MI.getNumOperands(); i++) { 628 MachineOperand &MO = MI.getOperand(i); 629 if (MO.isReg() && MO.isUse()) { 630 unsigned feederReg = MO.getReg(); 631 for (MachineBasicBlock::iterator localII = feederPos, 632 end = jmpPos; localII != end; localII++) { 633 MachineInstr &localMI = *localII; 634 for (unsigned j = 0; j < localMI.getNumOperands(); j++) { 635 MachineOperand &localMO = localMI.getOperand(j); 636 if (localMO.isReg() && localMO.isUse() && 637 localMO.isKill() && feederReg == localMO.getReg()) { 638 // We found that there is kill of a use register 639 // Set up a kill flag on the register 640 localMO.setIsKill(false); 641 MO.setIsKill(); 642 updatedIsKill = true; 643 break; 644 } 645 } 646 if (updatedIsKill) break; 647 } 648 } 649 if (updatedIsKill) break; 650 } 651 652 MBB->splice(jmpPos, MI.getParent(), MI); 653 MBB->splice(jmpPos, MI.getParent(), cmpInstr); 654 DebugLoc dl = MI.getDebugLoc(); 655 MachineInstr *NewMI; 656 657 assert((isNewValueJumpCandidate(*cmpInstr)) && 658 "This compare is not a New Value Jump candidate."); 659 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, 660 isSecondOpNewified, 661 jmpTarget, MBPI); 662 if (invertPredicate) 663 opc = QII->getInvertedPredicatedOpcode(opc); 664 665 if (isSecondOpReg) 666 NewMI = BuildMI(*MBB, jmpPos, dl, 667 QII->get(opc)) 668 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 669 .addReg(cmpOp2, getKillRegState(MO2IsKill)) 670 .addMBB(jmpTarget); 671 672 else 673 NewMI = BuildMI(*MBB, jmpPos, dl, 674 QII->get(opc)) 675 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 676 .addImm(cmpOp2) 677 .addMBB(jmpTarget); 678 679 assert(NewMI && "New Value Jump Instruction Not created!"); 680 (void)NewMI; 681 if (cmpInstr->getOperand(0).isReg() && 682 cmpInstr->getOperand(0).isKill()) 683 cmpInstr->getOperand(0).setIsKill(false); 684 if (cmpInstr->getOperand(1).isReg() && 685 cmpInstr->getOperand(1).isKill()) 686 cmpInstr->getOperand(1).setIsKill(false); 687 cmpInstr->eraseFromParent(); 688 jmpInstr->eraseFromParent(); 689 ++nvjGenerated; 690 ++NumNVJGenerated; 691 break; 692 } 693 } 694 } 695 } 696 697 return true; 698 699 } 700 701 FunctionPass *llvm::createHexagonNewValueJump() { 702 return new HexagonNewValueJump(); 703 } 704