1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements NewValueJump pass in Hexagon. 11 // Ideally, we should merge this as a Peephole pass prior to register 12 // allocation, but because we have a spill in between the feeder and new value 13 // jump instructions, we are forced to write after register allocation. 14 // Having said that, we should re-attempt to pull this earlier at some point 15 // in future. 16 17 // The basic approach looks for sequence of predicated jump, compare instruciton 18 // that genereates the predicate and, the feeder to the predicate. Once it finds 19 // all, it collapses compare and jump instruction into a new valu jump 20 // intstructions. 21 // 22 // 23 //===----------------------------------------------------------------------===// 24 #include "Hexagon.h" 25 #include "HexagonInstrInfo.h" 26 #include "HexagonMachineFunctionInfo.h" 27 #include "HexagonRegisterInfo.h" 28 #include "HexagonSubtarget.h" 29 #include "HexagonTargetMachine.h" 30 #include "llvm/ADT/Statistic.h" 31 #include "llvm/CodeGen/LiveVariables.h" 32 #include "llvm/CodeGen/MachineFunctionAnalysis.h" 33 #include "llvm/CodeGen/MachineFunctionPass.h" 34 #include "llvm/CodeGen/MachineInstrBuilder.h" 35 #include "llvm/CodeGen/MachineRegisterInfo.h" 36 #include "llvm/CodeGen/Passes.h" 37 #include "llvm/CodeGen/ScheduleDAGInstrs.h" 38 #include "llvm/PassSupport.h" 39 #include "llvm/Support/CommandLine.h" 40 #include "llvm/Support/Debug.h" 41 #include "llvm/Support/raw_ostream.h" 42 #include "llvm/Target/TargetInstrInfo.h" 43 #include "llvm/Target/TargetMachine.h" 44 #include "llvm/Target/TargetRegisterInfo.h" 45 using namespace llvm; 46 47 #define DEBUG_TYPE "hexagon-nvj" 48 49 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created"); 50 51 static cl::opt<int> 52 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc( 53 "Maximum number of predicated jumps to be converted to New Value Jump")); 54 55 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden, 56 cl::ZeroOrMore, cl::init(false), 57 cl::desc("Disable New Value Jumps")); 58 59 namespace llvm { 60 FunctionPass *createHexagonNewValueJump(); 61 void initializeHexagonNewValueJumpPass(PassRegistry&); 62 } 63 64 65 namespace { 66 struct HexagonNewValueJump : public MachineFunctionPass { 67 const HexagonInstrInfo *QII; 68 const HexagonRegisterInfo *QRI; 69 70 public: 71 static char ID; 72 73 HexagonNewValueJump() : MachineFunctionPass(ID) { 74 initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry()); 75 } 76 77 void getAnalysisUsage(AnalysisUsage &AU) const override { 78 AU.addRequired<MachineBranchProbabilityInfo>(); 79 MachineFunctionPass::getAnalysisUsage(AU); 80 } 81 82 const char *getPassName() const override { 83 return "Hexagon NewValueJump"; 84 } 85 86 bool runOnMachineFunction(MachineFunction &Fn) override; 87 MachineFunctionProperties getRequiredProperties() const override { 88 return MachineFunctionProperties().set( 89 MachineFunctionProperties::Property::AllVRegsAllocated); 90 } 91 92 private: 93 /// \brief A handle to the branch probability pass. 94 const MachineBranchProbabilityInfo *MBPI; 95 96 bool isNewValueJumpCandidate(const MachineInstr *MI) const; 97 }; 98 99 } // end of anonymous namespace 100 101 char HexagonNewValueJump::ID = 0; 102 103 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", 104 "Hexagon NewValueJump", false, false) 105 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) 106 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj", 107 "Hexagon NewValueJump", false, false) 108 109 110 // We have identified this II could be feeder to NVJ, 111 // verify that it can be. 112 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, 113 const TargetRegisterInfo *TRI, 114 MachineBasicBlock::iterator II, 115 MachineBasicBlock::iterator end, 116 MachineBasicBlock::iterator skip, 117 MachineFunction &MF) { 118 119 // Predicated instruction can not be feeder to NVJ. 120 if (QII->isPredicated(*II)) 121 return false; 122 123 // Bail out if feederReg is a paired register (double regs in 124 // our case). One would think that we can check to see if a given 125 // register cmpReg1 or cmpReg2 is a sub register of feederReg 126 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic 127 // before the callsite of this function 128 // But we can not as it comes in the following fashion. 129 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> 130 // %R0<def> = KILL %R0, %D0<imp-use,kill> 131 // %P0<def> = CMPEQri %R0<kill>, 0 132 // Hence, we need to check if it's a KILL instruction. 133 if (II->getOpcode() == TargetOpcode::KILL) 134 return false; 135 136 137 // Make sure there there is no 'def' or 'use' of any of the uses of 138 // feeder insn between it's definition, this MI and jump, jmpInst 139 // skipping compare, cmpInst. 140 // Here's the example. 141 // r21=memub(r22+r24<<#0) 142 // p0 = cmp.eq(r21, #0) 143 // r4=memub(r3+r21<<#0) 144 // if (p0.new) jump:t .LBB29_45 145 // Without this check, it will be converted into 146 // r4=memub(r3+r21<<#0) 147 // r21=memub(r22+r24<<#0) 148 // p0 = cmp.eq(r21, #0) 149 // if (p0.new) jump:t .LBB29_45 150 // and result WAR hazards if converted to New Value Jump. 151 152 for (unsigned i = 0; i < II->getNumOperands(); ++i) { 153 if (II->getOperand(i).isReg() && 154 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { 155 MachineBasicBlock::iterator localII = II; 156 ++localII; 157 unsigned Reg = II->getOperand(i).getReg(); 158 for (MachineBasicBlock::iterator localBegin = localII; 159 localBegin != end; ++localBegin) { 160 if (localBegin == skip ) continue; 161 // Check for Subregisters too. 162 if (localBegin->modifiesRegister(Reg, TRI) || 163 localBegin->readsRegister(Reg, TRI)) 164 return false; 165 } 166 } 167 } 168 return true; 169 } 170 171 // These are the common checks that need to performed 172 // to determine if 173 // 1. compare instruction can be moved before jump. 174 // 2. feeder to the compare instruction can be moved before jump. 175 static bool commonChecksToProhibitNewValueJump(bool afterRA, 176 MachineBasicBlock::iterator MII) { 177 178 // If store in path, bail out. 179 if (MII->getDesc().mayStore()) 180 return false; 181 182 // if call in path, bail out. 183 if (MII->getOpcode() == Hexagon::J2_call) 184 return false; 185 186 // if NVJ is running prior to RA, do the following checks. 187 if (!afterRA) { 188 // The following Target Opcode instructions are spurious 189 // to new value jump. If they are in the path, bail out. 190 // KILL sets kill flag on the opcode. It also sets up a 191 // single register, out of pair. 192 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> 193 // %R0<def> = KILL %R0, %D0<imp-use,kill> 194 // %P0<def> = CMPEQri %R0<kill>, 0 195 // PHI can be anything after RA. 196 // COPY can remateriaze things in between feeder, compare and nvj. 197 if (MII->getOpcode() == TargetOpcode::KILL || 198 MII->getOpcode() == TargetOpcode::PHI || 199 MII->getOpcode() == TargetOpcode::COPY) 200 return false; 201 202 // The following pseudo Hexagon instructions sets "use" and "def" 203 // of registers by individual passes in the backend. At this time, 204 // we don't know the scope of usage and definitions of these 205 // instructions. 206 if (MII->getOpcode() == Hexagon::LDriw_pred || 207 MII->getOpcode() == Hexagon::STriw_pred) 208 return false; 209 } 210 211 return true; 212 } 213 214 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, 215 const TargetRegisterInfo *TRI, 216 MachineBasicBlock::iterator II, 217 unsigned pReg, 218 bool secondReg, 219 bool optLocation, 220 MachineBasicBlock::iterator end, 221 MachineFunction &MF) { 222 223 MachineInstr *MI = II; 224 225 // If the second operand of the compare is an imm, make sure it's in the 226 // range specified by the arch. 227 if (!secondReg) { 228 int64_t v = MI->getOperand(2).getImm(); 229 230 if (!(isUInt<5>(v) || 231 ((MI->getOpcode() == Hexagon::C2_cmpeqi || 232 MI->getOpcode() == Hexagon::C2_cmpgti) && 233 (v == -1)))) 234 return false; 235 } 236 237 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning. 238 cmpReg1 = MI->getOperand(1).getReg(); 239 240 if (secondReg) { 241 cmpOp2 = MI->getOperand(2).getReg(); 242 243 // Make sure that that second register is not from COPY 244 // At machine code level, we don't need this, but if we decide 245 // to move new value jump prior to RA, we would be needing this. 246 MachineRegisterInfo &MRI = MF.getRegInfo(); 247 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) { 248 MachineInstr *def = MRI.getVRegDef(cmpOp2); 249 if (def->getOpcode() == TargetOpcode::COPY) 250 return false; 251 } 252 } 253 254 // Walk the instructions after the compare (predicate def) to the jump, 255 // and satisfy the following conditions. 256 ++II ; 257 for (MachineBasicBlock::iterator localII = II; localII != end; 258 ++localII) { 259 260 // Check 1. 261 // If "common" checks fail, bail out. 262 if (!commonChecksToProhibitNewValueJump(optLocation, localII)) 263 return false; 264 265 // Check 2. 266 // If there is a def or use of predicate (result of compare), bail out. 267 if (localII->modifiesRegister(pReg, TRI) || 268 localII->readsRegister(pReg, TRI)) 269 return false; 270 271 // Check 3. 272 // If there is a def of any of the use of the compare (operands of compare), 273 // bail out. 274 // Eg. 275 // p0 = cmp.eq(r2, r0) 276 // r2 = r4 277 // if (p0.new) jump:t .LBB28_3 278 if (localII->modifiesRegister(cmpReg1, TRI) || 279 (secondReg && localII->modifiesRegister(cmpOp2, TRI))) 280 return false; 281 } 282 return true; 283 } 284 285 286 // Given a compare operator, return a matching New Value Jump compare operator. 287 // Make sure that MI here is included in isNewValueJumpCandidate. 288 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, 289 bool secondRegNewified, 290 MachineBasicBlock *jmpTarget, 291 const MachineBranchProbabilityInfo 292 *MBPI) { 293 bool taken = false; 294 MachineBasicBlock *Src = MI->getParent(); 295 const BranchProbability Prediction = 296 MBPI->getEdgeProbability(Src, jmpTarget); 297 298 if (Prediction >= BranchProbability(1,2)) 299 taken = true; 300 301 switch (MI->getOpcode()) { 302 case Hexagon::C2_cmpeq: 303 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t 304 : Hexagon::J4_cmpeq_t_jumpnv_nt; 305 306 case Hexagon::C2_cmpeqi: { 307 if (reg >= 0) 308 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t 309 : Hexagon::J4_cmpeqi_t_jumpnv_nt; 310 else 311 return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t 312 : Hexagon::J4_cmpeqn1_t_jumpnv_nt; 313 } 314 315 case Hexagon::C2_cmpgt: { 316 if (secondRegNewified) 317 return taken ? Hexagon::J4_cmplt_t_jumpnv_t 318 : Hexagon::J4_cmplt_t_jumpnv_nt; 319 else 320 return taken ? Hexagon::J4_cmpgt_t_jumpnv_t 321 : Hexagon::J4_cmpgt_t_jumpnv_nt; 322 } 323 324 case Hexagon::C2_cmpgti: { 325 if (reg >= 0) 326 return taken ? Hexagon::J4_cmpgti_t_jumpnv_t 327 : Hexagon::J4_cmpgti_t_jumpnv_nt; 328 else 329 return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t 330 : Hexagon::J4_cmpgtn1_t_jumpnv_nt; 331 } 332 333 case Hexagon::C2_cmpgtu: { 334 if (secondRegNewified) 335 return taken ? Hexagon::J4_cmpltu_t_jumpnv_t 336 : Hexagon::J4_cmpltu_t_jumpnv_nt; 337 else 338 return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t 339 : Hexagon::J4_cmpgtu_t_jumpnv_nt; 340 } 341 342 case Hexagon::C2_cmpgtui: 343 return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t 344 : Hexagon::J4_cmpgtui_t_jumpnv_nt; 345 346 case Hexagon::C4_cmpneq: 347 return taken ? Hexagon::J4_cmpeq_f_jumpnv_t 348 : Hexagon::J4_cmpeq_f_jumpnv_nt; 349 350 case Hexagon::C4_cmplte: 351 if (secondRegNewified) 352 return taken ? Hexagon::J4_cmplt_f_jumpnv_t 353 : Hexagon::J4_cmplt_f_jumpnv_nt; 354 return taken ? Hexagon::J4_cmpgt_f_jumpnv_t 355 : Hexagon::J4_cmpgt_f_jumpnv_nt; 356 357 case Hexagon::C4_cmplteu: 358 if (secondRegNewified) 359 return taken ? Hexagon::J4_cmpltu_f_jumpnv_t 360 : Hexagon::J4_cmpltu_f_jumpnv_nt; 361 return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t 362 : Hexagon::J4_cmpgtu_f_jumpnv_nt; 363 364 default: 365 llvm_unreachable("Could not find matching New Value Jump instruction."); 366 } 367 // return *some value* to avoid compiler warning 368 return 0; 369 } 370 371 bool HexagonNewValueJump::isNewValueJumpCandidate(const MachineInstr *MI) 372 const { 373 switch (MI->getOpcode()) { 374 case Hexagon::C2_cmpeq: 375 case Hexagon::C2_cmpeqi: 376 case Hexagon::C2_cmpgt: 377 case Hexagon::C2_cmpgti: 378 case Hexagon::C2_cmpgtu: 379 case Hexagon::C2_cmpgtui: 380 case Hexagon::C4_cmpneq: 381 case Hexagon::C4_cmplte: 382 case Hexagon::C4_cmplteu: 383 return true; 384 385 default: 386 return false; 387 } 388 } 389 390 391 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { 392 393 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" 394 << "********** Function: " 395 << MF.getName() << "\n"); 396 397 if (skipFunction(*MF.getFunction())) 398 return false; 399 400 // If we move NewValueJump before register allocation we'll need live variable 401 // analysis here too. 402 403 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); 404 QRI = static_cast<const HexagonRegisterInfo *>( 405 MF.getSubtarget().getRegisterInfo()); 406 MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); 407 408 if (DisableNewValueJumps) { 409 return false; 410 } 411 412 int nvjCount = DbgNVJCount; 413 int nvjGenerated = 0; 414 415 // Loop through all the bb's of the function 416 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); 417 MBBb != MBBe; ++MBBb) { 418 MachineBasicBlock *MBB = &*MBBb; 419 420 DEBUG(dbgs() << "** dumping bb ** " 421 << MBB->getNumber() << "\n"); 422 DEBUG(MBB->dump()); 423 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n"); 424 bool foundJump = false; 425 bool foundCompare = false; 426 bool invertPredicate = false; 427 unsigned predReg = 0; // predicate reg of the jump. 428 unsigned cmpReg1 = 0; 429 int cmpOp2 = 0; 430 bool MO1IsKill = false; 431 bool MO2IsKill = false; 432 MachineBasicBlock::iterator jmpPos; 433 MachineBasicBlock::iterator cmpPos; 434 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr; 435 MachineBasicBlock *jmpTarget = nullptr; 436 bool afterRA = false; 437 bool isSecondOpReg = false; 438 bool isSecondOpNewified = false; 439 // Traverse the basic block - bottom up 440 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin(); 441 MII != E;) { 442 MachineInstr *MI = --MII; 443 if (MI->isDebugValue()) { 444 continue; 445 } 446 447 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated)) 448 break; 449 450 DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n"); 451 452 if (!foundJump && 453 (MI->getOpcode() == Hexagon::J2_jumpt || 454 MI->getOpcode() == Hexagon::J2_jumpf || 455 MI->getOpcode() == Hexagon::J2_jumptnewpt || 456 MI->getOpcode() == Hexagon::J2_jumptnew || 457 MI->getOpcode() == Hexagon::J2_jumpfnewpt || 458 MI->getOpcode() == Hexagon::J2_jumpfnew)) { 459 // This is where you would insert your compare and 460 // instr that feeds compare 461 jmpPos = MII; 462 jmpInstr = MI; 463 predReg = MI->getOperand(0).getReg(); 464 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg); 465 466 // If ifconverter had not messed up with the kill flags of the 467 // operands, the following check on the kill flag would suffice. 468 // if(!jmpInstr->getOperand(0).isKill()) break; 469 470 // This predicate register is live out out of BB 471 // this would only work if we can actually use Live 472 // variable analysis on phy regs - but LLVM does not 473 // provide LV analysis on phys regs. 474 //if(LVs.isLiveOut(predReg, *MBB)) break; 475 476 // Get all the successors of this block - which will always 477 // be 2. Check if the predicate register is live in in those 478 // successor. If yes, we can not delete the predicate - 479 // I am doing this only because LLVM does not provide LiveOut 480 // at the BB level. 481 bool predLive = false; 482 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(), 483 SIE = MBB->succ_end(); SI != SIE; ++SI) { 484 MachineBasicBlock* succMBB = *SI; 485 if (succMBB->isLiveIn(predReg)) { 486 predLive = true; 487 } 488 } 489 if (predLive) 490 break; 491 492 if (!MI->getOperand(1).isMBB()) 493 continue; 494 jmpTarget = MI->getOperand(1).getMBB(); 495 foundJump = true; 496 if (MI->getOpcode() == Hexagon::J2_jumpf || 497 MI->getOpcode() == Hexagon::J2_jumpfnewpt || 498 MI->getOpcode() == Hexagon::J2_jumpfnew) { 499 invertPredicate = true; 500 } 501 continue; 502 } 503 504 // No new value jump if there is a barrier. A barrier has to be in its 505 // own packet. A barrier has zero operands. We conservatively bail out 506 // here if we see any instruction with zero operands. 507 if (foundJump && MI->getNumOperands() == 0) 508 break; 509 510 if (foundJump && 511 !foundCompare && 512 MI->getOperand(0).isReg() && 513 MI->getOperand(0).getReg() == predReg) { 514 515 // Not all compares can be new value compare. Arch Spec: 7.6.1.1 516 if (isNewValueJumpCandidate(MI)) { 517 518 assert((MI->getDesc().isCompare()) && 519 "Only compare instruction can be collapsed into New Value Jump"); 520 isSecondOpReg = MI->getOperand(2).isReg(); 521 522 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg, 523 afterRA, jmpPos, MF)) 524 break; 525 526 cmpInstr = MI; 527 cmpPos = MII; 528 foundCompare = true; 529 530 // We need cmpReg1 and cmpOp2(imm or reg) while building 531 // new value jump instruction. 532 cmpReg1 = MI->getOperand(1).getReg(); 533 if (MI->getOperand(1).isKill()) 534 MO1IsKill = true; 535 536 if (isSecondOpReg) { 537 cmpOp2 = MI->getOperand(2).getReg(); 538 if (MI->getOperand(2).isKill()) 539 MO2IsKill = true; 540 } else 541 cmpOp2 = MI->getOperand(2).getImm(); 542 continue; 543 } 544 } 545 546 if (foundCompare && foundJump) { 547 548 // If "common" checks fail, bail out on this BB. 549 if (!commonChecksToProhibitNewValueJump(afterRA, MII)) 550 break; 551 552 bool foundFeeder = false; 553 MachineBasicBlock::iterator feederPos = MII; 554 if (MI->getOperand(0).isReg() && 555 MI->getOperand(0).isDef() && 556 (MI->getOperand(0).getReg() == cmpReg1 || 557 (isSecondOpReg && 558 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) { 559 560 unsigned feederReg = MI->getOperand(0).getReg(); 561 562 // First try to see if we can get the feeder from the first operand 563 // of the compare. If we can not, and if secondOpReg is true 564 // (second operand of the compare is also register), try that one. 565 // TODO: Try to come up with some heuristic to figure out which 566 // feeder would benefit. 567 568 if (feederReg == cmpReg1) { 569 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) { 570 if (!isSecondOpReg) 571 break; 572 else 573 continue; 574 } else 575 foundFeeder = true; 576 } 577 578 if (!foundFeeder && 579 isSecondOpReg && 580 feederReg == (unsigned) cmpOp2) 581 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) 582 break; 583 584 if (isSecondOpReg) { 585 // In case of CMPLT, or CMPLTU, or EQ with the second register 586 // to newify, swap the operands. 587 if (cmpInstr->getOpcode() == Hexagon::C2_cmpeq && 588 feederReg == (unsigned) cmpOp2) { 589 unsigned tmp = cmpReg1; 590 bool tmpIsKill = MO1IsKill; 591 cmpReg1 = cmpOp2; 592 MO1IsKill = MO2IsKill; 593 cmpOp2 = tmp; 594 MO2IsKill = tmpIsKill; 595 } 596 597 // Now we have swapped the operands, all we need to check is, 598 // if the second operand (after swap) is the feeder. 599 // And if it is, make a note. 600 if (feederReg == (unsigned)cmpOp2) 601 isSecondOpNewified = true; 602 } 603 604 // Now that we are moving feeder close the jump, 605 // make sure we are respecting the kill values of 606 // the operands of the feeder. 607 608 bool updatedIsKill = false; 609 for (unsigned i = 0; i < MI->getNumOperands(); i++) { 610 MachineOperand &MO = MI->getOperand(i); 611 if (MO.isReg() && MO.isUse()) { 612 unsigned feederReg = MO.getReg(); 613 for (MachineBasicBlock::iterator localII = feederPos, 614 end = jmpPos; localII != end; localII++) { 615 MachineInstr *localMI = localII; 616 for (unsigned j = 0; j < localMI->getNumOperands(); j++) { 617 MachineOperand &localMO = localMI->getOperand(j); 618 if (localMO.isReg() && localMO.isUse() && 619 localMO.isKill() && feederReg == localMO.getReg()) { 620 // We found that there is kill of a use register 621 // Set up a kill flag on the register 622 localMO.setIsKill(false); 623 MO.setIsKill(); 624 updatedIsKill = true; 625 break; 626 } 627 } 628 if (updatedIsKill) break; 629 } 630 } 631 if (updatedIsKill) break; 632 } 633 634 MBB->splice(jmpPos, MI->getParent(), MI); 635 MBB->splice(jmpPos, MI->getParent(), cmpInstr); 636 DebugLoc dl = MI->getDebugLoc(); 637 MachineInstr *NewMI; 638 639 assert((isNewValueJumpCandidate(cmpInstr)) && 640 "This compare is not a New Value Jump candidate."); 641 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, 642 isSecondOpNewified, 643 jmpTarget, MBPI); 644 if (invertPredicate) 645 opc = QII->getInvertedPredicatedOpcode(opc); 646 647 if (isSecondOpReg) 648 NewMI = BuildMI(*MBB, jmpPos, dl, 649 QII->get(opc)) 650 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 651 .addReg(cmpOp2, getKillRegState(MO2IsKill)) 652 .addMBB(jmpTarget); 653 654 else if ((cmpInstr->getOpcode() == Hexagon::C2_cmpeqi || 655 cmpInstr->getOpcode() == Hexagon::C2_cmpgti) && 656 cmpOp2 == -1 ) 657 // Corresponding new-value compare jump instructions don't have the 658 // operand for -1 immediate value. 659 NewMI = BuildMI(*MBB, jmpPos, dl, 660 QII->get(opc)) 661 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 662 .addMBB(jmpTarget); 663 664 else 665 NewMI = BuildMI(*MBB, jmpPos, dl, 666 QII->get(opc)) 667 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 668 .addImm(cmpOp2) 669 .addMBB(jmpTarget); 670 671 assert(NewMI && "New Value Jump Instruction Not created!"); 672 (void)NewMI; 673 if (cmpInstr->getOperand(0).isReg() && 674 cmpInstr->getOperand(0).isKill()) 675 cmpInstr->getOperand(0).setIsKill(false); 676 if (cmpInstr->getOperand(1).isReg() && 677 cmpInstr->getOperand(1).isKill()) 678 cmpInstr->getOperand(1).setIsKill(false); 679 cmpInstr->eraseFromParent(); 680 jmpInstr->eraseFromParent(); 681 ++nvjGenerated; 682 ++NumNVJGenerated; 683 break; 684 } 685 } 686 } 687 } 688 689 return true; 690 691 } 692 693 FunctionPass *llvm::createHexagonNewValueJump() { 694 return new HexagonNewValueJump(); 695 } 696