1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements NewValueJump pass in Hexagon. 11 // Ideally, we should merge this as a Peephole pass prior to register 12 // allocation, but because we have a spill in between the feeder and new value 13 // jump instructions, we are forced to write after register allocation. 14 // Having said that, we should re-attempt to pull this earlier at some point 15 // in future. 16 17 // The basic approach looks for sequence of predicated jump, compare instruciton 18 // that genereates the predicate and, the feeder to the predicate. Once it finds 19 // all, it collapses compare and jump instruction into a new valu jump 20 // intstructions. 21 // 22 // 23 //===----------------------------------------------------------------------===// 24 #include "Hexagon.h" 25 #include "HexagonInstrInfo.h" 26 #include "HexagonMachineFunctionInfo.h" 27 #include "HexagonRegisterInfo.h" 28 #include "HexagonSubtarget.h" 29 #include "HexagonTargetMachine.h" 30 #include "llvm/ADT/Statistic.h" 31 #include "llvm/CodeGen/LiveVariables.h" 32 #include "llvm/CodeGen/MachineFunctionPass.h" 33 #include "llvm/CodeGen/MachineInstrBuilder.h" 34 #include "llvm/CodeGen/MachineRegisterInfo.h" 35 #include "llvm/CodeGen/Passes.h" 36 #include "llvm/CodeGen/ScheduleDAGInstrs.h" 37 #include "llvm/PassSupport.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/raw_ostream.h" 41 #include "llvm/Target/TargetInstrInfo.h" 42 #include "llvm/Target/TargetMachine.h" 43 #include "llvm/Target/TargetRegisterInfo.h" 44 using namespace llvm; 45 46 #define DEBUG_TYPE "hexagon-nvj" 47 48 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created"); 49 50 static cl::opt<int> 51 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc( 52 "Maximum number of predicated jumps to be converted to New Value Jump")); 53 54 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden, 55 cl::ZeroOrMore, cl::init(false), 56 cl::desc("Disable New Value Jumps")); 57 58 namespace llvm { 59 FunctionPass *createHexagonNewValueJump(); 60 void initializeHexagonNewValueJumpPass(PassRegistry&); 61 } 62 63 64 namespace { 65 struct HexagonNewValueJump : public MachineFunctionPass { 66 const HexagonInstrInfo *QII; 67 const HexagonRegisterInfo *QRI; 68 69 public: 70 static char ID; 71 72 HexagonNewValueJump() : MachineFunctionPass(ID) { 73 initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry()); 74 } 75 76 void getAnalysisUsage(AnalysisUsage &AU) const override { 77 AU.addRequired<MachineBranchProbabilityInfo>(); 78 MachineFunctionPass::getAnalysisUsage(AU); 79 } 80 81 StringRef getPassName() const override { return "Hexagon NewValueJump"; } 82 83 bool runOnMachineFunction(MachineFunction &Fn) override; 84 MachineFunctionProperties getRequiredProperties() const override { 85 return MachineFunctionProperties().set( 86 MachineFunctionProperties::Property::NoVRegs); 87 } 88 89 private: 90 /// \brief A handle to the branch probability pass. 91 const MachineBranchProbabilityInfo *MBPI; 92 93 bool isNewValueJumpCandidate(const MachineInstr &MI) const; 94 }; 95 96 } // end of anonymous namespace 97 98 char HexagonNewValueJump::ID = 0; 99 100 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", 101 "Hexagon NewValueJump", false, false) 102 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) 103 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj", 104 "Hexagon NewValueJump", false, false) 105 106 107 // We have identified this II could be feeder to NVJ, 108 // verify that it can be. 109 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, 110 const TargetRegisterInfo *TRI, 111 MachineBasicBlock::iterator II, 112 MachineBasicBlock::iterator end, 113 MachineBasicBlock::iterator skip, 114 MachineFunction &MF) { 115 116 // Predicated instruction can not be feeder to NVJ. 117 if (QII->isPredicated(*II)) 118 return false; 119 120 // Bail out if feederReg is a paired register (double regs in 121 // our case). One would think that we can check to see if a given 122 // register cmpReg1 or cmpReg2 is a sub register of feederReg 123 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic 124 // before the callsite of this function 125 // But we can not as it comes in the following fashion. 126 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> 127 // %R0<def> = KILL %R0, %D0<imp-use,kill> 128 // %P0<def> = CMPEQri %R0<kill>, 0 129 // Hence, we need to check if it's a KILL instruction. 130 if (II->getOpcode() == TargetOpcode::KILL) 131 return false; 132 133 134 // Make sure there there is no 'def' or 'use' of any of the uses of 135 // feeder insn between it's definition, this MI and jump, jmpInst 136 // skipping compare, cmpInst. 137 // Here's the example. 138 // r21=memub(r22+r24<<#0) 139 // p0 = cmp.eq(r21, #0) 140 // r4=memub(r3+r21<<#0) 141 // if (p0.new) jump:t .LBB29_45 142 // Without this check, it will be converted into 143 // r4=memub(r3+r21<<#0) 144 // r21=memub(r22+r24<<#0) 145 // p0 = cmp.eq(r21, #0) 146 // if (p0.new) jump:t .LBB29_45 147 // and result WAR hazards if converted to New Value Jump. 148 149 for (unsigned i = 0; i < II->getNumOperands(); ++i) { 150 if (II->getOperand(i).isReg() && 151 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { 152 MachineBasicBlock::iterator localII = II; 153 ++localII; 154 unsigned Reg = II->getOperand(i).getReg(); 155 for (MachineBasicBlock::iterator localBegin = localII; 156 localBegin != end; ++localBegin) { 157 if (localBegin == skip ) continue; 158 // Check for Subregisters too. 159 if (localBegin->modifiesRegister(Reg, TRI) || 160 localBegin->readsRegister(Reg, TRI)) 161 return false; 162 } 163 } 164 } 165 return true; 166 } 167 168 // These are the common checks that need to performed 169 // to determine if 170 // 1. compare instruction can be moved before jump. 171 // 2. feeder to the compare instruction can be moved before jump. 172 static bool commonChecksToProhibitNewValueJump(bool afterRA, 173 MachineBasicBlock::iterator MII) { 174 175 // If store in path, bail out. 176 if (MII->getDesc().mayStore()) 177 return false; 178 179 // if call in path, bail out. 180 if (MII->isCall()) 181 return false; 182 183 // if NVJ is running prior to RA, do the following checks. 184 if (!afterRA) { 185 // The following Target Opcode instructions are spurious 186 // to new value jump. If they are in the path, bail out. 187 // KILL sets kill flag on the opcode. It also sets up a 188 // single register, out of pair. 189 // %D0<def> = S2_lsr_r_p %D0<kill>, %R2<kill> 190 // %R0<def> = KILL %R0, %D0<imp-use,kill> 191 // %P0<def> = C2_cmpeqi %R0<kill>, 0 192 // PHI can be anything after RA. 193 // COPY can remateriaze things in between feeder, compare and nvj. 194 if (MII->getOpcode() == TargetOpcode::KILL || 195 MII->getOpcode() == TargetOpcode::PHI || 196 MII->getOpcode() == TargetOpcode::COPY) 197 return false; 198 199 // The following pseudo Hexagon instructions sets "use" and "def" 200 // of registers by individual passes in the backend. At this time, 201 // we don't know the scope of usage and definitions of these 202 // instructions. 203 if (MII->getOpcode() == Hexagon::LDriw_pred || 204 MII->getOpcode() == Hexagon::STriw_pred) 205 return false; 206 } 207 208 return true; 209 } 210 211 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, 212 const TargetRegisterInfo *TRI, 213 MachineBasicBlock::iterator II, 214 unsigned pReg, 215 bool secondReg, 216 bool optLocation, 217 MachineBasicBlock::iterator end, 218 MachineFunction &MF) { 219 220 MachineInstr &MI = *II; 221 222 // If the second operand of the compare is an imm, make sure it's in the 223 // range specified by the arch. 224 if (!secondReg) { 225 int64_t v = MI.getOperand(2).getImm(); 226 bool Valid = false; 227 228 switch (MI.getOpcode()) { 229 case Hexagon::C2_cmpeqi: 230 case Hexagon::C2_cmpgti: 231 Valid = (isUInt<5>(v) || v == -1); 232 break; 233 case Hexagon::C2_cmpgtui: 234 Valid = isUInt<5>(v); 235 break; 236 case Hexagon::S2_tstbit_i: 237 case Hexagon::S4_ntstbit_i: 238 Valid = (v == 0); 239 break; 240 } 241 242 if (!Valid) 243 return false; 244 } 245 246 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning. 247 cmpReg1 = MI.getOperand(1).getReg(); 248 249 if (secondReg) { 250 cmpOp2 = MI.getOperand(2).getReg(); 251 252 // If the same register appears as both operands, we cannot generate a new 253 // value compare. Only one operand may use the .new suffix. 254 if (cmpReg1 == cmpOp2) 255 return false; 256 257 // Make sure that that second register is not from COPY 258 // At machine code level, we don't need this, but if we decide 259 // to move new value jump prior to RA, we would be needing this. 260 MachineRegisterInfo &MRI = MF.getRegInfo(); 261 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) { 262 MachineInstr *def = MRI.getVRegDef(cmpOp2); 263 if (def->getOpcode() == TargetOpcode::COPY) 264 return false; 265 } 266 } 267 268 // Walk the instructions after the compare (predicate def) to the jump, 269 // and satisfy the following conditions. 270 ++II ; 271 for (MachineBasicBlock::iterator localII = II; localII != end; 272 ++localII) { 273 if (localII->isDebugValue()) 274 continue; 275 276 // Check 1. 277 // If "common" checks fail, bail out. 278 if (!commonChecksToProhibitNewValueJump(optLocation, localII)) 279 return false; 280 281 // Check 2. 282 // If there is a def or use of predicate (result of compare), bail out. 283 if (localII->modifiesRegister(pReg, TRI) || 284 localII->readsRegister(pReg, TRI)) 285 return false; 286 287 // Check 3. 288 // If there is a def of any of the use of the compare (operands of compare), 289 // bail out. 290 // Eg. 291 // p0 = cmp.eq(r2, r0) 292 // r2 = r4 293 // if (p0.new) jump:t .LBB28_3 294 if (localII->modifiesRegister(cmpReg1, TRI) || 295 (secondReg && localII->modifiesRegister(cmpOp2, TRI))) 296 return false; 297 } 298 return true; 299 } 300 301 302 // Given a compare operator, return a matching New Value Jump compare operator. 303 // Make sure that MI here is included in isNewValueJumpCandidate. 304 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, 305 bool secondRegNewified, 306 MachineBasicBlock *jmpTarget, 307 const MachineBranchProbabilityInfo 308 *MBPI) { 309 bool taken = false; 310 MachineBasicBlock *Src = MI->getParent(); 311 const BranchProbability Prediction = 312 MBPI->getEdgeProbability(Src, jmpTarget); 313 314 if (Prediction >= BranchProbability(1,2)) 315 taken = true; 316 317 switch (MI->getOpcode()) { 318 case Hexagon::C2_cmpeq: 319 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t 320 : Hexagon::J4_cmpeq_t_jumpnv_nt; 321 322 case Hexagon::C2_cmpeqi: { 323 if (reg >= 0) 324 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t 325 : Hexagon::J4_cmpeqi_t_jumpnv_nt; 326 else 327 return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t 328 : Hexagon::J4_cmpeqn1_t_jumpnv_nt; 329 } 330 331 case Hexagon::C2_cmpgt: { 332 if (secondRegNewified) 333 return taken ? Hexagon::J4_cmplt_t_jumpnv_t 334 : Hexagon::J4_cmplt_t_jumpnv_nt; 335 else 336 return taken ? Hexagon::J4_cmpgt_t_jumpnv_t 337 : Hexagon::J4_cmpgt_t_jumpnv_nt; 338 } 339 340 case Hexagon::C2_cmpgti: { 341 if (reg >= 0) 342 return taken ? Hexagon::J4_cmpgti_t_jumpnv_t 343 : Hexagon::J4_cmpgti_t_jumpnv_nt; 344 else 345 return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t 346 : Hexagon::J4_cmpgtn1_t_jumpnv_nt; 347 } 348 349 case Hexagon::C2_cmpgtu: { 350 if (secondRegNewified) 351 return taken ? Hexagon::J4_cmpltu_t_jumpnv_t 352 : Hexagon::J4_cmpltu_t_jumpnv_nt; 353 else 354 return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t 355 : Hexagon::J4_cmpgtu_t_jumpnv_nt; 356 } 357 358 case Hexagon::C2_cmpgtui: 359 return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t 360 : Hexagon::J4_cmpgtui_t_jumpnv_nt; 361 362 case Hexagon::C4_cmpneq: 363 return taken ? Hexagon::J4_cmpeq_f_jumpnv_t 364 : Hexagon::J4_cmpeq_f_jumpnv_nt; 365 366 case Hexagon::C4_cmplte: 367 if (secondRegNewified) 368 return taken ? Hexagon::J4_cmplt_f_jumpnv_t 369 : Hexagon::J4_cmplt_f_jumpnv_nt; 370 return taken ? Hexagon::J4_cmpgt_f_jumpnv_t 371 : Hexagon::J4_cmpgt_f_jumpnv_nt; 372 373 case Hexagon::C4_cmplteu: 374 if (secondRegNewified) 375 return taken ? Hexagon::J4_cmpltu_f_jumpnv_t 376 : Hexagon::J4_cmpltu_f_jumpnv_nt; 377 return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t 378 : Hexagon::J4_cmpgtu_f_jumpnv_nt; 379 380 default: 381 llvm_unreachable("Could not find matching New Value Jump instruction."); 382 } 383 // return *some value* to avoid compiler warning 384 return 0; 385 } 386 387 bool HexagonNewValueJump::isNewValueJumpCandidate( 388 const MachineInstr &MI) const { 389 switch (MI.getOpcode()) { 390 case Hexagon::C2_cmpeq: 391 case Hexagon::C2_cmpeqi: 392 case Hexagon::C2_cmpgt: 393 case Hexagon::C2_cmpgti: 394 case Hexagon::C2_cmpgtu: 395 case Hexagon::C2_cmpgtui: 396 case Hexagon::C4_cmpneq: 397 case Hexagon::C4_cmplte: 398 case Hexagon::C4_cmplteu: 399 return true; 400 401 default: 402 return false; 403 } 404 } 405 406 407 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { 408 409 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" 410 << "********** Function: " 411 << MF.getName() << "\n"); 412 413 if (skipFunction(*MF.getFunction())) 414 return false; 415 416 // If we move NewValueJump before register allocation we'll need live variable 417 // analysis here too. 418 419 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); 420 QRI = static_cast<const HexagonRegisterInfo *>( 421 MF.getSubtarget().getRegisterInfo()); 422 MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); 423 424 if (DisableNewValueJumps) { 425 return false; 426 } 427 428 int nvjCount = DbgNVJCount; 429 int nvjGenerated = 0; 430 431 // Loop through all the bb's of the function 432 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); 433 MBBb != MBBe; ++MBBb) { 434 MachineBasicBlock *MBB = &*MBBb; 435 436 DEBUG(dbgs() << "** dumping bb ** " 437 << MBB->getNumber() << "\n"); 438 DEBUG(MBB->dump()); 439 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n"); 440 bool foundJump = false; 441 bool foundCompare = false; 442 bool invertPredicate = false; 443 unsigned predReg = 0; // predicate reg of the jump. 444 unsigned cmpReg1 = 0; 445 int cmpOp2 = 0; 446 bool MO1IsKill = false; 447 bool MO2IsKill = false; 448 MachineBasicBlock::iterator jmpPos; 449 MachineBasicBlock::iterator cmpPos; 450 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr; 451 MachineBasicBlock *jmpTarget = nullptr; 452 bool afterRA = false; 453 bool isSecondOpReg = false; 454 bool isSecondOpNewified = false; 455 // Traverse the basic block - bottom up 456 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin(); 457 MII != E;) { 458 MachineInstr &MI = *--MII; 459 if (MI.isDebugValue()) { 460 continue; 461 } 462 463 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated)) 464 break; 465 466 DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n"); 467 468 if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt || 469 MI.getOpcode() == Hexagon::J2_jumptpt || 470 MI.getOpcode() == Hexagon::J2_jumpf || 471 MI.getOpcode() == Hexagon::J2_jumpfpt || 472 MI.getOpcode() == Hexagon::J2_jumptnewpt || 473 MI.getOpcode() == Hexagon::J2_jumptnew || 474 MI.getOpcode() == Hexagon::J2_jumpfnewpt || 475 MI.getOpcode() == Hexagon::J2_jumpfnew)) { 476 // This is where you would insert your compare and 477 // instr that feeds compare 478 jmpPos = MII; 479 jmpInstr = &MI; 480 predReg = MI.getOperand(0).getReg(); 481 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg); 482 483 // If ifconverter had not messed up with the kill flags of the 484 // operands, the following check on the kill flag would suffice. 485 // if(!jmpInstr->getOperand(0).isKill()) break; 486 487 // This predicate register is live out out of BB 488 // this would only work if we can actually use Live 489 // variable analysis on phy regs - but LLVM does not 490 // provide LV analysis on phys regs. 491 //if(LVs.isLiveOut(predReg, *MBB)) break; 492 493 // Get all the successors of this block - which will always 494 // be 2. Check if the predicate register is live-in in those 495 // successor. If yes, we can not delete the predicate - 496 // I am doing this only because LLVM does not provide LiveOut 497 // at the BB level. 498 bool predLive = false; 499 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(), 500 SIE = MBB->succ_end(); SI != SIE; ++SI) { 501 MachineBasicBlock* succMBB = *SI; 502 if (succMBB->isLiveIn(predReg)) { 503 predLive = true; 504 } 505 } 506 if (predLive) 507 break; 508 509 if (!MI.getOperand(1).isMBB()) 510 continue; 511 jmpTarget = MI.getOperand(1).getMBB(); 512 foundJump = true; 513 if (MI.getOpcode() == Hexagon::J2_jumpf || 514 MI.getOpcode() == Hexagon::J2_jumpfnewpt || 515 MI.getOpcode() == Hexagon::J2_jumpfnew) { 516 invertPredicate = true; 517 } 518 continue; 519 } 520 521 // No new value jump if there is a barrier. A barrier has to be in its 522 // own packet. A barrier has zero operands. We conservatively bail out 523 // here if we see any instruction with zero operands. 524 if (foundJump && MI.getNumOperands() == 0) 525 break; 526 527 if (foundJump && !foundCompare && MI.getOperand(0).isReg() && 528 MI.getOperand(0).getReg() == predReg) { 529 530 // Not all compares can be new value compare. Arch Spec: 7.6.1.1 531 if (isNewValueJumpCandidate(MI)) { 532 533 assert( 534 (MI.getDesc().isCompare()) && 535 "Only compare instruction can be collapsed into New Value Jump"); 536 isSecondOpReg = MI.getOperand(2).isReg(); 537 538 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg, 539 afterRA, jmpPos, MF)) 540 break; 541 542 cmpInstr = &MI; 543 cmpPos = MII; 544 foundCompare = true; 545 546 // We need cmpReg1 and cmpOp2(imm or reg) while building 547 // new value jump instruction. 548 cmpReg1 = MI.getOperand(1).getReg(); 549 if (MI.getOperand(1).isKill()) 550 MO1IsKill = true; 551 552 if (isSecondOpReg) { 553 cmpOp2 = MI.getOperand(2).getReg(); 554 if (MI.getOperand(2).isKill()) 555 MO2IsKill = true; 556 } else 557 cmpOp2 = MI.getOperand(2).getImm(); 558 continue; 559 } 560 } 561 562 if (foundCompare && foundJump) { 563 564 // If "common" checks fail, bail out on this BB. 565 if (!commonChecksToProhibitNewValueJump(afterRA, MII)) 566 break; 567 568 bool foundFeeder = false; 569 MachineBasicBlock::iterator feederPos = MII; 570 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && 571 (MI.getOperand(0).getReg() == cmpReg1 || 572 (isSecondOpReg && 573 MI.getOperand(0).getReg() == (unsigned)cmpOp2))) { 574 575 unsigned feederReg = MI.getOperand(0).getReg(); 576 577 // First try to see if we can get the feeder from the first operand 578 // of the compare. If we can not, and if secondOpReg is true 579 // (second operand of the compare is also register), try that one. 580 // TODO: Try to come up with some heuristic to figure out which 581 // feeder would benefit. 582 583 if (feederReg == cmpReg1) { 584 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) { 585 if (!isSecondOpReg) 586 break; 587 else 588 continue; 589 } else 590 foundFeeder = true; 591 } 592 593 if (!foundFeeder && 594 isSecondOpReg && 595 feederReg == (unsigned) cmpOp2) 596 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) 597 break; 598 599 if (isSecondOpReg) { 600 // In case of CMPLT, or CMPLTU, or EQ with the second register 601 // to newify, swap the operands. 602 unsigned COp = cmpInstr->getOpcode(); 603 if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) && 604 (feederReg == (unsigned) cmpOp2)) { 605 unsigned tmp = cmpReg1; 606 bool tmpIsKill = MO1IsKill; 607 cmpReg1 = cmpOp2; 608 MO1IsKill = MO2IsKill; 609 cmpOp2 = tmp; 610 MO2IsKill = tmpIsKill; 611 } 612 613 // Now we have swapped the operands, all we need to check is, 614 // if the second operand (after swap) is the feeder. 615 // And if it is, make a note. 616 if (feederReg == (unsigned)cmpOp2) 617 isSecondOpNewified = true; 618 } 619 620 // Now that we are moving feeder close the jump, 621 // make sure we are respecting the kill values of 622 // the operands of the feeder. 623 624 bool updatedIsKill = false; 625 for (unsigned i = 0; i < MI.getNumOperands(); i++) { 626 MachineOperand &MO = MI.getOperand(i); 627 if (MO.isReg() && MO.isUse()) { 628 unsigned feederReg = MO.getReg(); 629 for (MachineBasicBlock::iterator localII = feederPos, 630 end = jmpPos; localII != end; localII++) { 631 MachineInstr &localMI = *localII; 632 for (unsigned j = 0; j < localMI.getNumOperands(); j++) { 633 MachineOperand &localMO = localMI.getOperand(j); 634 if (localMO.isReg() && localMO.isUse() && 635 localMO.isKill() && feederReg == localMO.getReg()) { 636 // We found that there is kill of a use register 637 // Set up a kill flag on the register 638 localMO.setIsKill(false); 639 MO.setIsKill(); 640 updatedIsKill = true; 641 break; 642 } 643 } 644 if (updatedIsKill) break; 645 } 646 } 647 if (updatedIsKill) break; 648 } 649 650 MBB->splice(jmpPos, MI.getParent(), MI); 651 MBB->splice(jmpPos, MI.getParent(), cmpInstr); 652 DebugLoc dl = MI.getDebugLoc(); 653 MachineInstr *NewMI; 654 655 assert((isNewValueJumpCandidate(*cmpInstr)) && 656 "This compare is not a New Value Jump candidate."); 657 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, 658 isSecondOpNewified, 659 jmpTarget, MBPI); 660 if (invertPredicate) 661 opc = QII->getInvertedPredicatedOpcode(opc); 662 663 if (isSecondOpReg) 664 NewMI = BuildMI(*MBB, jmpPos, dl, 665 QII->get(opc)) 666 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 667 .addReg(cmpOp2, getKillRegState(MO2IsKill)) 668 .addMBB(jmpTarget); 669 670 else 671 NewMI = BuildMI(*MBB, jmpPos, dl, 672 QII->get(opc)) 673 .addReg(cmpReg1, getKillRegState(MO1IsKill)) 674 .addImm(cmpOp2) 675 .addMBB(jmpTarget); 676 677 assert(NewMI && "New Value Jump Instruction Not created!"); 678 (void)NewMI; 679 if (cmpInstr->getOperand(0).isReg() && 680 cmpInstr->getOperand(0).isKill()) 681 cmpInstr->getOperand(0).setIsKill(false); 682 if (cmpInstr->getOperand(1).isReg() && 683 cmpInstr->getOperand(1).isKill()) 684 cmpInstr->getOperand(1).setIsKill(false); 685 cmpInstr->eraseFromParent(); 686 jmpInstr->eraseFromParent(); 687 ++nvjGenerated; 688 ++NumNVJGenerated; 689 break; 690 } 691 } 692 } 693 } 694 695 return true; 696 697 } 698 699 FunctionPass *llvm::createHexagonNewValueJump() { 700 return new HexagonNewValueJump(); 701 } 702