1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCInstrInfo.h" 16 #include "MCTargetDesc/HexagonMCTargetDesc.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/Endian.h" 28 #include "llvm/Support/MathExtras.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include <cassert> 32 #include <cstddef> 33 #include <cstdint> 34 #include <memory> 35 36 using namespace llvm; 37 using namespace Hexagon; 38 39 using DecodeStatus = MCDisassembler::DecodeStatus; 40 41 namespace { 42 43 /// \brief Hexagon disassembler for all Hexagon platforms. 44 class HexagonDisassembler : public MCDisassembler { 45 public: 46 std::unique_ptr<MCInstrInfo const> const MCII; 47 std::unique_ptr<MCInst *> CurrentBundle; 48 49 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 50 MCInstrInfo const *MCII) 51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} 52 53 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 54 ArrayRef<uint8_t> Bytes, uint64_t Address, 55 raw_ostream &VStream, raw_ostream &CStream, 56 bool &Complete) const; 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &VStream, 60 raw_ostream &CStream) const override; 61 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; 62 }; 63 64 } // end anonymous namespace 65 66 static uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, 67 int64_t Value) { 68 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 69 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 70 if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 71 return Value; 72 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 73 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 74 int64_t Bits; 75 bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); 76 assert(Success); (void)Success; 77 uint32_t Upper26 = static_cast<uint32_t>(Bits); 78 uint32_t Operand = Upper26 | Lower6; 79 return Operand; 80 } 81 82 static HexagonDisassembler const &disassembler(void const *Decoder) { 83 return *static_cast<HexagonDisassembler const *>(Decoder); 84 } 85 86 template <size_t T> 87 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 88 HexagonDisassembler const &Disassembler = disassembler(Decoder); 89 int64_t FullValue = 90 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, 91 SignExtend64<T>(tmp)); 92 int64_t Extended = SignExtend64<32>(FullValue); 93 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 94 } 95 96 // Forward declare these because the auto-generated code will reference them. 97 // Definitions are further down. 98 99 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus 116 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 140 uint64_t /*Address*/, const void *Decoder); 141 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 142 const void *Decoder); 143 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 144 const void *Decoder); 145 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 146 const void *Decoder); 147 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 152 const void *Decoder); 153 static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 156 const void *Decoder); 157 158 #include "HexagonDepDecoders.h" 159 #include "HexagonGenDisassemblerTables.inc" 160 161 static MCDisassembler *createHexagonDisassembler(const Target &T, 162 const MCSubtargetInfo &STI, 163 MCContext &Ctx) { 164 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 165 } 166 167 extern "C" void LLVMInitializeHexagonDisassembler() { 168 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 169 createHexagonDisassembler); 170 } 171 172 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 173 ArrayRef<uint8_t> Bytes, 174 uint64_t Address, 175 raw_ostream &os, 176 raw_ostream &cs) const { 177 DecodeStatus Result = DecodeStatus::Success; 178 bool Complete = false; 179 Size = 0; 180 181 *CurrentBundle = &MI; 182 MI = HexagonMCInstrInfo::createBundle(); 183 while (Result == Success && !Complete) { 184 if (Bytes.size() < HEXAGON_INSTR_SIZE) 185 return MCDisassembler::Fail; 186 MCInst *Inst = new (getContext()) MCInst; 187 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 188 MI.addOperand(MCOperand::createInst(Inst)); 189 Size += HEXAGON_INSTR_SIZE; 190 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 191 } 192 if (Result == MCDisassembler::Fail) 193 return Result; 194 if (Size > HEXAGON_MAX_PACKET_SIZE) 195 return MCDisassembler::Fail; 196 HexagonMCChecker Checker(getContext(), *MCII, STI, MI, 197 *getContext().getRegisterInfo(), false); 198 if (!Checker.check()) 199 return MCDisassembler::Fail; 200 return MCDisassembler::Success; 201 } 202 203 static void adjustDuplex(MCInst &MI, MCContext &Context) { 204 switch (MI.getOpcode()) { 205 case Hexagon::SA1_setin1: 206 MI.insert(MI.begin() + 1, 207 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 208 break; 209 case Hexagon::SA1_dec: 210 MI.insert(MI.begin() + 2, 211 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 212 break; 213 default: 214 break; 215 } 216 } 217 218 DecodeStatus HexagonDisassembler::getSingleInstruction( 219 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 220 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 221 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 222 223 uint32_t Instruction = support::endian::read32le(Bytes.data()); 224 225 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 226 if ((Instruction & HexagonII::INST_PARSE_MASK) == 227 HexagonII::INST_PARSE_LOOP_END) { 228 if (BundleSize == 0) 229 HexagonMCInstrInfo::setInnerLoop(MCB); 230 else if (BundleSize == 1) 231 HexagonMCInstrInfo::setOuterLoop(MCB); 232 else 233 return DecodeStatus::Fail; 234 } 235 236 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 237 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 238 239 DecodeStatus Result = DecodeStatus::Fail; 240 if ((Instruction & HexagonII::INST_PARSE_MASK) == 241 HexagonII::INST_PARSE_DUPLEX) { 242 unsigned duplexIClass; 243 uint8_t const *DecodeLow, *DecodeHigh; 244 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 245 switch (duplexIClass) { 246 default: 247 return MCDisassembler::Fail; 248 case 0: 249 DecodeLow = DecoderTableSUBINSN_L132; 250 DecodeHigh = DecoderTableSUBINSN_L132; 251 break; 252 case 1: 253 DecodeLow = DecoderTableSUBINSN_L232; 254 DecodeHigh = DecoderTableSUBINSN_L132; 255 break; 256 case 2: 257 DecodeLow = DecoderTableSUBINSN_L232; 258 DecodeHigh = DecoderTableSUBINSN_L232; 259 break; 260 case 3: 261 DecodeLow = DecoderTableSUBINSN_A32; 262 DecodeHigh = DecoderTableSUBINSN_A32; 263 break; 264 case 4: 265 DecodeLow = DecoderTableSUBINSN_L132; 266 DecodeHigh = DecoderTableSUBINSN_A32; 267 break; 268 case 5: 269 DecodeLow = DecoderTableSUBINSN_L232; 270 DecodeHigh = DecoderTableSUBINSN_A32; 271 break; 272 case 6: 273 DecodeLow = DecoderTableSUBINSN_S132; 274 DecodeHigh = DecoderTableSUBINSN_A32; 275 break; 276 case 7: 277 DecodeLow = DecoderTableSUBINSN_S232; 278 DecodeHigh = DecoderTableSUBINSN_A32; 279 break; 280 case 8: 281 DecodeLow = DecoderTableSUBINSN_S132; 282 DecodeHigh = DecoderTableSUBINSN_L132; 283 break; 284 case 9: 285 DecodeLow = DecoderTableSUBINSN_S132; 286 DecodeHigh = DecoderTableSUBINSN_L232; 287 break; 288 case 10: 289 DecodeLow = DecoderTableSUBINSN_S132; 290 DecodeHigh = DecoderTableSUBINSN_S132; 291 break; 292 case 11: 293 DecodeLow = DecoderTableSUBINSN_S232; 294 DecodeHigh = DecoderTableSUBINSN_S132; 295 break; 296 case 12: 297 DecodeLow = DecoderTableSUBINSN_S232; 298 DecodeHigh = DecoderTableSUBINSN_L132; 299 break; 300 case 13: 301 DecodeLow = DecoderTableSUBINSN_S232; 302 DecodeHigh = DecoderTableSUBINSN_L232; 303 break; 304 case 14: 305 DecodeLow = DecoderTableSUBINSN_S232; 306 DecodeHigh = DecoderTableSUBINSN_S232; 307 break; 308 } 309 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); 310 MCInst *MILow = new (getContext()) MCInst; 311 MCInst *MIHigh = new (getContext()) MCInst; 312 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, 313 this, STI); 314 if (Result != DecodeStatus::Success) 315 return DecodeStatus::Fail; 316 adjustDuplex(*MILow, getContext()); 317 Result = decodeInstruction( 318 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); 319 if (Result != DecodeStatus::Success) 320 return DecodeStatus::Fail; 321 adjustDuplex(*MIHigh, getContext()); 322 MCOperand OPLow = MCOperand::createInst(MILow); 323 MCOperand OPHigh = MCOperand::createInst(MIHigh); 324 MI.addOperand(OPLow); 325 MI.addOperand(OPHigh); 326 Complete = true; 327 } else { 328 if ((Instruction & HexagonII::INST_PARSE_MASK) == 329 HexagonII::INST_PARSE_PACKET_END) 330 Complete = true; 331 332 if (Extender != nullptr) 333 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, 334 Address, this, STI); 335 336 if (Result != MCDisassembler::Success) 337 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, 338 STI); 339 340 if (Result != MCDisassembler::Success && 341 STI.getFeatureBits()[Hexagon::ExtensionHVX]) 342 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, 343 Address, this, STI); 344 345 } 346 347 switch (MI.getOpcode()) { 348 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 349 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 350 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 351 case Hexagon::J4_cmpeqn1_fp0_jump_t: 352 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 353 case Hexagon::J4_cmpeqn1_fp1_jump_t: 354 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 355 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 356 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 357 case Hexagon::J4_cmpeqn1_tp0_jump_t: 358 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 359 case Hexagon::J4_cmpeqn1_tp1_jump_t: 360 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 361 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 362 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 363 case Hexagon::J4_cmpgtn1_fp0_jump_t: 364 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 365 case Hexagon::J4_cmpgtn1_fp1_jump_t: 366 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 367 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 368 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 369 case Hexagon::J4_cmpgtn1_tp0_jump_t: 370 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 371 case Hexagon::J4_cmpgtn1_tp1_jump_t: 372 MI.insert(MI.begin() + 1, 373 MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 374 break; 375 default: 376 break; 377 } 378 379 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 380 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 381 MCOperand &MCO = MI.getOperand(OpIndex); 382 assert(MCO.isReg() && "New value consumers must be registers"); 383 unsigned Register = 384 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 385 if ((Register & 0x6) == 0) 386 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 387 return MCDisassembler::Fail; 388 unsigned Lookback = (Register & 0x6) >> 1; 389 unsigned Offset = 1; 390 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 391 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 392 auto i = Instructions.end() - 1; 393 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 394 if (i == n) 395 // Couldn't find producer 396 return MCDisassembler::Fail; 397 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) 398 // Skip scalars when calculating distances for vectors 399 ++Lookback; 400 if (HexagonMCInstrInfo::isImmext(*i->getInst())) 401 ++Lookback; 402 if (Offset == Lookback) 403 break; 404 } 405 auto const &Inst = *i->getInst(); 406 bool SubregBit = (Register & 0x1) != 0; 407 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 408 // If subreg bit is set we're selecting the second produced newvalue 409 unsigned Producer = 410 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 411 assert(Producer != Hexagon::NoRegister); 412 MCO.setReg(Producer); 413 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 414 unsigned Producer = 415 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 416 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 417 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 418 else if (SubregBit) 419 // Hexagon PRM 10.11 New-value operands 420 // Nt[0] is reserved and should always be encoded as zero. 421 return MCDisassembler::Fail; 422 assert(Producer != Hexagon::NoRegister); 423 MCO.setReg(Producer); 424 } else 425 return MCDisassembler::Fail; 426 } 427 428 if (Extender != nullptr) { 429 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) 430 ? *MI.getOperand(1).getInst() 431 : MI; 432 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 433 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 434 return MCDisassembler::Fail; 435 } 436 return Result; 437 } 438 439 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 440 ArrayRef<MCPhysReg> Table) { 441 if (RegNo < Table.size()) { 442 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 443 return MCDisassembler::Success; 444 } 445 446 return MCDisassembler::Fail; 447 } 448 449 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 450 uint64_t Address, 451 const void *Decoder) { 452 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 453 } 454 455 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 456 uint64_t Address, 457 const void *Decoder) { 458 static const MCPhysReg IntRegDecoderTable[] = { 459 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 460 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 461 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 462 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 463 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 464 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 465 Hexagon::R30, Hexagon::R31}; 466 467 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 468 } 469 470 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 471 unsigned RegNo, 472 uint64_t Address, 473 const void *Decoder) { 474 static const MCPhysReg GeneralSubRegDecoderTable[] = { 475 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 476 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, 477 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 478 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 479 }; 480 481 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); 482 } 483 484 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 485 uint64_t /*Address*/, 486 const void *Decoder) { 487 static const MCPhysReg HvxVRDecoderTable[] = { 488 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 489 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 490 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 491 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 492 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 493 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 494 Hexagon::V30, Hexagon::V31}; 495 496 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); 497 } 498 499 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 500 uint64_t /*Address*/, 501 const void *Decoder) { 502 static const MCPhysReg DoubleRegDecoderTable[] = { 503 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 504 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 505 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 506 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 507 508 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 509 } 510 511 static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( 512 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { 513 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { 514 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 515 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; 516 517 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); 518 } 519 520 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 521 uint64_t /*Address*/, 522 const void *Decoder) { 523 static const MCPhysReg HvxWRDecoderTable[] = { 524 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 525 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 526 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 527 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 528 529 return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable)); 530 } 531 532 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 533 uint64_t /*Address*/, 534 const void *Decoder) { 535 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 536 Hexagon::P2, Hexagon::P3}; 537 538 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 539 } 540 541 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 542 uint64_t /*Address*/, 543 const void *Decoder) { 544 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 545 Hexagon::Q2, Hexagon::Q3}; 546 547 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); 548 } 549 550 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 551 uint64_t /*Address*/, 552 const void *Decoder) { 553 using namespace Hexagon; 554 555 static const MCPhysReg CtrlRegDecoderTable[] = { 556 /* 0 */ SA0, LC0, SA1, LC1, 557 /* 4 */ P3_0, C5, M0, M1, 558 /* 8 */ USR, PC, UGP, GP, 559 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, 560 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, 561 /* 20 */ 0, 0, 0, 0, 562 /* 24 */ 0, 0, 0, 0, 563 /* 28 */ 0, 0, UTIMERLO, UTIMERHI 564 }; 565 566 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 567 return MCDisassembler::Fail; 568 569 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 570 if (CtrlRegDecoderTable[RegNo] == NoRegister) 571 return MCDisassembler::Fail; 572 573 unsigned Register = CtrlRegDecoderTable[RegNo]; 574 Inst.addOperand(MCOperand::createReg(Register)); 575 return MCDisassembler::Success; 576 } 577 578 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 579 uint64_t /*Address*/, 580 const void *Decoder) { 581 using namespace Hexagon; 582 583 static const MCPhysReg CtrlReg64DecoderTable[] = { 584 /* 0 */ C1_0, 0, C3_2, 0, 585 /* 4 */ C5_4, 0, C7_6, 0, 586 /* 8 */ C9_8, 0, C11_10, 0, 587 /* 12 */ CS, 0, UPCYCLE, 0, 588 /* 16 */ C17_16, 0, PKTCOUNT, 0, 589 /* 20 */ 0, 0, 0, 0, 590 /* 24 */ 0, 0, 0, 0, 591 /* 28 */ 0, 0, UTIMER, 0 592 }; 593 594 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 595 return MCDisassembler::Fail; 596 597 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 598 if (CtrlReg64DecoderTable[RegNo] == NoRegister) 599 return MCDisassembler::Fail; 600 601 unsigned Register = CtrlReg64DecoderTable[RegNo]; 602 Inst.addOperand(MCOperand::createReg(Register)); 603 return MCDisassembler::Success; 604 } 605 606 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 607 uint64_t /*Address*/, 608 const void *Decoder) { 609 unsigned Register = 0; 610 switch (RegNo) { 611 case 0: 612 Register = Hexagon::M0; 613 break; 614 case 1: 615 Register = Hexagon::M1; 616 break; 617 default: 618 return MCDisassembler::Fail; 619 } 620 Inst.addOperand(MCOperand::createReg(Register)); 621 return MCDisassembler::Success; 622 } 623 624 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 625 uint64_t /*Address*/, 626 const void *Decoder) { 627 HexagonDisassembler const &Disassembler = disassembler(Decoder); 628 int64_t FullValue = 629 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, tmp); 630 assert(FullValue >= 0 && "Negative in unsigned decoder"); 631 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 632 return MCDisassembler::Success; 633 } 634 635 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 636 uint64_t /*Address*/, const void *Decoder) { 637 HexagonDisassembler const &Disassembler = disassembler(Decoder); 638 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 639 tmp = SignExtend64(tmp, Bits); 640 signedDecoder<32>(MI, tmp, Decoder); 641 return MCDisassembler::Success; 642 } 643 644 // custom decoder for various jump/call immediates 645 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 646 const void *Decoder) { 647 HexagonDisassembler const &Disassembler = disassembler(Decoder); 648 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 649 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 650 if (Bits == 0) 651 Bits = 15; 652 uint32_t FullValue = 653 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, 654 SignExtend64(tmp, Bits)); 655 int64_t Extended = SignExtend64<32>(FullValue) + Address; 656 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) 657 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 658 return MCDisassembler::Success; 659 } 660