1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCInstrInfo.h" 16 #include "MCTargetDesc/HexagonMCTargetDesc.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/Endian.h" 28 #include "llvm/Support/MathExtras.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include <cassert> 32 #include <cstddef> 33 #include <cstdint> 34 #include <memory> 35 36 using namespace llvm; 37 using namespace Hexagon; 38 39 using DecodeStatus = MCDisassembler::DecodeStatus; 40 41 namespace { 42 43 /// \brief Hexagon disassembler for all Hexagon platforms. 44 class HexagonDisassembler : public MCDisassembler { 45 public: 46 std::unique_ptr<MCInstrInfo const> const MCII; 47 std::unique_ptr<MCInst *> CurrentBundle; 48 mutable MCInst const *CurrentExtender; 49 50 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 51 MCInstrInfo const *MCII) 52 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), 53 CurrentExtender(nullptr) {} 54 55 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 56 ArrayRef<uint8_t> Bytes, uint64_t Address, 57 raw_ostream &VStream, raw_ostream &CStream, 58 bool &Complete) const; 59 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 60 ArrayRef<uint8_t> Bytes, uint64_t Address, 61 raw_ostream &VStream, 62 raw_ostream &CStream) const override; 63 void remapInstruction(MCInst &Instr) const; 64 }; 65 66 static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI, 67 int64_t Value) { 68 MCInstrInfo MCII = *Disassembler.MCII; 69 if (!Disassembler.CurrentExtender || 70 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 71 return Value; 72 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 73 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 74 int64_t Bits; 75 bool Success = 76 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute( 77 Bits); 78 assert(Success); 79 (void)Success; 80 uint64_t Upper26 = static_cast<uint64_t>(Bits); 81 uint64_t Operand = Upper26 | Lower6; 82 return Operand; 83 } 84 static HexagonDisassembler const &disassembler(void const *Decoder) { 85 return *static_cast<HexagonDisassembler const *>(Decoder); 86 } 87 template <size_t T> 88 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 89 HexagonDisassembler const &Disassembler = disassembler(Decoder); 90 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp)); 91 int64_t Extended = SignExtend64<32>(FullValue); 92 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 93 } 94 } 95 96 // Forward declare these because the auto-generated code will reference them. 97 // Definitions are further down. 98 99 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus 116 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 140 uint64_t /*Address*/, const void *Decoder); 141 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 142 const void *Decoder); 143 144 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 145 const void *Decoder) { 146 signedDecoder<4>(MI, tmp, Decoder); 147 return MCDisassembler::Success; 148 } 149 static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 150 const void *Decoder) { 151 signedDecoder<14>(MI, tmp, Decoder); 152 return MCDisassembler::Success; 153 } 154 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 155 const void *Decoder) { 156 signedDecoder<8>(MI, tmp, Decoder); 157 return MCDisassembler::Success; 158 } 159 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 160 const void *Decoder) { 161 signedDecoder<7>(MI, tmp, Decoder); 162 return MCDisassembler::Success; 163 } 164 static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 165 const void *Decoder) { 166 signedDecoder<12>(MI, tmp, Decoder); 167 return MCDisassembler::Success; 168 } 169 static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 170 const void *Decoder) { 171 signedDecoder<3>(MI, tmp, Decoder); 172 return MCDisassembler::Success; 173 } 174 static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 175 const void *Decoder) { 176 signedDecoder<13>(MI, tmp, Decoder); 177 return MCDisassembler::Success; 178 } 179 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 180 const void *Decoder) { 181 signedDecoder<6>(MI, tmp, Decoder); 182 return MCDisassembler::Success; 183 } 184 static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 185 const void *Decoder) { 186 signedDecoder<9>(MI, tmp, Decoder); 187 return MCDisassembler::Success; 188 } 189 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 190 const void *Decoder) { 191 signedDecoder<5>(MI, tmp, Decoder); 192 return MCDisassembler::Success; 193 } 194 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 195 const void *Decoder) { 196 signedDecoder<6>(MI, tmp, Decoder); 197 return MCDisassembler::Success; 198 } 199 #include "HexagonGenDisassemblerTables.inc" 200 201 static MCDisassembler *createHexagonDisassembler(const Target &T, 202 const MCSubtargetInfo &STI, 203 MCContext &Ctx) { 204 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 205 } 206 207 extern "C" void LLVMInitializeHexagonDisassembler() { 208 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 209 createHexagonDisassembler); 210 } 211 212 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 213 ArrayRef<uint8_t> Bytes, 214 uint64_t Address, 215 raw_ostream &os, 216 raw_ostream &cs) const { 217 DecodeStatus Result = DecodeStatus::Success; 218 bool Complete = false; 219 Size = 0; 220 221 *CurrentBundle = &MI; 222 MI.setOpcode(Hexagon::BUNDLE); 223 MI.addOperand(MCOperand::createImm(0)); 224 while (Result == Success && !Complete) { 225 if (Bytes.size() < HEXAGON_INSTR_SIZE) 226 return MCDisassembler::Fail; 227 MCInst *Inst = new (getContext()) MCInst; 228 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 229 MI.addOperand(MCOperand::createInst(Inst)); 230 Size += HEXAGON_INSTR_SIZE; 231 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 232 } 233 if (Result == MCDisassembler::Fail) 234 return Result; 235 if (Size > HEXAGON_MAX_PACKET_SIZE) 236 return MCDisassembler::Fail; 237 HexagonMCChecker Checker(getContext(), *MCII, STI, MI, 238 *getContext().getRegisterInfo(), false); 239 if (!Checker.check()) 240 return MCDisassembler::Fail; 241 remapInstruction(MI); 242 return MCDisassembler::Success; 243 } 244 245 void HexagonDisassembler::remapInstruction(MCInst &Instr) const { 246 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) { 247 auto &MI = const_cast<MCInst &>(*I.getInst()); 248 switch (MI.getOpcode()) { 249 case Hexagon::S2_allocframe: 250 if (MI.getOperand(0).getReg() == Hexagon::R29) { 251 MI.setOpcode(Hexagon::S6_allocframe_to_raw); 252 MI.erase(MI.begin () + 1); 253 MI.erase(MI.begin ()); 254 } 255 break; 256 case Hexagon::L2_deallocframe: 257 if (MI.getOperand(0).getReg() == Hexagon::D15 && 258 MI.getOperand(1).getReg() == Hexagon::R30) { 259 MI.setOpcode(L6_deallocframe_map_to_raw); 260 MI.erase(MI.begin () + 1); 261 MI.erase(MI.begin ()); 262 } 263 break; 264 case Hexagon::L4_return: 265 if (MI.getOperand(0).getReg() == Hexagon::D15 && 266 MI.getOperand(1).getReg() == Hexagon::R30) { 267 MI.setOpcode(L6_return_map_to_raw); 268 MI.erase(MI.begin () + 1); 269 MI.erase(MI.begin ()); 270 } 271 break; 272 case Hexagon::L4_return_t: 273 if (MI.getOperand(0).getReg() == Hexagon::D15 && 274 MI.getOperand(2).getReg() == Hexagon::R30) { 275 MI.setOpcode(L4_return_map_to_raw_t); 276 MI.erase(MI.begin () + 2); 277 MI.erase(MI.begin ()); 278 } 279 break; 280 case Hexagon::L4_return_f: 281 if (MI.getOperand(0).getReg() == Hexagon::D15 && 282 MI.getOperand(2).getReg() == Hexagon::R30) { 283 MI.setOpcode(L4_return_map_to_raw_f); 284 MI.erase(MI.begin () + 2); 285 MI.erase(MI.begin ()); 286 } 287 break; 288 case Hexagon::L4_return_tnew_pt: 289 if (MI.getOperand(0).getReg() == Hexagon::D15 && 290 MI.getOperand(2).getReg() == Hexagon::R30) { 291 MI.setOpcode(L4_return_map_to_raw_tnew_pt); 292 MI.erase(MI.begin () + 2); 293 MI.erase(MI.begin ()); 294 } 295 break; 296 case Hexagon::L4_return_fnew_pt: 297 if (MI.getOperand(0).getReg() == Hexagon::D15 && 298 MI.getOperand(2).getReg() == Hexagon::R30) { 299 MI.setOpcode(L4_return_map_to_raw_fnew_pt); 300 MI.erase(MI.begin () + 2); 301 MI.erase(MI.begin ()); 302 } 303 break; 304 case Hexagon::L4_return_tnew_pnt: 305 if (MI.getOperand(0).getReg() == Hexagon::D15 && 306 MI.getOperand(2).getReg() == Hexagon::R30) { 307 MI.setOpcode(L4_return_map_to_raw_tnew_pnt); 308 MI.erase(MI.begin () + 2); 309 MI.erase(MI.begin ()); 310 } 311 break; 312 case Hexagon::L4_return_fnew_pnt: 313 if (MI.getOperand(0).getReg() == Hexagon::D15 && 314 MI.getOperand(2).getReg() == Hexagon::R30) { 315 MI.setOpcode(L4_return_map_to_raw_fnew_pnt); 316 MI.erase(MI.begin () + 2); 317 MI.erase(MI.begin ()); 318 } 319 break; 320 } 321 } 322 } 323 324 static void adjustDuplex(MCInst &MI, MCContext &Context) { 325 switch (MI.getOpcode()) { 326 case Hexagon::SA1_setin1: 327 MI.insert(MI.begin() + 1, 328 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 329 break; 330 case Hexagon::SA1_dec: 331 MI.insert(MI.begin() + 2, 332 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 333 break; 334 default: 335 break; 336 } 337 } 338 339 DecodeStatus HexagonDisassembler::getSingleInstruction( 340 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 341 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 342 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 343 344 uint32_t Instruction = support::endian::read32le(Bytes.data()); 345 346 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 347 if ((Instruction & HexagonII::INST_PARSE_MASK) == 348 HexagonII::INST_PARSE_LOOP_END) { 349 if (BundleSize == 0) 350 HexagonMCInstrInfo::setInnerLoop(MCB); 351 else if (BundleSize == 1) 352 HexagonMCInstrInfo::setOuterLoop(MCB); 353 else 354 return DecodeStatus::Fail; 355 } 356 357 CurrentExtender = HexagonMCInstrInfo::extenderForIndex( 358 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 359 360 DecodeStatus Result = DecodeStatus::Fail; 361 if ((Instruction & HexagonII::INST_PARSE_MASK) == 362 HexagonII::INST_PARSE_DUPLEX) { 363 unsigned duplexIClass; 364 uint8_t const *DecodeLow, *DecodeHigh; 365 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 366 switch (duplexIClass) { 367 default: 368 return MCDisassembler::Fail; 369 case 0: 370 DecodeLow = DecoderTableSUBINSN_L132; 371 DecodeHigh = DecoderTableSUBINSN_L132; 372 break; 373 case 1: 374 DecodeLow = DecoderTableSUBINSN_L232; 375 DecodeHigh = DecoderTableSUBINSN_L132; 376 break; 377 case 2: 378 DecodeLow = DecoderTableSUBINSN_L232; 379 DecodeHigh = DecoderTableSUBINSN_L232; 380 break; 381 case 3: 382 DecodeLow = DecoderTableSUBINSN_A32; 383 DecodeHigh = DecoderTableSUBINSN_A32; 384 break; 385 case 4: 386 DecodeLow = DecoderTableSUBINSN_L132; 387 DecodeHigh = DecoderTableSUBINSN_A32; 388 break; 389 case 5: 390 DecodeLow = DecoderTableSUBINSN_L232; 391 DecodeHigh = DecoderTableSUBINSN_A32; 392 break; 393 case 6: 394 DecodeLow = DecoderTableSUBINSN_S132; 395 DecodeHigh = DecoderTableSUBINSN_A32; 396 break; 397 case 7: 398 DecodeLow = DecoderTableSUBINSN_S232; 399 DecodeHigh = DecoderTableSUBINSN_A32; 400 break; 401 case 8: 402 DecodeLow = DecoderTableSUBINSN_S132; 403 DecodeHigh = DecoderTableSUBINSN_L132; 404 break; 405 case 9: 406 DecodeLow = DecoderTableSUBINSN_S132; 407 DecodeHigh = DecoderTableSUBINSN_L232; 408 break; 409 case 10: 410 DecodeLow = DecoderTableSUBINSN_S132; 411 DecodeHigh = DecoderTableSUBINSN_S132; 412 break; 413 case 11: 414 DecodeLow = DecoderTableSUBINSN_S232; 415 DecodeHigh = DecoderTableSUBINSN_S132; 416 break; 417 case 12: 418 DecodeLow = DecoderTableSUBINSN_S232; 419 DecodeHigh = DecoderTableSUBINSN_L132; 420 break; 421 case 13: 422 DecodeLow = DecoderTableSUBINSN_S232; 423 DecodeHigh = DecoderTableSUBINSN_L232; 424 break; 425 case 14: 426 DecodeLow = DecoderTableSUBINSN_S232; 427 DecodeHigh = DecoderTableSUBINSN_S232; 428 break; 429 } 430 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); 431 MCInst *MILow = new (getContext()) MCInst; 432 MCInst *MIHigh = new (getContext()) MCInst; 433 auto TmpExtender = CurrentExtender; 434 CurrentExtender = 435 nullptr; // constant extenders in duplex must always be in slot 1 436 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, 437 this, STI); 438 CurrentExtender = TmpExtender; 439 if (Result != DecodeStatus::Success) 440 return DecodeStatus::Fail; 441 adjustDuplex(*MILow, getContext()); 442 Result = decodeInstruction( 443 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); 444 if (Result != DecodeStatus::Success) 445 return DecodeStatus::Fail; 446 adjustDuplex(*MIHigh, getContext()); 447 MCOperand OPLow = MCOperand::createInst(MILow); 448 MCOperand OPHigh = MCOperand::createInst(MIHigh); 449 MI.addOperand(OPLow); 450 MI.addOperand(OPHigh); 451 Complete = true; 452 } else { 453 if ((Instruction & HexagonII::INST_PARSE_MASK) == 454 HexagonII::INST_PARSE_PACKET_END) 455 Complete = true; 456 457 if (CurrentExtender != nullptr) 458 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, 459 Address, this, STI); 460 461 if (Result != MCDisassembler::Success) 462 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, 463 STI); 464 465 if (Result != MCDisassembler::Success && 466 STI.getFeatureBits()[Hexagon::ExtensionHVX]) 467 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, 468 Address, this, STI); 469 470 } 471 472 switch (MI.getOpcode()) { 473 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 474 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 475 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 476 case Hexagon::J4_cmpeqn1_fp0_jump_t: 477 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 478 case Hexagon::J4_cmpeqn1_fp1_jump_t: 479 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 480 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 481 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 482 case Hexagon::J4_cmpeqn1_tp0_jump_t: 483 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 484 case Hexagon::J4_cmpeqn1_tp1_jump_t: 485 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 486 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 487 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 488 case Hexagon::J4_cmpgtn1_fp0_jump_t: 489 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 490 case Hexagon::J4_cmpgtn1_fp1_jump_t: 491 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 492 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 493 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 494 case Hexagon::J4_cmpgtn1_tp0_jump_t: 495 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 496 case Hexagon::J4_cmpgtn1_tp1_jump_t: 497 MI.insert(MI.begin() + 1, 498 MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 499 break; 500 default: 501 break; 502 } 503 504 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 505 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 506 MCOperand &MCO = MI.getOperand(OpIndex); 507 assert(MCO.isReg() && "New value consumers must be registers"); 508 unsigned Register = 509 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 510 if ((Register & 0x6) == 0) 511 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 512 return MCDisassembler::Fail; 513 unsigned Lookback = (Register & 0x6) >> 1; 514 unsigned Offset = 1; 515 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 516 bool PrevVector = false; 517 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 518 auto i = Instructions.end() - 1; 519 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 520 if (i == n) 521 // Couldn't find producer 522 return MCDisassembler::Fail; 523 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst()); 524 if (Vector && !CurrentVector) 525 // Skip scalars when calculating distances for vectors 526 ++Lookback; 527 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector)) 528 ++Lookback; 529 PrevVector = CurrentVector; 530 if (Offset == Lookback) 531 break; 532 } 533 auto const &Inst = *i->getInst(); 534 bool SubregBit = (Register & 0x1) != 0; 535 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 536 // If subreg bit is set we're selecting the second produced newvalue 537 unsigned Producer = SubregBit ? 538 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() : 539 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 540 assert(Producer != Hexagon::NoRegister); 541 MCO.setReg(Producer); 542 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 543 unsigned Producer = 544 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 545 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 546 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 547 else if (SubregBit) 548 // Hexagon PRM 10.11 New-value operands 549 // Nt[0] is reserved and should always be encoded as zero. 550 return MCDisassembler::Fail; 551 assert(Producer != Hexagon::NoRegister); 552 MCO.setReg(Producer); 553 } else 554 return MCDisassembler::Fail; 555 } 556 557 if (CurrentExtender != nullptr) { 558 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) 559 ? *MI.getOperand(1).getInst() 560 : MI; 561 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 562 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 563 return MCDisassembler::Fail; 564 } 565 return Result; 566 } 567 568 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 569 ArrayRef<MCPhysReg> Table) { 570 if (RegNo < Table.size()) { 571 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 572 return MCDisassembler::Success; 573 } 574 575 return MCDisassembler::Fail; 576 } 577 578 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 579 uint64_t Address, 580 const void *Decoder) { 581 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 582 } 583 584 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 585 uint64_t Address, 586 const void *Decoder) { 587 static const MCPhysReg IntRegDecoderTable[] = { 588 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 589 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 590 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 591 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 592 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 593 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 594 Hexagon::R30, Hexagon::R31}; 595 596 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 597 } 598 599 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 600 unsigned RegNo, 601 uint64_t Address, 602 const void *Decoder) { 603 static const MCPhysReg GeneralSubRegDecoderTable[] = { 604 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 605 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, 606 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 607 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 608 }; 609 610 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); 611 } 612 613 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 614 uint64_t /*Address*/, 615 const void *Decoder) { 616 static const MCPhysReg HvxVRDecoderTable[] = { 617 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 618 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 619 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 620 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 621 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 622 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 623 Hexagon::V30, Hexagon::V31}; 624 625 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); 626 } 627 628 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 629 uint64_t /*Address*/, 630 const void *Decoder) { 631 static const MCPhysReg DoubleRegDecoderTable[] = { 632 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 633 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 634 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 635 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 636 637 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 638 } 639 640 static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( 641 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { 642 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { 643 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 644 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; 645 646 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); 647 } 648 649 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 650 uint64_t /*Address*/, 651 const void *Decoder) { 652 static const MCPhysReg HvxWRDecoderTable[] = { 653 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 654 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 655 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 656 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 657 658 return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable)); 659 } 660 661 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 662 uint64_t /*Address*/, 663 const void *Decoder) { 664 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 665 Hexagon::P2, Hexagon::P3}; 666 667 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 668 } 669 670 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 671 uint64_t /*Address*/, 672 const void *Decoder) { 673 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 674 Hexagon::Q2, Hexagon::Q3}; 675 676 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); 677 } 678 679 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 680 uint64_t /*Address*/, 681 const void *Decoder) { 682 using namespace Hexagon; 683 684 static const MCPhysReg CtrlRegDecoderTable[] = { 685 /* 0 */ SA0, LC0, SA1, LC1, 686 /* 4 */ P3_0, C5, M0, M1, 687 /* 8 */ USR, PC, UGP, GP, 688 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, 689 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, 690 /* 20 */ 0, 0, 0, 0, 691 /* 24 */ 0, 0, 0, 0, 692 /* 28 */ 0, 0, UTIMERLO, UTIMERHI 693 }; 694 695 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 696 return MCDisassembler::Fail; 697 698 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 699 if (CtrlRegDecoderTable[RegNo] == NoRegister) 700 return MCDisassembler::Fail; 701 702 unsigned Register = CtrlRegDecoderTable[RegNo]; 703 Inst.addOperand(MCOperand::createReg(Register)); 704 return MCDisassembler::Success; 705 } 706 707 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 708 uint64_t /*Address*/, 709 const void *Decoder) { 710 using namespace Hexagon; 711 712 static const MCPhysReg CtrlReg64DecoderTable[] = { 713 /* 0 */ C1_0, 0, C3_2, 0, 714 /* 4 */ C5_4, 0, C7_6, 0, 715 /* 8 */ C9_8, 0, C11_10, 0, 716 /* 12 */ CS, 0, UPCYCLE, 0, 717 /* 16 */ C17_16, 0, PKTCOUNT, 0, 718 /* 20 */ 0, 0, 0, 0, 719 /* 24 */ 0, 0, 0, 0, 720 /* 28 */ 0, 0, UTIMER, 0 721 }; 722 723 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 724 return MCDisassembler::Fail; 725 726 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 727 if (CtrlReg64DecoderTable[RegNo] == NoRegister) 728 return MCDisassembler::Fail; 729 730 unsigned Register = CtrlReg64DecoderTable[RegNo]; 731 Inst.addOperand(MCOperand::createReg(Register)); 732 return MCDisassembler::Success; 733 } 734 735 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 736 uint64_t /*Address*/, 737 const void *Decoder) { 738 unsigned Register = 0; 739 switch (RegNo) { 740 case 0: 741 Register = Hexagon::M0; 742 break; 743 case 1: 744 Register = Hexagon::M1; 745 break; 746 default: 747 return MCDisassembler::Fail; 748 } 749 Inst.addOperand(MCOperand::createReg(Register)); 750 return MCDisassembler::Success; 751 } 752 753 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 754 uint64_t /*Address*/, 755 const void *Decoder) { 756 HexagonDisassembler const &Disassembler = disassembler(Decoder); 757 int64_t FullValue = fullValue(Disassembler, MI, tmp); 758 assert(FullValue >= 0 && "Negative in unsigned decoder"); 759 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 760 return MCDisassembler::Success; 761 } 762 763 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 764 uint64_t /*Address*/, const void *Decoder) { 765 HexagonDisassembler const &Disassembler = disassembler(Decoder); 766 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 767 tmp = SignExtend64(tmp, Bits); 768 signedDecoder<32>(MI, tmp, Decoder); 769 return MCDisassembler::Success; 770 } 771 772 // custom decoder for various jump/call immediates 773 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 774 const void *Decoder) { 775 HexagonDisassembler const &Disassembler = disassembler(Decoder); 776 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 777 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 778 if (Bits == 0) 779 Bits = 15; 780 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits)); 781 uint32_t Extended = FullValue + Address; 782 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) 783 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 784 return MCDisassembler::Success; 785 } 786