1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCTargetDesc.h" 16 #include "MCTargetDesc/HexagonMCInstrInfo.h" 17 #include "MCTargetDesc/HexagonInstPrinter.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/MC/MCDisassembler.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrDesc.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/LEB128.h" 30 #include "llvm/Support/MemoryObject.h" 31 #include "llvm/Support/raw_ostream.h" 32 #include "llvm/Support/TargetRegistry.h" 33 #include <vector> 34 35 using namespace llvm; 36 using namespace Hexagon; 37 38 typedef MCDisassembler::DecodeStatus DecodeStatus; 39 40 namespace { 41 /// \brief Hexagon disassembler for all Hexagon platforms. 42 class HexagonDisassembler : public MCDisassembler { 43 public: 44 std::unique_ptr<MCInstrInfo const> const MCII; 45 std::unique_ptr<MCInst *> CurrentBundle; 46 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 47 MCInstrInfo const *MCII) 48 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} 49 50 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 51 ArrayRef<uint8_t> Bytes, uint64_t Address, 52 raw_ostream &VStream, raw_ostream &CStream, 53 bool &Complete) const; 54 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 55 ArrayRef<uint8_t> Bytes, uint64_t Address, 56 raw_ostream &VStream, 57 raw_ostream &CStream) const override; 58 59 void adjustExtendedInstructions(MCInst &MCI, MCInst const &MCB) const; 60 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; 61 }; 62 } 63 64 // Forward declare these because the auto-generated code will reference them. 65 // Definitions are further down. 66 67 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 68 uint64_t Address, 69 const void *Decoder); 70 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 71 uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 98 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn); 99 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, 100 void const *Decoder); 101 102 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 103 raw_ostream &os); 104 105 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg); 106 107 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 108 uint64_t Address, const void *Decoder); 109 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 112 const void *Decoder); 113 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 116 const void *Decoder); 117 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 118 const void *Decoder); 119 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 122 const void *Decoder); 123 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 128 const void *Decoder); 129 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 134 const void *Decoder); 135 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 136 const void *Decoder); 137 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 138 const void *Decoder); 139 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 140 const void *Decoder); 141 142 #include "HexagonGenDisassemblerTables.inc" 143 144 static MCDisassembler *createHexagonDisassembler(const Target &T, 145 const MCSubtargetInfo &STI, 146 MCContext &Ctx) { 147 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 148 } 149 150 extern "C" void LLVMInitializeHexagonDisassembler() { 151 TargetRegistry::RegisterMCDisassembler(TheHexagonTarget, 152 createHexagonDisassembler); 153 } 154 155 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 156 ArrayRef<uint8_t> Bytes, 157 uint64_t Address, 158 raw_ostream &os, 159 raw_ostream &cs) const { 160 DecodeStatus Result = DecodeStatus::Success; 161 bool Complete = false; 162 Size = 0; 163 164 *CurrentBundle = &MI; 165 MI.setOpcode(Hexagon::BUNDLE); 166 MI.addOperand(MCOperand::createImm(0)); 167 while (Result == Success && Complete == false) { 168 if (Bytes.size() < HEXAGON_INSTR_SIZE) 169 return MCDisassembler::Fail; 170 MCInst *Inst = new (getContext()) MCInst; 171 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 172 MI.addOperand(MCOperand::createInst(Inst)); 173 Size += HEXAGON_INSTR_SIZE; 174 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 175 } 176 if(Result == MCDisassembler::Fail) 177 return Result; 178 HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo()); 179 if(!Checker.check()) 180 return MCDisassembler::Fail; 181 return MCDisassembler::Success; 182 } 183 184 namespace { 185 HexagonDisassembler const &disassembler(void const *Decoder) { 186 return *static_cast<HexagonDisassembler const *>(Decoder); 187 } 188 MCContext &contextFromDecoder(void const *Decoder) { 189 return disassembler(Decoder).getContext(); 190 } 191 } 192 193 DecodeStatus HexagonDisassembler::getSingleInstruction( 194 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 195 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 196 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 197 198 uint32_t Instruction = 199 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 200 201 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 202 if ((Instruction & HexagonII::INST_PARSE_MASK) == 203 HexagonII::INST_PARSE_LOOP_END) { 204 if (BundleSize == 0) 205 HexagonMCInstrInfo::setInnerLoop(MCB); 206 else if (BundleSize == 1) 207 HexagonMCInstrInfo::setOuterLoop(MCB); 208 else 209 return DecodeStatus::Fail; 210 } 211 212 DecodeStatus Result = DecodeStatus::Success; 213 if ((Instruction & HexagonII::INST_PARSE_MASK) == 214 HexagonII::INST_PARSE_DUPLEX) { 215 // Determine the instruction class of each instruction in the duplex. 216 unsigned duplexIClass, IClassLow, IClassHigh; 217 218 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 219 switch (duplexIClass) { 220 default: 221 return MCDisassembler::Fail; 222 case 0: 223 IClassLow = HexagonII::HSIG_L1; 224 IClassHigh = HexagonII::HSIG_L1; 225 break; 226 case 1: 227 IClassLow = HexagonII::HSIG_L2; 228 IClassHigh = HexagonII::HSIG_L1; 229 break; 230 case 2: 231 IClassLow = HexagonII::HSIG_L2; 232 IClassHigh = HexagonII::HSIG_L2; 233 break; 234 case 3: 235 IClassLow = HexagonII::HSIG_A; 236 IClassHigh = HexagonII::HSIG_A; 237 break; 238 case 4: 239 IClassLow = HexagonII::HSIG_L1; 240 IClassHigh = HexagonII::HSIG_A; 241 break; 242 case 5: 243 IClassLow = HexagonII::HSIG_L2; 244 IClassHigh = HexagonII::HSIG_A; 245 break; 246 case 6: 247 IClassLow = HexagonII::HSIG_S1; 248 IClassHigh = HexagonII::HSIG_A; 249 break; 250 case 7: 251 IClassLow = HexagonII::HSIG_S2; 252 IClassHigh = HexagonII::HSIG_A; 253 break; 254 case 8: 255 IClassLow = HexagonII::HSIG_S1; 256 IClassHigh = HexagonII::HSIG_L1; 257 break; 258 case 9: 259 IClassLow = HexagonII::HSIG_S1; 260 IClassHigh = HexagonII::HSIG_L2; 261 break; 262 case 10: 263 IClassLow = HexagonII::HSIG_S1; 264 IClassHigh = HexagonII::HSIG_S1; 265 break; 266 case 11: 267 IClassLow = HexagonII::HSIG_S2; 268 IClassHigh = HexagonII::HSIG_S1; 269 break; 270 case 12: 271 IClassLow = HexagonII::HSIG_S2; 272 IClassHigh = HexagonII::HSIG_L1; 273 break; 274 case 13: 275 IClassLow = HexagonII::HSIG_S2; 276 IClassHigh = HexagonII::HSIG_L2; 277 break; 278 case 14: 279 IClassLow = HexagonII::HSIG_S2; 280 IClassHigh = HexagonII::HSIG_S2; 281 break; 282 } 283 284 // Set the MCInst to be a duplex instruction. Which one doesn't matter. 285 MI.setOpcode(Hexagon::DuplexIClass0); 286 287 // Decode each instruction in the duplex. 288 // Create an MCInst for each instruction. 289 unsigned instLow = Instruction & 0x1fff; 290 unsigned instHigh = (Instruction >> 16) & 0x1fff; 291 unsigned opLow; 292 if (GetSubinstOpcode(IClassLow, instLow, opLow, os) != 293 MCDisassembler::Success) 294 return MCDisassembler::Fail; 295 unsigned opHigh; 296 if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) != 297 MCDisassembler::Success) 298 return MCDisassembler::Fail; 299 MCInst *MILow = new (getContext()) MCInst; 300 MILow->setOpcode(opLow); 301 MCInst *MIHigh = new (getContext()) MCInst; 302 MIHigh->setOpcode(opHigh); 303 addSubinstOperands(MILow, opLow, instLow); 304 addSubinstOperands(MIHigh, opHigh, instHigh); 305 // see ConvertToSubInst() in 306 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 307 308 // Add the duplex instruction MCInsts as operands to the passed in MCInst. 309 MCOperand OPLow = MCOperand::createInst(MILow); 310 MCOperand OPHigh = MCOperand::createInst(MIHigh); 311 MI.addOperand(OPLow); 312 MI.addOperand(OPHigh); 313 Complete = true; 314 } else { 315 if ((Instruction & HexagonII::INST_PARSE_MASK) == 316 HexagonII::INST_PARSE_PACKET_END) 317 Complete = true; 318 // Calling the auto-generated decoder function. 319 Result = 320 decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); 321 322 // If a, "standard" insn isn't found check special cases. 323 if (MCDisassembler::Success != Result || 324 MI.getOpcode() == Hexagon::A4_ext) { 325 Result = decodeImmext(MI, Instruction, this); 326 if (MCDisassembler::Success != Result) { 327 Result = decodeSpecial(MI, Instruction); 328 } 329 } else { 330 // If the instruction is a compound instruction, register values will 331 // follow the duplex model, so the register values in the MCInst are 332 // incorrect. If the instruction is a compound, loop through the 333 // operands and change registers appropriately. 334 if (llvm::HexagonMCInstrInfo::getType(*MCII, MI) == 335 HexagonII::TypeCOMPOUND) { 336 for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) { 337 if (i->isReg()) { 338 unsigned reg = i->getReg() - Hexagon::R0; 339 i->setReg(getRegFromSubinstEncoding(reg)); 340 } 341 } 342 } 343 } 344 } 345 346 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 347 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 348 MCOperand &MCO = MI.getOperand(OpIndex); 349 assert(MCO.isReg() && "New value consumers must be registers"); 350 unsigned Register = 351 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 352 if ((Register & 0x6) == 0) 353 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 354 return MCDisassembler::Fail; 355 unsigned Lookback = (Register & 0x6) >> 1; 356 unsigned Offset = 1; 357 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 358 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 359 auto i = Instructions.end() - 1; 360 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 361 if (i == n) 362 // Couldn't find producer 363 return MCDisassembler::Fail; 364 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) 365 // Skip scalars when calculating distances for vectors 366 ++Lookback; 367 if (HexagonMCInstrInfo::isImmext(*i->getInst())) 368 ++Lookback; 369 if (Offset == Lookback) 370 break; 371 } 372 auto const &Inst = *i->getInst(); 373 bool SubregBit = (Register & 0x1) != 0; 374 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 375 // If subreg bit is set we're selecting the second produced newvalue 376 unsigned Producer = 377 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 378 assert(Producer != Hexagon::NoRegister); 379 MCO.setReg(Producer); 380 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 381 unsigned Producer = 382 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 383 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 384 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 385 else if (SubregBit) 386 // Subreg bit should not be set for non-doublevector newvalue producers 387 return MCDisassembler::Fail; 388 assert(Producer != Hexagon::NoRegister); 389 MCO.setReg(Producer); 390 } else 391 return MCDisassembler::Fail; 392 } 393 394 adjustExtendedInstructions(MI, MCB); 395 MCInst const *Extender = 396 HexagonMCInstrInfo::extenderForIndex(MCB, 397 HexagonMCInstrInfo::bundleSize(MCB)); 398 if(Extender != nullptr) { 399 MCInst const & Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ? 400 *MI.getOperand(1).getInst() : MI; 401 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 402 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 403 return MCDisassembler::Fail; 404 } 405 return Result; 406 } 407 408 void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI, 409 MCInst const &MCB) const { 410 if (!HexagonMCInstrInfo::hasExtenderForIndex( 411 MCB, HexagonMCInstrInfo::bundleSize(MCB))) { 412 unsigned opcode; 413 // This code is used by the disassembler to disambiguate between GP 414 // relative and absolute addressing instructions since they both have 415 // same encoding bits. However, an absolute addressing instruction must 416 // follow an immediate extender. Disassembler alwaus select absolute 417 // addressing instructions first and uses this code to change them into 418 // GP relative instruction in the absence of the corresponding immediate 419 // extender. 420 switch (MCI.getOpcode()) { 421 case Hexagon::S2_storerbabs: 422 opcode = Hexagon::S2_storerbgp; 423 break; 424 case Hexagon::S2_storerhabs: 425 opcode = Hexagon::S2_storerhgp; 426 break; 427 case Hexagon::S2_storerfabs: 428 opcode = Hexagon::S2_storerfgp; 429 break; 430 case Hexagon::S2_storeriabs: 431 opcode = Hexagon::S2_storerigp; 432 break; 433 case Hexagon::S2_storerbnewabs: 434 opcode = Hexagon::S2_storerbnewgp; 435 break; 436 case Hexagon::S2_storerhnewabs: 437 opcode = Hexagon::S2_storerhnewgp; 438 break; 439 case Hexagon::S2_storerinewabs: 440 opcode = Hexagon::S2_storerinewgp; 441 break; 442 case Hexagon::S2_storerdabs: 443 opcode = Hexagon::S2_storerdgp; 444 break; 445 case Hexagon::L4_loadrb_abs: 446 opcode = Hexagon::L2_loadrbgp; 447 break; 448 case Hexagon::L4_loadrub_abs: 449 opcode = Hexagon::L2_loadrubgp; 450 break; 451 case Hexagon::L4_loadrh_abs: 452 opcode = Hexagon::L2_loadrhgp; 453 break; 454 case Hexagon::L4_loadruh_abs: 455 opcode = Hexagon::L2_loadruhgp; 456 break; 457 case Hexagon::L4_loadri_abs: 458 opcode = Hexagon::L2_loadrigp; 459 break; 460 case Hexagon::L4_loadrd_abs: 461 opcode = Hexagon::L2_loadrdgp; 462 break; 463 default: 464 opcode = MCI.getOpcode(); 465 } 466 MCI.setOpcode(opcode); 467 } 468 } 469 470 namespace llvm { 471 extern const MCInstrDesc HexagonInsts[]; 472 } 473 474 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 475 const uint16_t Table[], size_t Size) { 476 if (RegNo < Size) { 477 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 478 return MCDisassembler::Success; 479 } else 480 return MCDisassembler::Fail; 481 } 482 483 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 484 uint64_t Address, 485 const void *Decoder) { 486 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 487 } 488 489 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 490 uint64_t Address, 491 const void *Decoder) { 492 static const uint16_t IntRegDecoderTable[] = { 493 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 494 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 495 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 496 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 497 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 498 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 499 Hexagon::R30, Hexagon::R31}; 500 501 return (DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable, 502 sizeof(IntRegDecoderTable))); 503 } 504 505 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 506 uint64_t /*Address*/, 507 const void *Decoder) { 508 static const uint16_t VecRegDecoderTable[] = { 509 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 510 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 511 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 512 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 513 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 514 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 515 Hexagon::V30, Hexagon::V31}; 516 517 return (DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable, 518 sizeof(VecRegDecoderTable))); 519 } 520 521 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 522 uint64_t /*Address*/, 523 const void *Decoder) { 524 static const uint16_t DoubleRegDecoderTable[] = { 525 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 526 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 527 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 528 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 529 530 return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable, 531 sizeof(DoubleRegDecoderTable))); 532 } 533 534 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 535 uint64_t /*Address*/, 536 const void *Decoder) { 537 static const uint16_t VecDblRegDecoderTable[] = { 538 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 539 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 540 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 541 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 542 543 return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable, 544 sizeof(VecDblRegDecoderTable))); 545 } 546 547 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 548 uint64_t /*Address*/, 549 const void *Decoder) { 550 static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 551 Hexagon::P2, Hexagon::P3}; 552 553 return (DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable, 554 sizeof(PredRegDecoderTable))); 555 } 556 557 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 558 uint64_t /*Address*/, 559 const void *Decoder) { 560 static const uint16_t VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 561 Hexagon::Q2, Hexagon::Q3}; 562 563 return (DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable, 564 sizeof(VecPredRegDecoderTable))); 565 } 566 567 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 568 uint64_t /*Address*/, 569 const void *Decoder) { 570 static const uint16_t CtrlRegDecoderTable[] = { 571 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, 572 Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7, 573 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, 574 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC 575 }; 576 577 if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0])) 578 return MCDisassembler::Fail; 579 580 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister) 581 return MCDisassembler::Fail; 582 583 unsigned Register = CtrlRegDecoderTable[RegNo]; 584 Inst.addOperand(MCOperand::createReg(Register)); 585 return MCDisassembler::Success; 586 } 587 588 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 589 uint64_t /*Address*/, 590 const void *Decoder) { 591 static const uint16_t CtrlReg64DecoderTable[] = { 592 Hexagon::C1_0, Hexagon::NoRegister, 593 Hexagon::C3_2, Hexagon::NoRegister, 594 Hexagon::C7_6, Hexagon::NoRegister, 595 Hexagon::C9_8, Hexagon::NoRegister, 596 Hexagon::C11_10, Hexagon::NoRegister, 597 Hexagon::CS, Hexagon::NoRegister, 598 Hexagon::UPC, Hexagon::NoRegister 599 }; 600 601 if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0])) 602 return MCDisassembler::Fail; 603 604 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister) 605 return MCDisassembler::Fail; 606 607 unsigned Register = CtrlReg64DecoderTable[RegNo]; 608 Inst.addOperand(MCOperand::createReg(Register)); 609 return MCDisassembler::Success; 610 } 611 612 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 613 uint64_t /*Address*/, 614 const void *Decoder) { 615 unsigned Register = 0; 616 switch (RegNo) { 617 case 0: 618 Register = Hexagon::M0; 619 break; 620 case 1: 621 Register = Hexagon::M1; 622 break; 623 default: 624 return MCDisassembler::Fail; 625 } 626 Inst.addOperand(MCOperand::createReg(Register)); 627 return MCDisassembler::Success; 628 } 629 630 namespace { 631 uint32_t fullValue(MCInstrInfo const &MCII, 632 MCInst &MCB, 633 MCInst &MI, 634 int64_t Value) { 635 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 636 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 637 if(!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 638 return Value; 639 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 640 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 641 int64_t Bits; 642 bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); 643 assert(Success);(void)Success; 644 uint32_t Upper26 = static_cast<uint32_t>(Bits); 645 uint32_t Operand = Upper26 | Lower6; 646 return Operand; 647 } 648 template <size_t T> 649 void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 650 HexagonDisassembler const &Disassembler = disassembler(Decoder); 651 int64_t FullValue = fullValue(*Disassembler.MCII, 652 **Disassembler.CurrentBundle, 653 MI, SignExtend64<T>(tmp)); 654 int64_t Extended = SignExtend64<32>(FullValue); 655 HexagonMCInstrInfo::addConstant(MI, Extended, 656 Disassembler.getContext()); 657 } 658 } 659 660 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 661 uint64_t /*Address*/, 662 const void *Decoder) { 663 HexagonDisassembler const &Disassembler = disassembler(Decoder); 664 int64_t FullValue = fullValue(*Disassembler.MCII, 665 **Disassembler.CurrentBundle, 666 MI, tmp); 667 assert(FullValue >= 0 && "Negative in unsigned decoder"); 668 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 669 return MCDisassembler::Success; 670 } 671 672 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, 673 uint64_t /*Address*/, const void *Decoder) { 674 signedDecoder<16>(MI, tmp, Decoder); 675 return MCDisassembler::Success; 676 } 677 678 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, 679 uint64_t /*Address*/, const void *Decoder) { 680 signedDecoder<12>(MI, tmp, Decoder); 681 return MCDisassembler::Success; 682 } 683 684 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, 685 uint64_t /*Address*/, const void *Decoder) { 686 signedDecoder<11>(MI, tmp, Decoder); 687 return MCDisassembler::Success; 688 } 689 690 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, 691 uint64_t /*Address*/, const void *Decoder) { 692 HexagonMCInstrInfo::addConstant(MI, SignExtend64<12>(tmp), contextFromDecoder(Decoder)); 693 return MCDisassembler::Success; 694 } 695 696 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, 697 uint64_t /*Address*/, const void *Decoder) { 698 signedDecoder<13>(MI, tmp, Decoder); 699 return MCDisassembler::Success; 700 } 701 702 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, 703 uint64_t /*Address*/, const void *Decoder) { 704 signedDecoder<14>(MI, tmp, Decoder); 705 return MCDisassembler::Success; 706 } 707 708 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, 709 uint64_t /*Address*/, const void *Decoder) { 710 signedDecoder<10>(MI, tmp, Decoder); 711 return MCDisassembler::Success; 712 } 713 714 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, 715 const void *Decoder) { 716 signedDecoder<8>(MI, tmp, Decoder); 717 return MCDisassembler::Success; 718 } 719 720 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, 721 uint64_t /*Address*/, const void *Decoder) { 722 signedDecoder<6>(MI, tmp, Decoder); 723 return MCDisassembler::Success; 724 } 725 726 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, 727 uint64_t /*Address*/, const void *Decoder) { 728 signedDecoder<4>(MI, tmp, Decoder); 729 return MCDisassembler::Success; 730 } 731 732 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, 733 uint64_t /*Address*/, const void *Decoder) { 734 signedDecoder<5>(MI, tmp, Decoder); 735 return MCDisassembler::Success; 736 } 737 738 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, 739 uint64_t /*Address*/, const void *Decoder) { 740 signedDecoder<6>(MI, tmp, Decoder); 741 return MCDisassembler::Success; 742 } 743 744 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, 745 uint64_t /*Address*/, const void *Decoder) { 746 signedDecoder<7>(MI, tmp, Decoder); 747 return MCDisassembler::Success; 748 } 749 750 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, 751 uint64_t /*Address*/, const void *Decoder) { 752 signedDecoder<10>(MI, tmp, Decoder); 753 return MCDisassembler::Success; 754 } 755 756 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, 757 uint64_t /*Address*/, const void *Decoder) { 758 signedDecoder<19>(MI, tmp, Decoder); 759 return MCDisassembler::Success; 760 } 761 762 // custom decoder for various jump/call immediates 763 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 764 const void *Decoder) { 765 HexagonDisassembler const &Disassembler = disassembler(Decoder); 766 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 767 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 768 if (Bits == 0) 769 Bits = 15; 770 uint32_t FullValue = fullValue(*Disassembler.MCII, 771 **Disassembler.CurrentBundle, 772 MI, SignExtend64(tmp, Bits)); 773 int64_t Extended = SignExtend64<32>(FullValue) + Address; 774 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 775 0, 4)) 776 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 777 return MCDisassembler::Success; 778 } 779 780 // Addressing mode dependent load store opcode map. 781 // - If an insn is preceded by an extender the address is absolute. 782 // - memw(##symbol) = r0 783 // - If an insn is not preceded by an extender the address is GP relative. 784 // - memw(gp + #symbol) = r0 785 // Please note that the instructions must be ordered in the descending order 786 // of their opcode. 787 // HexagonII::INST_ICLASS_ST 788 static unsigned int StoreConditionalOpcodeData[][2] = { 789 {S4_pstorerdfnew_abs, 0xafc02084}, 790 {S4_pstorerdtnew_abs, 0xafc02080}, 791 {S4_pstorerdf_abs, 0xafc00084}, 792 {S4_pstorerdt_abs, 0xafc00080}, 793 {S4_pstorerinewfnew_abs, 0xafa03084}, 794 {S4_pstorerinewtnew_abs, 0xafa03080}, 795 {S4_pstorerhnewfnew_abs, 0xafa02884}, 796 {S4_pstorerhnewtnew_abs, 0xafa02880}, 797 {S4_pstorerbnewfnew_abs, 0xafa02084}, 798 {S4_pstorerbnewtnew_abs, 0xafa02080}, 799 {S4_pstorerinewf_abs, 0xafa01084}, 800 {S4_pstorerinewt_abs, 0xafa01080}, 801 {S4_pstorerhnewf_abs, 0xafa00884}, 802 {S4_pstorerhnewt_abs, 0xafa00880}, 803 {S4_pstorerbnewf_abs, 0xafa00084}, 804 {S4_pstorerbnewt_abs, 0xafa00080}, 805 {S4_pstorerifnew_abs, 0xaf802084}, 806 {S4_pstoreritnew_abs, 0xaf802080}, 807 {S4_pstorerif_abs, 0xaf800084}, 808 {S4_pstorerit_abs, 0xaf800080}, 809 {S4_pstorerhfnew_abs, 0xaf402084}, 810 {S4_pstorerhtnew_abs, 0xaf402080}, 811 {S4_pstorerhf_abs, 0xaf400084}, 812 {S4_pstorerht_abs, 0xaf400080}, 813 {S4_pstorerbfnew_abs, 0xaf002084}, 814 {S4_pstorerbtnew_abs, 0xaf002080}, 815 {S4_pstorerbf_abs, 0xaf000084}, 816 {S4_pstorerbt_abs, 0xaf000080}}; 817 // HexagonII::INST_ICLASS_LD 818 819 // HexagonII::INST_ICLASS_LD_ST_2 820 static unsigned int LoadStoreOpcodeData[][2] = {{L4_loadrd_abs, 0x49c00000}, 821 {L4_loadri_abs, 0x49800000}, 822 {L4_loadruh_abs, 0x49600000}, 823 {L4_loadrh_abs, 0x49400000}, 824 {L4_loadrub_abs, 0x49200000}, 825 {L4_loadrb_abs, 0x49000000}, 826 {S2_storerdabs, 0x48c00000}, 827 {S2_storerinewabs, 0x48a01000}, 828 {S2_storerhnewabs, 0x48a00800}, 829 {S2_storerbnewabs, 0x48a00000}, 830 {S2_storeriabs, 0x48800000}, 831 {S2_storerfabs, 0x48600000}, 832 {S2_storerhabs, 0x48400000}, 833 {S2_storerbabs, 0x48000000}}; 834 static int NumCondS = 835 sizeof(StoreConditionalOpcodeData) / sizeof(StoreConditionalOpcodeData[0]); 836 static int NumLS = sizeof(LoadStoreOpcodeData) / sizeof(LoadStoreOpcodeData[0]); 837 838 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) { 839 840 unsigned MachineOpcode = 0; 841 unsigned LLVMOpcode = 0; 842 int i; 843 844 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_ST) { 845 for (i = 0; i < NumCondS; ++i) { 846 if ((insn & StoreConditionalOpcodeData[i][1]) == 847 StoreConditionalOpcodeData[i][1]) { 848 MachineOpcode = StoreConditionalOpcodeData[i][1]; 849 LLVMOpcode = StoreConditionalOpcodeData[i][0]; 850 break; 851 } 852 } 853 } 854 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_LD_ST_2) { 855 for (i = 0; i < NumLS; ++i) { 856 if ((insn & LoadStoreOpcodeData[i][1]) == LoadStoreOpcodeData[i][1]) { 857 MachineOpcode = LoadStoreOpcodeData[i][1]; 858 LLVMOpcode = LoadStoreOpcodeData[i][0]; 859 break; 860 } 861 } 862 } 863 864 if (MachineOpcode) { 865 unsigned Value = 0; 866 unsigned shift = 0; 867 MI.setOpcode(LLVMOpcode); 868 // Remove the parse bits from the insn. 869 insn &= ~HexagonII::INST_PARSE_MASK; 870 871 switch (LLVMOpcode) { 872 default: 873 return MCDisassembler::Fail; 874 break; 875 876 case Hexagon::S4_pstorerdf_abs: 877 case Hexagon::S4_pstorerdt_abs: 878 case Hexagon::S4_pstorerdfnew_abs: 879 case Hexagon::S4_pstorerdtnew_abs: { 880 // op: Pv 881 Value = insn & UINT64_C(3); 882 DecodePredRegsRegisterClass(MI, Value, 0, 0); 883 // op: u6 884 Value = (insn >> 12) & UINT64_C(48); 885 Value |= (insn >> 3) & UINT64_C(15); 886 MI.addOperand(MCOperand::createImm(Value)); 887 // op: Rtt 888 Value = (insn >> 8) & UINT64_C(31); 889 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 890 break; 891 } 892 893 case Hexagon::S4_pstorerbnewf_abs: 894 case Hexagon::S4_pstorerbnewt_abs: 895 case Hexagon::S4_pstorerbnewfnew_abs: 896 case Hexagon::S4_pstorerbnewtnew_abs: 897 case Hexagon::S4_pstorerhnewf_abs: 898 case Hexagon::S4_pstorerhnewt_abs: 899 case Hexagon::S4_pstorerhnewfnew_abs: 900 case Hexagon::S4_pstorerhnewtnew_abs: 901 case Hexagon::S4_pstorerinewf_abs: 902 case Hexagon::S4_pstorerinewt_abs: 903 case Hexagon::S4_pstorerinewfnew_abs: 904 case Hexagon::S4_pstorerinewtnew_abs: { 905 // op: Pv 906 Value = insn & UINT64_C(3); 907 DecodePredRegsRegisterClass(MI, Value, 0, 0); 908 // op: u6 909 Value = (insn >> 12) & UINT64_C(48); 910 Value |= (insn >> 3) & UINT64_C(15); 911 MI.addOperand(MCOperand::createImm(Value)); 912 // op: Nt 913 Value = (insn >> 8) & UINT64_C(7); 914 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 915 break; 916 } 917 918 case Hexagon::S4_pstorerbf_abs: 919 case Hexagon::S4_pstorerbt_abs: 920 case Hexagon::S4_pstorerbfnew_abs: 921 case Hexagon::S4_pstorerbtnew_abs: 922 case Hexagon::S4_pstorerhf_abs: 923 case Hexagon::S4_pstorerht_abs: 924 case Hexagon::S4_pstorerhfnew_abs: 925 case Hexagon::S4_pstorerhtnew_abs: 926 case Hexagon::S4_pstorerif_abs: 927 case Hexagon::S4_pstorerit_abs: 928 case Hexagon::S4_pstorerifnew_abs: 929 case Hexagon::S4_pstoreritnew_abs: { 930 // op: Pv 931 Value = insn & UINT64_C(3); 932 DecodePredRegsRegisterClass(MI, Value, 0, 0); 933 // op: u6 934 Value = (insn >> 12) & UINT64_C(48); 935 Value |= (insn >> 3) & UINT64_C(15); 936 MI.addOperand(MCOperand::createImm(Value)); 937 // op: Rt 938 Value = (insn >> 8) & UINT64_C(31); 939 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 940 break; 941 } 942 943 case Hexagon::L4_ploadrdf_abs: 944 case Hexagon::L4_ploadrdt_abs: 945 case Hexagon::L4_ploadrdfnew_abs: 946 case Hexagon::L4_ploadrdtnew_abs: { 947 // op: Rdd 948 Value = insn & UINT64_C(31); 949 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 950 // op: Pt 951 Value = ((insn >> 9) & UINT64_C(3)); 952 DecodePredRegsRegisterClass(MI, Value, 0, 0); 953 // op: u6 954 Value = ((insn >> 15) & UINT64_C(62)); 955 Value |= ((insn >> 8) & UINT64_C(1)); 956 MI.addOperand(MCOperand::createImm(Value)); 957 break; 958 } 959 960 case Hexagon::L4_ploadrbf_abs: 961 case Hexagon::L4_ploadrbt_abs: 962 case Hexagon::L4_ploadrbfnew_abs: 963 case Hexagon::L4_ploadrbtnew_abs: 964 case Hexagon::L4_ploadrhf_abs: 965 case Hexagon::L4_ploadrht_abs: 966 case Hexagon::L4_ploadrhfnew_abs: 967 case Hexagon::L4_ploadrhtnew_abs: 968 case Hexagon::L4_ploadrubf_abs: 969 case Hexagon::L4_ploadrubt_abs: 970 case Hexagon::L4_ploadrubfnew_abs: 971 case Hexagon::L4_ploadrubtnew_abs: 972 case Hexagon::L4_ploadruhf_abs: 973 case Hexagon::L4_ploadruht_abs: 974 case Hexagon::L4_ploadruhfnew_abs: 975 case Hexagon::L4_ploadruhtnew_abs: 976 case Hexagon::L4_ploadrif_abs: 977 case Hexagon::L4_ploadrit_abs: 978 case Hexagon::L4_ploadrifnew_abs: 979 case Hexagon::L4_ploadritnew_abs: 980 // op: Rd 981 Value = insn & UINT64_C(31); 982 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 983 // op: Pt 984 Value = (insn >> 9) & UINT64_C(3); 985 DecodePredRegsRegisterClass(MI, Value, 0, 0); 986 // op: u6 987 Value = (insn >> 15) & UINT64_C(62); 988 Value |= (insn >> 8) & UINT64_C(1); 989 MI.addOperand(MCOperand::createImm(Value)); 990 break; 991 992 // op: g16_2 993 case (Hexagon::L4_loadri_abs): 994 ++shift; 995 // op: g16_1 996 case Hexagon::L4_loadrh_abs: 997 case Hexagon::L4_loadruh_abs: 998 ++shift; 999 // op: g16_0 1000 case Hexagon::L4_loadrb_abs: 1001 case Hexagon::L4_loadrub_abs: { 1002 // op: Rd 1003 Value |= insn & UINT64_C(31); 1004 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1005 Value = (insn >> 11) & UINT64_C(49152); 1006 Value |= (insn >> 7) & UINT64_C(15872); 1007 Value |= (insn >> 5) & UINT64_C(511); 1008 MI.addOperand(MCOperand::createImm(Value << shift)); 1009 break; 1010 } 1011 1012 case Hexagon::L4_loadrd_abs: { 1013 Value = insn & UINT64_C(31); 1014 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 1015 Value = (insn >> 11) & UINT64_C(49152); 1016 Value |= (insn >> 7) & UINT64_C(15872); 1017 Value |= (insn >> 5) & UINT64_C(511); 1018 MI.addOperand(MCOperand::createImm(Value << 3)); 1019 break; 1020 } 1021 1022 case Hexagon::S2_storerdabs: { 1023 // op: g16_3 1024 Value = (insn >> 11) & UINT64_C(49152); 1025 Value |= (insn >> 7) & UINT64_C(15872); 1026 Value |= (insn >> 5) & UINT64_C(256); 1027 Value |= insn & UINT64_C(255); 1028 MI.addOperand(MCOperand::createImm(Value << 3)); 1029 // op: Rtt 1030 Value = (insn >> 8) & UINT64_C(31); 1031 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 1032 break; 1033 } 1034 1035 // op: g16_2 1036 case Hexagon::S2_storerinewabs: 1037 ++shift; 1038 // op: g16_1 1039 case Hexagon::S2_storerhnewabs: 1040 ++shift; 1041 // op: g16_0 1042 case Hexagon::S2_storerbnewabs: { 1043 Value = (insn >> 11) & UINT64_C(49152); 1044 Value |= (insn >> 7) & UINT64_C(15872); 1045 Value |= (insn >> 5) & UINT64_C(256); 1046 Value |= insn & UINT64_C(255); 1047 MI.addOperand(MCOperand::createImm(Value << shift)); 1048 // op: Nt 1049 Value = (insn >> 8) & UINT64_C(7); 1050 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1051 break; 1052 } 1053 1054 // op: g16_2 1055 case Hexagon::S2_storeriabs: 1056 ++shift; 1057 // op: g16_1 1058 case Hexagon::S2_storerhabs: 1059 case Hexagon::S2_storerfabs: 1060 ++shift; 1061 // op: g16_0 1062 case Hexagon::S2_storerbabs: { 1063 Value = (insn >> 11) & UINT64_C(49152); 1064 Value |= (insn >> 7) & UINT64_C(15872); 1065 Value |= (insn >> 5) & UINT64_C(256); 1066 Value |= insn & UINT64_C(255); 1067 MI.addOperand(MCOperand::createImm(Value << shift)); 1068 // op: Rt 1069 Value = (insn >> 8) & UINT64_C(31); 1070 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1071 break; 1072 } 1073 } 1074 return MCDisassembler::Success; 1075 } 1076 return MCDisassembler::Fail; 1077 } 1078 1079 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, 1080 void const *Decoder) { 1081 1082 // Instruction Class for a constant a extender: bits 31:28 = 0x0000 1083 if ((~insn & 0xf0000000) == 0xf0000000) { 1084 unsigned Value; 1085 // 27:16 High 12 bits of 26-bit extender. 1086 Value = (insn & 0x0fff0000) << 4; 1087 // 13:0 Low 14 bits of 26-bit extender. 1088 Value |= ((insn & 0x3fff) << 6); 1089 MI.setOpcode(Hexagon::A4_ext); 1090 HexagonMCInstrInfo::addConstant(MI, Value, contextFromDecoder(Decoder)); 1091 return MCDisassembler::Success; 1092 } 1093 return MCDisassembler::Fail; 1094 } 1095 1096 // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td 1097 enum subInstBinaryValues { 1098 V4_SA1_addi_BITS = 0x0000, 1099 V4_SA1_addi_MASK = 0x1800, 1100 V4_SA1_addrx_BITS = 0x1800, 1101 V4_SA1_addrx_MASK = 0x1f00, 1102 V4_SA1_addsp_BITS = 0x0c00, 1103 V4_SA1_addsp_MASK = 0x1c00, 1104 V4_SA1_and1_BITS = 0x1200, 1105 V4_SA1_and1_MASK = 0x1f00, 1106 V4_SA1_clrf_BITS = 0x1a70, 1107 V4_SA1_clrf_MASK = 0x1e70, 1108 V4_SA1_clrfnew_BITS = 0x1a50, 1109 V4_SA1_clrfnew_MASK = 0x1e70, 1110 V4_SA1_clrt_BITS = 0x1a60, 1111 V4_SA1_clrt_MASK = 0x1e70, 1112 V4_SA1_clrtnew_BITS = 0x1a40, 1113 V4_SA1_clrtnew_MASK = 0x1e70, 1114 V4_SA1_cmpeqi_BITS = 0x1900, 1115 V4_SA1_cmpeqi_MASK = 0x1f00, 1116 V4_SA1_combine0i_BITS = 0x1c00, 1117 V4_SA1_combine0i_MASK = 0x1d18, 1118 V4_SA1_combine1i_BITS = 0x1c08, 1119 V4_SA1_combine1i_MASK = 0x1d18, 1120 V4_SA1_combine2i_BITS = 0x1c10, 1121 V4_SA1_combine2i_MASK = 0x1d18, 1122 V4_SA1_combine3i_BITS = 0x1c18, 1123 V4_SA1_combine3i_MASK = 0x1d18, 1124 V4_SA1_combinerz_BITS = 0x1d08, 1125 V4_SA1_combinerz_MASK = 0x1d08, 1126 V4_SA1_combinezr_BITS = 0x1d00, 1127 V4_SA1_combinezr_MASK = 0x1d08, 1128 V4_SA1_dec_BITS = 0x1300, 1129 V4_SA1_dec_MASK = 0x1f00, 1130 V4_SA1_inc_BITS = 0x1100, 1131 V4_SA1_inc_MASK = 0x1f00, 1132 V4_SA1_seti_BITS = 0x0800, 1133 V4_SA1_seti_MASK = 0x1c00, 1134 V4_SA1_setin1_BITS = 0x1a00, 1135 V4_SA1_setin1_MASK = 0x1e40, 1136 V4_SA1_sxtb_BITS = 0x1500, 1137 V4_SA1_sxtb_MASK = 0x1f00, 1138 V4_SA1_sxth_BITS = 0x1400, 1139 V4_SA1_sxth_MASK = 0x1f00, 1140 V4_SA1_tfr_BITS = 0x1000, 1141 V4_SA1_tfr_MASK = 0x1f00, 1142 V4_SA1_zxtb_BITS = 0x1700, 1143 V4_SA1_zxtb_MASK = 0x1f00, 1144 V4_SA1_zxth_BITS = 0x1600, 1145 V4_SA1_zxth_MASK = 0x1f00, 1146 V4_SL1_loadri_io_BITS = 0x0000, 1147 V4_SL1_loadri_io_MASK = 0x1000, 1148 V4_SL1_loadrub_io_BITS = 0x1000, 1149 V4_SL1_loadrub_io_MASK = 0x1000, 1150 V4_SL2_deallocframe_BITS = 0x1f00, 1151 V4_SL2_deallocframe_MASK = 0x1fc0, 1152 V4_SL2_jumpr31_BITS = 0x1fc0, 1153 V4_SL2_jumpr31_MASK = 0x1fc4, 1154 V4_SL2_jumpr31_f_BITS = 0x1fc5, 1155 V4_SL2_jumpr31_f_MASK = 0x1fc7, 1156 V4_SL2_jumpr31_fnew_BITS = 0x1fc7, 1157 V4_SL2_jumpr31_fnew_MASK = 0x1fc7, 1158 V4_SL2_jumpr31_t_BITS = 0x1fc4, 1159 V4_SL2_jumpr31_t_MASK = 0x1fc7, 1160 V4_SL2_jumpr31_tnew_BITS = 0x1fc6, 1161 V4_SL2_jumpr31_tnew_MASK = 0x1fc7, 1162 V4_SL2_loadrb_io_BITS = 0x1000, 1163 V4_SL2_loadrb_io_MASK = 0x1800, 1164 V4_SL2_loadrd_sp_BITS = 0x1e00, 1165 V4_SL2_loadrd_sp_MASK = 0x1f00, 1166 V4_SL2_loadrh_io_BITS = 0x0000, 1167 V4_SL2_loadrh_io_MASK = 0x1800, 1168 V4_SL2_loadri_sp_BITS = 0x1c00, 1169 V4_SL2_loadri_sp_MASK = 0x1e00, 1170 V4_SL2_loadruh_io_BITS = 0x0800, 1171 V4_SL2_loadruh_io_MASK = 0x1800, 1172 V4_SL2_return_BITS = 0x1f40, 1173 V4_SL2_return_MASK = 0x1fc4, 1174 V4_SL2_return_f_BITS = 0x1f45, 1175 V4_SL2_return_f_MASK = 0x1fc7, 1176 V4_SL2_return_fnew_BITS = 0x1f47, 1177 V4_SL2_return_fnew_MASK = 0x1fc7, 1178 V4_SL2_return_t_BITS = 0x1f44, 1179 V4_SL2_return_t_MASK = 0x1fc7, 1180 V4_SL2_return_tnew_BITS = 0x1f46, 1181 V4_SL2_return_tnew_MASK = 0x1fc7, 1182 V4_SS1_storeb_io_BITS = 0x1000, 1183 V4_SS1_storeb_io_MASK = 0x1000, 1184 V4_SS1_storew_io_BITS = 0x0000, 1185 V4_SS1_storew_io_MASK = 0x1000, 1186 V4_SS2_allocframe_BITS = 0x1c00, 1187 V4_SS2_allocframe_MASK = 0x1e00, 1188 V4_SS2_storebi0_BITS = 0x1200, 1189 V4_SS2_storebi0_MASK = 0x1f00, 1190 V4_SS2_storebi1_BITS = 0x1300, 1191 V4_SS2_storebi1_MASK = 0x1f00, 1192 V4_SS2_stored_sp_BITS = 0x0a00, 1193 V4_SS2_stored_sp_MASK = 0x1e00, 1194 V4_SS2_storeh_io_BITS = 0x0000, 1195 V4_SS2_storeh_io_MASK = 0x1800, 1196 V4_SS2_storew_sp_BITS = 0x0800, 1197 V4_SS2_storew_sp_MASK = 0x1e00, 1198 V4_SS2_storewi0_BITS = 0x1000, 1199 V4_SS2_storewi0_MASK = 0x1f00, 1200 V4_SS2_storewi1_BITS = 0x1100, 1201 V4_SS2_storewi1_MASK = 0x1f00 1202 }; 1203 1204 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 1205 raw_ostream &os) { 1206 switch (IClass) { 1207 case HexagonII::HSIG_L1: 1208 if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS) 1209 op = Hexagon::V4_SL1_loadri_io; 1210 else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS) 1211 op = Hexagon::V4_SL1_loadrub_io; 1212 else { 1213 os << "<unknown subinstruction>"; 1214 return MCDisassembler::Fail; 1215 } 1216 break; 1217 case HexagonII::HSIG_L2: 1218 if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS) 1219 op = Hexagon::V4_SL2_deallocframe; 1220 else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS) 1221 op = Hexagon::V4_SL2_jumpr31; 1222 else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS) 1223 op = Hexagon::V4_SL2_jumpr31_f; 1224 else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS) 1225 op = Hexagon::V4_SL2_jumpr31_fnew; 1226 else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS) 1227 op = Hexagon::V4_SL2_jumpr31_t; 1228 else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS) 1229 op = Hexagon::V4_SL2_jumpr31_tnew; 1230 else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS) 1231 op = Hexagon::V4_SL2_loadrb_io; 1232 else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS) 1233 op = Hexagon::V4_SL2_loadrd_sp; 1234 else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS) 1235 op = Hexagon::V4_SL2_loadrh_io; 1236 else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS) 1237 op = Hexagon::V4_SL2_loadri_sp; 1238 else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS) 1239 op = Hexagon::V4_SL2_loadruh_io; 1240 else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS) 1241 op = Hexagon::V4_SL2_return; 1242 else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS) 1243 op = Hexagon::V4_SL2_return_f; 1244 else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS) 1245 op = Hexagon::V4_SL2_return_fnew; 1246 else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS) 1247 op = Hexagon::V4_SL2_return_t; 1248 else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS) 1249 op = Hexagon::V4_SL2_return_tnew; 1250 else { 1251 os << "<unknown subinstruction>"; 1252 return MCDisassembler::Fail; 1253 } 1254 break; 1255 case HexagonII::HSIG_A: 1256 if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS) 1257 op = Hexagon::V4_SA1_addi; 1258 else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS) 1259 op = Hexagon::V4_SA1_addrx; 1260 else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS) 1261 op = Hexagon::V4_SA1_addsp; 1262 else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS) 1263 op = Hexagon::V4_SA1_and1; 1264 else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS) 1265 op = Hexagon::V4_SA1_clrf; 1266 else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS) 1267 op = Hexagon::V4_SA1_clrfnew; 1268 else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS) 1269 op = Hexagon::V4_SA1_clrt; 1270 else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS) 1271 op = Hexagon::V4_SA1_clrtnew; 1272 else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS) 1273 op = Hexagon::V4_SA1_cmpeqi; 1274 else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS) 1275 op = Hexagon::V4_SA1_combine0i; 1276 else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS) 1277 op = Hexagon::V4_SA1_combine1i; 1278 else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS) 1279 op = Hexagon::V4_SA1_combine2i; 1280 else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS) 1281 op = Hexagon::V4_SA1_combine3i; 1282 else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS) 1283 op = Hexagon::V4_SA1_combinerz; 1284 else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS) 1285 op = Hexagon::V4_SA1_combinezr; 1286 else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS) 1287 op = Hexagon::V4_SA1_dec; 1288 else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS) 1289 op = Hexagon::V4_SA1_inc; 1290 else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS) 1291 op = Hexagon::V4_SA1_seti; 1292 else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS) 1293 op = Hexagon::V4_SA1_setin1; 1294 else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS) 1295 op = Hexagon::V4_SA1_sxtb; 1296 else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS) 1297 op = Hexagon::V4_SA1_sxth; 1298 else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS) 1299 op = Hexagon::V4_SA1_tfr; 1300 else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS) 1301 op = Hexagon::V4_SA1_zxtb; 1302 else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS) 1303 op = Hexagon::V4_SA1_zxth; 1304 else { 1305 os << "<unknown subinstruction>"; 1306 return MCDisassembler::Fail; 1307 } 1308 break; 1309 case HexagonII::HSIG_S1: 1310 if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS) 1311 op = Hexagon::V4_SS1_storeb_io; 1312 else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS) 1313 op = Hexagon::V4_SS1_storew_io; 1314 else { 1315 os << "<unknown subinstruction>"; 1316 return MCDisassembler::Fail; 1317 } 1318 break; 1319 case HexagonII::HSIG_S2: 1320 if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS) 1321 op = Hexagon::V4_SS2_allocframe; 1322 else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS) 1323 op = Hexagon::V4_SS2_storebi0; 1324 else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS) 1325 op = Hexagon::V4_SS2_storebi1; 1326 else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS) 1327 op = Hexagon::V4_SS2_stored_sp; 1328 else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS) 1329 op = Hexagon::V4_SS2_storeh_io; 1330 else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS) 1331 op = Hexagon::V4_SS2_storew_sp; 1332 else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS) 1333 op = Hexagon::V4_SS2_storewi0; 1334 else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS) 1335 op = Hexagon::V4_SS2_storewi1; 1336 else { 1337 os << "<unknown subinstruction>"; 1338 return MCDisassembler::Fail; 1339 } 1340 break; 1341 default: 1342 os << "<unknown>"; 1343 return MCDisassembler::Fail; 1344 } 1345 return MCDisassembler::Success; 1346 } 1347 1348 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) { 1349 if (encoded_reg < 8) 1350 return Hexagon::R0 + encoded_reg; 1351 else if (encoded_reg < 16) 1352 return Hexagon::R0 + encoded_reg + 8; 1353 1354 // patently false value 1355 return Hexagon::NoRegister; 1356 } 1357 1358 static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) { 1359 if (encoded_dreg < 4) 1360 return Hexagon::D0 + encoded_dreg; 1361 else if (encoded_dreg < 8) 1362 return Hexagon::D0 + encoded_dreg + 4; 1363 1364 // patently false value 1365 return Hexagon::NoRegister; 1366 } 1367 1368 void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode, 1369 unsigned inst) const { 1370 int64_t operand; 1371 MCOperand Op; 1372 switch (opcode) { 1373 case Hexagon::V4_SL2_deallocframe: 1374 case Hexagon::V4_SL2_jumpr31: 1375 case Hexagon::V4_SL2_jumpr31_f: 1376 case Hexagon::V4_SL2_jumpr31_fnew: 1377 case Hexagon::V4_SL2_jumpr31_t: 1378 case Hexagon::V4_SL2_jumpr31_tnew: 1379 case Hexagon::V4_SL2_return: 1380 case Hexagon::V4_SL2_return_f: 1381 case Hexagon::V4_SL2_return_fnew: 1382 case Hexagon::V4_SL2_return_t: 1383 case Hexagon::V4_SL2_return_tnew: 1384 // no operands for these instructions 1385 break; 1386 case Hexagon::V4_SS2_allocframe: 1387 // u 8-4{5_3} 1388 operand = ((inst & 0x1f0) >> 4) << 3; 1389 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1390 break; 1391 case Hexagon::V4_SL1_loadri_io: 1392 // Rd 3-0, Rs 7-4, u 11-8{4_2} 1393 operand = getRegFromSubinstEncoding(inst & 0xf); 1394 Op = MCOperand::createReg(operand); 1395 MI->addOperand(Op); 1396 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1397 Op = MCOperand::createReg(operand); 1398 MI->addOperand(Op); 1399 operand = (inst & 0xf00) >> 6; 1400 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1401 break; 1402 case Hexagon::V4_SL1_loadrub_io: 1403 // Rd 3-0, Rs 7-4, u 11-8 1404 operand = getRegFromSubinstEncoding(inst & 0xf); 1405 Op = MCOperand::createReg(operand); 1406 MI->addOperand(Op); 1407 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1408 Op = MCOperand::createReg(operand); 1409 MI->addOperand(Op); 1410 operand = (inst & 0xf00) >> 8; 1411 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1412 break; 1413 case Hexagon::V4_SL2_loadrb_io: 1414 // Rd 3-0, Rs 7-4, u 10-8 1415 operand = getRegFromSubinstEncoding(inst & 0xf); 1416 Op = MCOperand::createReg(operand); 1417 MI->addOperand(Op); 1418 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1419 Op = MCOperand::createReg(operand); 1420 MI->addOperand(Op); 1421 operand = (inst & 0x700) >> 8; 1422 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1423 break; 1424 case Hexagon::V4_SL2_loadrh_io: 1425 case Hexagon::V4_SL2_loadruh_io: 1426 // Rd 3-0, Rs 7-4, u 10-8{3_1} 1427 operand = getRegFromSubinstEncoding(inst & 0xf); 1428 Op = MCOperand::createReg(operand); 1429 MI->addOperand(Op); 1430 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1431 Op = MCOperand::createReg(operand); 1432 MI->addOperand(Op); 1433 operand = ((inst & 0x700) >> 8) << 1; 1434 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1435 break; 1436 case Hexagon::V4_SL2_loadrd_sp: 1437 // Rdd 2-0, u 7-3{5_3} 1438 operand = getDRegFromSubinstEncoding(inst & 0x7); 1439 Op = MCOperand::createReg(operand); 1440 MI->addOperand(Op); 1441 operand = ((inst & 0x0f8) >> 3) << 3; 1442 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1443 break; 1444 case Hexagon::V4_SL2_loadri_sp: 1445 // Rd 3-0, u 8-4{5_2} 1446 operand = getRegFromSubinstEncoding(inst & 0xf); 1447 Op = MCOperand::createReg(operand); 1448 MI->addOperand(Op); 1449 operand = ((inst & 0x1f0) >> 4) << 2; 1450 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1451 break; 1452 case Hexagon::V4_SA1_addi: 1453 // Rx 3-0 (x2), s7 10-4 1454 operand = getRegFromSubinstEncoding(inst & 0xf); 1455 Op = MCOperand::createReg(operand); 1456 MI->addOperand(Op); 1457 MI->addOperand(Op); 1458 operand = SignExtend64<7>((inst & 0x7f0) >> 4); 1459 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1460 break; 1461 case Hexagon::V4_SA1_addrx: 1462 // Rx 3-0 (x2), Rs 7-4 1463 operand = getRegFromSubinstEncoding(inst & 0xf); 1464 Op = MCOperand::createReg(operand); 1465 MI->addOperand(Op); 1466 MI->addOperand(Op); 1467 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1468 Op = MCOperand::createReg(operand); 1469 MI->addOperand(Op); 1470 case Hexagon::V4_SA1_and1: 1471 case Hexagon::V4_SA1_dec: 1472 case Hexagon::V4_SA1_inc: 1473 case Hexagon::V4_SA1_sxtb: 1474 case Hexagon::V4_SA1_sxth: 1475 case Hexagon::V4_SA1_tfr: 1476 case Hexagon::V4_SA1_zxtb: 1477 case Hexagon::V4_SA1_zxth: 1478 // Rd 3-0, Rs 7-4 1479 operand = getRegFromSubinstEncoding(inst & 0xf); 1480 Op = MCOperand::createReg(operand); 1481 MI->addOperand(Op); 1482 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1483 Op = MCOperand::createReg(operand); 1484 MI->addOperand(Op); 1485 break; 1486 case Hexagon::V4_SA1_addsp: 1487 // Rd 3-0, u 9-4{6_2} 1488 operand = getRegFromSubinstEncoding(inst & 0xf); 1489 Op = MCOperand::createReg(operand); 1490 MI->addOperand(Op); 1491 operand = ((inst & 0x3f0) >> 4) << 2; 1492 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1493 break; 1494 case Hexagon::V4_SA1_seti: 1495 // Rd 3-0, u 9-4 1496 operand = getRegFromSubinstEncoding(inst & 0xf); 1497 Op = MCOperand::createReg(operand); 1498 MI->addOperand(Op); 1499 operand = (inst & 0x3f0) >> 4; 1500 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1501 break; 1502 case Hexagon::V4_SA1_clrf: 1503 case Hexagon::V4_SA1_clrfnew: 1504 case Hexagon::V4_SA1_clrt: 1505 case Hexagon::V4_SA1_clrtnew: 1506 case Hexagon::V4_SA1_setin1: 1507 // Rd 3-0 1508 operand = getRegFromSubinstEncoding(inst & 0xf); 1509 Op = MCOperand::createReg(operand); 1510 MI->addOperand(Op); 1511 break; 1512 case Hexagon::V4_SA1_cmpeqi: 1513 // Rs 7-4, u 1-0 1514 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1515 Op = MCOperand::createReg(operand); 1516 MI->addOperand(Op); 1517 operand = inst & 0x3; 1518 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1519 break; 1520 case Hexagon::V4_SA1_combine0i: 1521 case Hexagon::V4_SA1_combine1i: 1522 case Hexagon::V4_SA1_combine2i: 1523 case Hexagon::V4_SA1_combine3i: 1524 // Rdd 2-0, u 6-5 1525 operand = getDRegFromSubinstEncoding(inst & 0x7); 1526 Op = MCOperand::createReg(operand); 1527 MI->addOperand(Op); 1528 operand = (inst & 0x060) >> 5; 1529 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1530 break; 1531 case Hexagon::V4_SA1_combinerz: 1532 case Hexagon::V4_SA1_combinezr: 1533 // Rdd 2-0, Rs 7-4 1534 operand = getDRegFromSubinstEncoding(inst & 0x7); 1535 Op = MCOperand::createReg(operand); 1536 MI->addOperand(Op); 1537 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1538 Op = MCOperand::createReg(operand); 1539 MI->addOperand(Op); 1540 break; 1541 case Hexagon::V4_SS1_storeb_io: 1542 // Rs 7-4, u 11-8, Rt 3-0 1543 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1544 Op = MCOperand::createReg(operand); 1545 MI->addOperand(Op); 1546 operand = (inst & 0xf00) >> 8; 1547 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1548 operand = getRegFromSubinstEncoding(inst & 0xf); 1549 Op = MCOperand::createReg(operand); 1550 MI->addOperand(Op); 1551 break; 1552 case Hexagon::V4_SS1_storew_io: 1553 // Rs 7-4, u 11-8{4_2}, Rt 3-0 1554 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1555 Op = MCOperand::createReg(operand); 1556 MI->addOperand(Op); 1557 operand = ((inst & 0xf00) >> 8) << 2; 1558 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1559 operand = getRegFromSubinstEncoding(inst & 0xf); 1560 Op = MCOperand::createReg(operand); 1561 MI->addOperand(Op); 1562 break; 1563 case Hexagon::V4_SS2_storebi0: 1564 case Hexagon::V4_SS2_storebi1: 1565 // Rs 7-4, u 3-0 1566 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1567 Op = MCOperand::createReg(operand); 1568 MI->addOperand(Op); 1569 operand = inst & 0xf; 1570 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1571 break; 1572 case Hexagon::V4_SS2_storewi0: 1573 case Hexagon::V4_SS2_storewi1: 1574 // Rs 7-4, u 3-0{4_2} 1575 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1576 Op = MCOperand::createReg(operand); 1577 MI->addOperand(Op); 1578 operand = (inst & 0xf) << 2; 1579 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1580 break; 1581 case Hexagon::V4_SS2_stored_sp: 1582 // s 8-3{6_3}, Rtt 2-0 1583 operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3); 1584 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1585 operand = getDRegFromSubinstEncoding(inst & 0x7); 1586 Op = MCOperand::createReg(operand); 1587 MI->addOperand(Op); 1588 break; 1589 case Hexagon::V4_SS2_storeh_io: 1590 // Rs 7-4, u 10-8{3_1}, Rt 3-0 1591 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1592 Op = MCOperand::createReg(operand); 1593 MI->addOperand(Op); 1594 operand = ((inst & 0x700) >> 8) << 1; 1595 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1596 operand = getRegFromSubinstEncoding(inst & 0xf); 1597 Op = MCOperand::createReg(operand); 1598 MI->addOperand(Op); 1599 break; 1600 case Hexagon::V4_SS2_storew_sp: 1601 // u 8-4{5_2}, Rd 3-0 1602 operand = ((inst & 0x1f0) >> 4) << 2; 1603 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1604 operand = getRegFromSubinstEncoding(inst & 0xf); 1605 Op = MCOperand::createReg(operand); 1606 MI->addOperand(Op); 1607 break; 1608 default: 1609 // don't crash with an invalid subinstruction 1610 // llvm_unreachable("Invalid subinstruction in duplex instruction"); 1611 break; 1612 } 1613 } 1614