1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCTargetDesc.h" 16 #include "MCTargetDesc/HexagonMCInstrInfo.h" 17 #include "MCTargetDesc/HexagonInstPrinter.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrDesc.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/LEB128.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/Support/TargetRegistry.h" 32 33 using namespace llvm; 34 using namespace Hexagon; 35 36 typedef MCDisassembler::DecodeStatus DecodeStatus; 37 38 namespace { 39 /// \brief Hexagon disassembler for all Hexagon platforms. 40 class HexagonDisassembler : public MCDisassembler { 41 public: 42 std::unique_ptr<MCInstrInfo const> const MCII; 43 std::unique_ptr<MCInst *> CurrentBundle; 44 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 45 MCInstrInfo const *MCII) 46 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} 47 48 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 49 ArrayRef<uint8_t> Bytes, uint64_t Address, 50 raw_ostream &VStream, raw_ostream &CStream, 51 bool &Complete) const; 52 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 53 ArrayRef<uint8_t> Bytes, uint64_t Address, 54 raw_ostream &VStream, 55 raw_ostream &CStream) const override; 56 57 void adjustExtendedInstructions(MCInst &MCI, MCInst const &MCB) const; 58 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; 59 }; 60 } 61 62 // Forward declare these because the auto-generated code will reference them. 63 // Definitions are further down. 64 65 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 66 uint64_t Address, 67 const void *Decoder); 68 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 72 uint64_t Address, 73 const void *Decoder); 74 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 81 uint64_t Address, 82 const void *Decoder); 83 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 87 uint64_t Address, 88 const void *Decoder); 89 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn); 97 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, 98 void const *Decoder); 99 100 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 101 raw_ostream &os); 102 103 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg); 104 105 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 106 uint64_t Address, const void *Decoder); 107 static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 112 const void *Decoder); 113 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 116 const void *Decoder); 117 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 118 const void *Decoder); 119 static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 122 const void *Decoder); 123 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 128 const void *Decoder); 129 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 134 const void *Decoder); 135 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 136 const void *Decoder); 137 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 138 const void *Decoder); 139 140 #include "HexagonGenDisassemblerTables.inc" 141 142 static MCDisassembler *createHexagonDisassembler(const Target &T, 143 const MCSubtargetInfo &STI, 144 MCContext &Ctx) { 145 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 146 } 147 148 extern "C" void LLVMInitializeHexagonDisassembler() { 149 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 150 createHexagonDisassembler); 151 } 152 153 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 154 ArrayRef<uint8_t> Bytes, 155 uint64_t Address, 156 raw_ostream &os, 157 raw_ostream &cs) const { 158 DecodeStatus Result = DecodeStatus::Success; 159 bool Complete = false; 160 Size = 0; 161 162 *CurrentBundle = &MI; 163 MI = HexagonMCInstrInfo::createBundle(); 164 while (Result == Success && Complete == false) { 165 if (Bytes.size() < HEXAGON_INSTR_SIZE) 166 return MCDisassembler::Fail; 167 MCInst *Inst = new (getContext()) MCInst; 168 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 169 MI.addOperand(MCOperand::createInst(Inst)); 170 Size += HEXAGON_INSTR_SIZE; 171 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 172 } 173 if(Result == MCDisassembler::Fail) 174 return Result; 175 HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo()); 176 if(!Checker.check()) 177 return MCDisassembler::Fail; 178 return MCDisassembler::Success; 179 } 180 181 namespace { 182 HexagonDisassembler const &disassembler(void const *Decoder) { 183 return *static_cast<HexagonDisassembler const *>(Decoder); 184 } 185 MCContext &contextFromDecoder(void const *Decoder) { 186 return disassembler(Decoder).getContext(); 187 } 188 } 189 190 DecodeStatus HexagonDisassembler::getSingleInstruction( 191 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 192 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 193 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 194 195 uint32_t Instruction = 196 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 197 198 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 199 if ((Instruction & HexagonII::INST_PARSE_MASK) == 200 HexagonII::INST_PARSE_LOOP_END) { 201 if (BundleSize == 0) 202 HexagonMCInstrInfo::setInnerLoop(MCB); 203 else if (BundleSize == 1) 204 HexagonMCInstrInfo::setOuterLoop(MCB); 205 else 206 return DecodeStatus::Fail; 207 } 208 209 DecodeStatus Result = DecodeStatus::Success; 210 if ((Instruction & HexagonII::INST_PARSE_MASK) == 211 HexagonII::INST_PARSE_DUPLEX) { 212 // Determine the instruction class of each instruction in the duplex. 213 unsigned duplexIClass, IClassLow, IClassHigh; 214 215 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 216 switch (duplexIClass) { 217 default: 218 return MCDisassembler::Fail; 219 case 0: 220 IClassLow = HexagonII::HSIG_L1; 221 IClassHigh = HexagonII::HSIG_L1; 222 break; 223 case 1: 224 IClassLow = HexagonII::HSIG_L2; 225 IClassHigh = HexagonII::HSIG_L1; 226 break; 227 case 2: 228 IClassLow = HexagonII::HSIG_L2; 229 IClassHigh = HexagonII::HSIG_L2; 230 break; 231 case 3: 232 IClassLow = HexagonII::HSIG_A; 233 IClassHigh = HexagonII::HSIG_A; 234 break; 235 case 4: 236 IClassLow = HexagonII::HSIG_L1; 237 IClassHigh = HexagonII::HSIG_A; 238 break; 239 case 5: 240 IClassLow = HexagonII::HSIG_L2; 241 IClassHigh = HexagonII::HSIG_A; 242 break; 243 case 6: 244 IClassLow = HexagonII::HSIG_S1; 245 IClassHigh = HexagonII::HSIG_A; 246 break; 247 case 7: 248 IClassLow = HexagonII::HSIG_S2; 249 IClassHigh = HexagonII::HSIG_A; 250 break; 251 case 8: 252 IClassLow = HexagonII::HSIG_S1; 253 IClassHigh = HexagonII::HSIG_L1; 254 break; 255 case 9: 256 IClassLow = HexagonII::HSIG_S1; 257 IClassHigh = HexagonII::HSIG_L2; 258 break; 259 case 10: 260 IClassLow = HexagonII::HSIG_S1; 261 IClassHigh = HexagonII::HSIG_S1; 262 break; 263 case 11: 264 IClassLow = HexagonII::HSIG_S2; 265 IClassHigh = HexagonII::HSIG_S1; 266 break; 267 case 12: 268 IClassLow = HexagonII::HSIG_S2; 269 IClassHigh = HexagonII::HSIG_L1; 270 break; 271 case 13: 272 IClassLow = HexagonII::HSIG_S2; 273 IClassHigh = HexagonII::HSIG_L2; 274 break; 275 case 14: 276 IClassLow = HexagonII::HSIG_S2; 277 IClassHigh = HexagonII::HSIG_S2; 278 break; 279 } 280 281 // Set the MCInst to be a duplex instruction. Which one doesn't matter. 282 MI.setOpcode(Hexagon::DuplexIClass0); 283 284 // Decode each instruction in the duplex. 285 // Create an MCInst for each instruction. 286 unsigned instLow = Instruction & 0x1fff; 287 unsigned instHigh = (Instruction >> 16) & 0x1fff; 288 unsigned opLow; 289 if (GetSubinstOpcode(IClassLow, instLow, opLow, os) != 290 MCDisassembler::Success) 291 return MCDisassembler::Fail; 292 unsigned opHigh; 293 if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) != 294 MCDisassembler::Success) 295 return MCDisassembler::Fail; 296 MCInst *MILow = new (getContext()) MCInst; 297 MILow->setOpcode(opLow); 298 MCInst *MIHigh = new (getContext()) MCInst; 299 MIHigh->setOpcode(opHigh); 300 addSubinstOperands(MILow, opLow, instLow); 301 addSubinstOperands(MIHigh, opHigh, instHigh); 302 // see ConvertToSubInst() in 303 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 304 305 // Add the duplex instruction MCInsts as operands to the passed in MCInst. 306 MCOperand OPLow = MCOperand::createInst(MILow); 307 MCOperand OPHigh = MCOperand::createInst(MIHigh); 308 MI.addOperand(OPLow); 309 MI.addOperand(OPHigh); 310 Complete = true; 311 } else { 312 if ((Instruction & HexagonII::INST_PARSE_MASK) == 313 HexagonII::INST_PARSE_PACKET_END) 314 Complete = true; 315 // Calling the auto-generated decoder function. 316 Result = 317 decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); 318 319 // If a, "standard" insn isn't found check special cases. 320 if (MCDisassembler::Success != Result || 321 MI.getOpcode() == Hexagon::A4_ext) { 322 Result = decodeImmext(MI, Instruction, this); 323 if (MCDisassembler::Success != Result) { 324 Result = decodeSpecial(MI, Instruction); 325 } 326 } else { 327 // If the instruction is a compound instruction, register values will 328 // follow the duplex model, so the register values in the MCInst are 329 // incorrect. If the instruction is a compound, loop through the 330 // operands and change registers appropriately. 331 if (llvm::HexagonMCInstrInfo::getType(*MCII, MI) == 332 HexagonII::TypeCOMPOUND) { 333 for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) { 334 if (i->isReg()) { 335 unsigned reg = i->getReg() - Hexagon::R0; 336 i->setReg(getRegFromSubinstEncoding(reg)); 337 } 338 } 339 } 340 } 341 } 342 343 switch(MI.getOpcode()) { 344 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 345 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 346 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 347 case Hexagon::J4_cmpeqn1_fp0_jump_t: 348 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 349 case Hexagon::J4_cmpeqn1_fp1_jump_t: 350 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 351 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 352 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 353 case Hexagon::J4_cmpeqn1_tp0_jump_t: 354 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 355 case Hexagon::J4_cmpeqn1_tp1_jump_t: 356 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 357 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 358 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 359 case Hexagon::J4_cmpgtn1_fp0_jump_t: 360 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 361 case Hexagon::J4_cmpgtn1_fp1_jump_t: 362 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 363 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 364 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 365 case Hexagon::J4_cmpgtn1_tp0_jump_t: 366 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 367 case Hexagon::J4_cmpgtn1_tp1_jump_t: 368 MI.insert(MI.begin() + 1, MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 369 break; 370 default: 371 break; 372 } 373 374 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 375 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 376 MCOperand &MCO = MI.getOperand(OpIndex); 377 assert(MCO.isReg() && "New value consumers must be registers"); 378 unsigned Register = 379 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 380 if ((Register & 0x6) == 0) 381 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 382 return MCDisassembler::Fail; 383 unsigned Lookback = (Register & 0x6) >> 1; 384 unsigned Offset = 1; 385 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 386 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 387 auto i = Instructions.end() - 1; 388 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 389 if (i == n) 390 // Couldn't find producer 391 return MCDisassembler::Fail; 392 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) 393 // Skip scalars when calculating distances for vectors 394 ++Lookback; 395 if (HexagonMCInstrInfo::isImmext(*i->getInst())) 396 ++Lookback; 397 if (Offset == Lookback) 398 break; 399 } 400 auto const &Inst = *i->getInst(); 401 bool SubregBit = (Register & 0x1) != 0; 402 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 403 // If subreg bit is set we're selecting the second produced newvalue 404 unsigned Producer = 405 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 406 assert(Producer != Hexagon::NoRegister); 407 MCO.setReg(Producer); 408 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 409 unsigned Producer = 410 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 411 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 412 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 413 else if (SubregBit) 414 // Hexagon PRM 10.11 New-value operands 415 // Nt[0] is reserved and should always be encoded as zero. 416 return MCDisassembler::Fail; 417 assert(Producer != Hexagon::NoRegister); 418 MCO.setReg(Producer); 419 } else 420 return MCDisassembler::Fail; 421 } 422 423 adjustExtendedInstructions(MI, MCB); 424 MCInst const *Extender = 425 HexagonMCInstrInfo::extenderForIndex(MCB, 426 HexagonMCInstrInfo::bundleSize(MCB)); 427 if(Extender != nullptr) { 428 MCInst const & Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ? 429 *MI.getOperand(1).getInst() : MI; 430 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 431 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 432 return MCDisassembler::Fail; 433 } 434 return Result; 435 } 436 437 void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI, 438 MCInst const &MCB) const { 439 if (!HexagonMCInstrInfo::hasExtenderForIndex( 440 MCB, HexagonMCInstrInfo::bundleSize(MCB))) { 441 unsigned opcode; 442 // This code is used by the disassembler to disambiguate between GP 443 // relative and absolute addressing instructions since they both have 444 // same encoding bits. However, an absolute addressing instruction must 445 // follow an immediate extender. Disassembler alwaus select absolute 446 // addressing instructions first and uses this code to change them into 447 // GP relative instruction in the absence of the corresponding immediate 448 // extender. 449 switch (MCI.getOpcode()) { 450 case Hexagon::PS_storerbabs: 451 opcode = Hexagon::S2_storerbgp; 452 break; 453 case Hexagon::PS_storerhabs: 454 opcode = Hexagon::S2_storerhgp; 455 break; 456 case Hexagon::PS_storerfabs: 457 opcode = Hexagon::S2_storerfgp; 458 break; 459 case Hexagon::PS_storeriabs: 460 opcode = Hexagon::S2_storerigp; 461 break; 462 case Hexagon::PS_storerbnewabs: 463 opcode = Hexagon::S2_storerbnewgp; 464 break; 465 case Hexagon::PS_storerhnewabs: 466 opcode = Hexagon::S2_storerhnewgp; 467 break; 468 case Hexagon::PS_storerinewabs: 469 opcode = Hexagon::S2_storerinewgp; 470 break; 471 case Hexagon::PS_storerdabs: 472 opcode = Hexagon::S2_storerdgp; 473 break; 474 case Hexagon::PS_loadrbabs: 475 opcode = Hexagon::L2_loadrbgp; 476 break; 477 case Hexagon::PS_loadrubabs: 478 opcode = Hexagon::L2_loadrubgp; 479 break; 480 case Hexagon::PS_loadrhabs: 481 opcode = Hexagon::L2_loadrhgp; 482 break; 483 case Hexagon::PS_loadruhabs: 484 opcode = Hexagon::L2_loadruhgp; 485 break; 486 case Hexagon::PS_loadriabs: 487 opcode = Hexagon::L2_loadrigp; 488 break; 489 case Hexagon::PS_loadrdabs: 490 opcode = Hexagon::L2_loadrdgp; 491 break; 492 default: 493 opcode = MCI.getOpcode(); 494 } 495 MCI.setOpcode(opcode); 496 } 497 } 498 499 namespace llvm { 500 extern const MCInstrDesc HexagonInsts[]; 501 } 502 503 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 504 ArrayRef<MCPhysReg> Table) { 505 if (RegNo < Table.size()) { 506 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 507 return MCDisassembler::Success; 508 } 509 510 return MCDisassembler::Fail; 511 } 512 513 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 514 uint64_t Address, 515 const void *Decoder) { 516 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 517 } 518 519 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 520 uint64_t Address, 521 const void *Decoder) { 522 static const MCPhysReg IntRegDecoderTable[] = { 523 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 524 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 525 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 526 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 527 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 528 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 529 Hexagon::R30, Hexagon::R31}; 530 531 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 532 } 533 534 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 535 uint64_t /*Address*/, 536 const void *Decoder) { 537 static const MCPhysReg VecRegDecoderTable[] = { 538 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 539 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 540 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 541 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 542 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 543 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 544 Hexagon::V30, Hexagon::V31}; 545 546 return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable); 547 } 548 549 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 550 uint64_t /*Address*/, 551 const void *Decoder) { 552 static const MCPhysReg DoubleRegDecoderTable[] = { 553 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 554 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 555 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 556 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 557 558 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 559 } 560 561 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 562 uint64_t /*Address*/, 563 const void *Decoder) { 564 static const MCPhysReg VecDblRegDecoderTable[] = { 565 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 566 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 567 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 568 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 569 570 return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable)); 571 } 572 573 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 574 uint64_t /*Address*/, 575 const void *Decoder) { 576 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 577 Hexagon::P2, Hexagon::P3}; 578 579 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 580 } 581 582 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 583 uint64_t /*Address*/, 584 const void *Decoder) { 585 static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 586 Hexagon::Q2, Hexagon::Q3}; 587 588 return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable); 589 } 590 591 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 592 uint64_t /*Address*/, 593 const void *Decoder) { 594 static const MCPhysReg CtrlRegDecoderTable[] = { 595 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, 596 Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7, 597 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, 598 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC 599 }; 600 601 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 602 return MCDisassembler::Fail; 603 604 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister) 605 return MCDisassembler::Fail; 606 607 unsigned Register = CtrlRegDecoderTable[RegNo]; 608 Inst.addOperand(MCOperand::createReg(Register)); 609 return MCDisassembler::Success; 610 } 611 612 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 613 uint64_t /*Address*/, 614 const void *Decoder) { 615 static const MCPhysReg CtrlReg64DecoderTable[] = { 616 Hexagon::C1_0, Hexagon::NoRegister, 617 Hexagon::C3_2, Hexagon::NoRegister, 618 Hexagon::C7_6, Hexagon::NoRegister, 619 Hexagon::C9_8, Hexagon::NoRegister, 620 Hexagon::C11_10, Hexagon::NoRegister, 621 Hexagon::CS, Hexagon::NoRegister, 622 Hexagon::UPC, Hexagon::NoRegister 623 }; 624 625 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 626 return MCDisassembler::Fail; 627 628 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister) 629 return MCDisassembler::Fail; 630 631 unsigned Register = CtrlReg64DecoderTable[RegNo]; 632 Inst.addOperand(MCOperand::createReg(Register)); 633 return MCDisassembler::Success; 634 } 635 636 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 637 uint64_t /*Address*/, 638 const void *Decoder) { 639 unsigned Register = 0; 640 switch (RegNo) { 641 case 0: 642 Register = Hexagon::M0; 643 break; 644 case 1: 645 Register = Hexagon::M1; 646 break; 647 default: 648 return MCDisassembler::Fail; 649 } 650 Inst.addOperand(MCOperand::createReg(Register)); 651 return MCDisassembler::Success; 652 } 653 654 namespace { 655 uint32_t fullValue(MCInstrInfo const &MCII, 656 MCInst &MCB, 657 MCInst &MI, 658 int64_t Value) { 659 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 660 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 661 if(!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 662 return Value; 663 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 664 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 665 int64_t Bits; 666 bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); 667 assert(Success);(void)Success; 668 uint32_t Upper26 = static_cast<uint32_t>(Bits); 669 uint32_t Operand = Upper26 | Lower6; 670 return Operand; 671 } 672 template <size_t T> 673 void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 674 HexagonDisassembler const &Disassembler = disassembler(Decoder); 675 int64_t FullValue = fullValue(*Disassembler.MCII, 676 **Disassembler.CurrentBundle, 677 MI, SignExtend64<T>(tmp)); 678 int64_t Extended = SignExtend64<32>(FullValue); 679 HexagonMCInstrInfo::addConstant(MI, Extended, 680 Disassembler.getContext()); 681 } 682 } 683 684 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 685 uint64_t /*Address*/, 686 const void *Decoder) { 687 HexagonDisassembler const &Disassembler = disassembler(Decoder); 688 int64_t FullValue = fullValue(*Disassembler.MCII, 689 **Disassembler.CurrentBundle, 690 MI, tmp); 691 assert(FullValue >= 0 && "Negative in unsigned decoder"); 692 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 693 return MCDisassembler::Success; 694 } 695 696 static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, 697 uint64_t /*Address*/, const void *Decoder) { 698 signedDecoder<16>(MI, tmp, Decoder); 699 return MCDisassembler::Success; 700 } 701 702 static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, 703 uint64_t /*Address*/, const void *Decoder) { 704 signedDecoder<12>(MI, tmp, Decoder); 705 return MCDisassembler::Success; 706 } 707 708 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, 709 uint64_t /*Address*/, const void *Decoder) { 710 signedDecoder<11>(MI, tmp, Decoder); 711 return MCDisassembler::Success; 712 } 713 714 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, 715 uint64_t /*Address*/, const void *Decoder) { 716 HexagonMCInstrInfo::addConstant(MI, SignExtend64<12>(tmp), contextFromDecoder(Decoder)); 717 return MCDisassembler::Success; 718 } 719 720 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, 721 uint64_t /*Address*/, const void *Decoder) { 722 signedDecoder<13>(MI, tmp, Decoder); 723 return MCDisassembler::Success; 724 } 725 726 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, 727 uint64_t /*Address*/, const void *Decoder) { 728 signedDecoder<14>(MI, tmp, Decoder); 729 return MCDisassembler::Success; 730 } 731 732 static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, 733 uint64_t /*Address*/, const void *Decoder) { 734 signedDecoder<10>(MI, tmp, Decoder); 735 return MCDisassembler::Success; 736 } 737 738 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, 739 const void *Decoder) { 740 signedDecoder<8>(MI, tmp, Decoder); 741 return MCDisassembler::Success; 742 } 743 744 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, 745 uint64_t /*Address*/, const void *Decoder) { 746 signedDecoder<6>(MI, tmp, Decoder); 747 return MCDisassembler::Success; 748 } 749 750 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, 751 uint64_t /*Address*/, const void *Decoder) { 752 signedDecoder<4>(MI, tmp, Decoder); 753 return MCDisassembler::Success; 754 } 755 756 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, 757 uint64_t /*Address*/, const void *Decoder) { 758 signedDecoder<5>(MI, tmp, Decoder); 759 return MCDisassembler::Success; 760 } 761 762 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, 763 uint64_t /*Address*/, const void *Decoder) { 764 signedDecoder<6>(MI, tmp, Decoder); 765 return MCDisassembler::Success; 766 } 767 768 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, 769 uint64_t /*Address*/, const void *Decoder) { 770 signedDecoder<7>(MI, tmp, Decoder); 771 return MCDisassembler::Success; 772 } 773 774 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, 775 uint64_t /*Address*/, const void *Decoder) { 776 signedDecoder<10>(MI, tmp, Decoder); 777 return MCDisassembler::Success; 778 } 779 780 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, 781 uint64_t /*Address*/, const void *Decoder) { 782 signedDecoder<19>(MI, tmp, Decoder); 783 return MCDisassembler::Success; 784 } 785 786 // custom decoder for various jump/call immediates 787 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 788 const void *Decoder) { 789 HexagonDisassembler const &Disassembler = disassembler(Decoder); 790 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 791 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 792 if (Bits == 0) 793 Bits = 15; 794 uint32_t FullValue = fullValue(*Disassembler.MCII, 795 **Disassembler.CurrentBundle, 796 MI, SignExtend64(tmp, Bits)); 797 int64_t Extended = SignExtend64<32>(FullValue) + Address; 798 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 799 0, 4)) 800 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 801 return MCDisassembler::Success; 802 } 803 804 // Addressing mode dependent load store opcode map. 805 // - If an insn is preceded by an extender the address is absolute. 806 // - memw(##symbol) = r0 807 // - If an insn is not preceded by an extender the address is GP relative. 808 // - memw(gp + #symbol) = r0 809 // Please note that the instructions must be ordered in the descending order 810 // of their opcode. 811 // HexagonII::INST_ICLASS_ST 812 static const unsigned int StoreConditionalOpcodeData[][2] = { 813 {S4_pstorerdfnew_abs, 0xafc02084}, 814 {S4_pstorerdtnew_abs, 0xafc02080}, 815 {S4_pstorerdf_abs, 0xafc00084}, 816 {S4_pstorerdt_abs, 0xafc00080}, 817 {S4_pstorerinewfnew_abs, 0xafa03084}, 818 {S4_pstorerinewtnew_abs, 0xafa03080}, 819 {S4_pstorerhnewfnew_abs, 0xafa02884}, 820 {S4_pstorerhnewtnew_abs, 0xafa02880}, 821 {S4_pstorerbnewfnew_abs, 0xafa02084}, 822 {S4_pstorerbnewtnew_abs, 0xafa02080}, 823 {S4_pstorerinewf_abs, 0xafa01084}, 824 {S4_pstorerinewt_abs, 0xafa01080}, 825 {S4_pstorerhnewf_abs, 0xafa00884}, 826 {S4_pstorerhnewt_abs, 0xafa00880}, 827 {S4_pstorerbnewf_abs, 0xafa00084}, 828 {S4_pstorerbnewt_abs, 0xafa00080}, 829 {S4_pstorerifnew_abs, 0xaf802084}, 830 {S4_pstoreritnew_abs, 0xaf802080}, 831 {S4_pstorerif_abs, 0xaf800084}, 832 {S4_pstorerit_abs, 0xaf800080}, 833 {S4_pstorerhfnew_abs, 0xaf402084}, 834 {S4_pstorerhtnew_abs, 0xaf402080}, 835 {S4_pstorerhf_abs, 0xaf400084}, 836 {S4_pstorerht_abs, 0xaf400080}, 837 {S4_pstorerbfnew_abs, 0xaf002084}, 838 {S4_pstorerbtnew_abs, 0xaf002080}, 839 {S4_pstorerbf_abs, 0xaf000084}, 840 {S4_pstorerbt_abs, 0xaf000080}}; 841 // HexagonII::INST_ICLASS_LD 842 843 // HexagonII::INST_ICLASS_LD_ST_2 844 static unsigned int LoadStoreOpcodeData[][2] = {{PS_loadrdabs, 0x49c00000}, 845 {PS_loadriabs, 0x49800000}, 846 {PS_loadruhabs, 0x49600000}, 847 {PS_loadrhabs, 0x49400000}, 848 {PS_loadrubabs, 0x49200000}, 849 {PS_loadrbabs, 0x49000000}, 850 {PS_storerdabs, 0x48c00000}, 851 {PS_storerinewabs, 0x48a01000}, 852 {PS_storerhnewabs, 0x48a00800}, 853 {PS_storerbnewabs, 0x48a00000}, 854 {PS_storeriabs, 0x48800000}, 855 {PS_storerfabs, 0x48600000}, 856 {PS_storerhabs, 0x48400000}, 857 {PS_storerbabs, 0x48000000}}; 858 static const size_t NumCondS = array_lengthof(StoreConditionalOpcodeData); 859 static const size_t NumLS = array_lengthof(LoadStoreOpcodeData); 860 861 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) { 862 863 unsigned MachineOpcode = 0; 864 unsigned LLVMOpcode = 0; 865 866 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_ST) { 867 for (size_t i = 0; i < NumCondS; ++i) { 868 if ((insn & StoreConditionalOpcodeData[i][1]) == 869 StoreConditionalOpcodeData[i][1]) { 870 MachineOpcode = StoreConditionalOpcodeData[i][1]; 871 LLVMOpcode = StoreConditionalOpcodeData[i][0]; 872 break; 873 } 874 } 875 } 876 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_LD_ST_2) { 877 for (size_t i = 0; i < NumLS; ++i) { 878 if ((insn & LoadStoreOpcodeData[i][1]) == LoadStoreOpcodeData[i][1]) { 879 MachineOpcode = LoadStoreOpcodeData[i][1]; 880 LLVMOpcode = LoadStoreOpcodeData[i][0]; 881 break; 882 } 883 } 884 } 885 886 if (MachineOpcode) { 887 unsigned Value = 0; 888 unsigned shift = 0; 889 MI.setOpcode(LLVMOpcode); 890 // Remove the parse bits from the insn. 891 insn &= ~HexagonII::INST_PARSE_MASK; 892 893 switch (LLVMOpcode) { 894 default: 895 return MCDisassembler::Fail; 896 break; 897 898 case Hexagon::S4_pstorerdf_abs: 899 case Hexagon::S4_pstorerdt_abs: 900 case Hexagon::S4_pstorerdfnew_abs: 901 case Hexagon::S4_pstorerdtnew_abs: { 902 // op: Pv 903 Value = insn & UINT64_C(3); 904 DecodePredRegsRegisterClass(MI, Value, 0, 0); 905 // op: u6 906 Value = (insn >> 12) & UINT64_C(48); 907 Value |= (insn >> 3) & UINT64_C(15); 908 MI.addOperand(MCOperand::createImm(Value)); 909 // op: Rtt 910 Value = (insn >> 8) & UINT64_C(31); 911 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 912 break; 913 } 914 915 case Hexagon::S4_pstorerbnewf_abs: 916 case Hexagon::S4_pstorerbnewt_abs: 917 case Hexagon::S4_pstorerbnewfnew_abs: 918 case Hexagon::S4_pstorerbnewtnew_abs: 919 case Hexagon::S4_pstorerhnewf_abs: 920 case Hexagon::S4_pstorerhnewt_abs: 921 case Hexagon::S4_pstorerhnewfnew_abs: 922 case Hexagon::S4_pstorerhnewtnew_abs: 923 case Hexagon::S4_pstorerinewf_abs: 924 case Hexagon::S4_pstorerinewt_abs: 925 case Hexagon::S4_pstorerinewfnew_abs: 926 case Hexagon::S4_pstorerinewtnew_abs: { 927 // op: Pv 928 Value = insn & UINT64_C(3); 929 DecodePredRegsRegisterClass(MI, Value, 0, 0); 930 // op: u6 931 Value = (insn >> 12) & UINT64_C(48); 932 Value |= (insn >> 3) & UINT64_C(15); 933 MI.addOperand(MCOperand::createImm(Value)); 934 // op: Nt 935 Value = (insn >> 8) & UINT64_C(7); 936 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 937 break; 938 } 939 940 case Hexagon::S4_pstorerbf_abs: 941 case Hexagon::S4_pstorerbt_abs: 942 case Hexagon::S4_pstorerbfnew_abs: 943 case Hexagon::S4_pstorerbtnew_abs: 944 case Hexagon::S4_pstorerhf_abs: 945 case Hexagon::S4_pstorerht_abs: 946 case Hexagon::S4_pstorerhfnew_abs: 947 case Hexagon::S4_pstorerhtnew_abs: 948 case Hexagon::S4_pstorerif_abs: 949 case Hexagon::S4_pstorerit_abs: 950 case Hexagon::S4_pstorerifnew_abs: 951 case Hexagon::S4_pstoreritnew_abs: { 952 // op: Pv 953 Value = insn & UINT64_C(3); 954 DecodePredRegsRegisterClass(MI, Value, 0, 0); 955 // op: u6 956 Value = (insn >> 12) & UINT64_C(48); 957 Value |= (insn >> 3) & UINT64_C(15); 958 MI.addOperand(MCOperand::createImm(Value)); 959 // op: Rt 960 Value = (insn >> 8) & UINT64_C(31); 961 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 962 break; 963 } 964 965 case Hexagon::L4_ploadrdf_abs: 966 case Hexagon::L4_ploadrdt_abs: 967 case Hexagon::L4_ploadrdfnew_abs: 968 case Hexagon::L4_ploadrdtnew_abs: { 969 // op: Rdd 970 Value = insn & UINT64_C(31); 971 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 972 // op: Pt 973 Value = ((insn >> 9) & UINT64_C(3)); 974 DecodePredRegsRegisterClass(MI, Value, 0, 0); 975 // op: u6 976 Value = ((insn >> 15) & UINT64_C(62)); 977 Value |= ((insn >> 8) & UINT64_C(1)); 978 MI.addOperand(MCOperand::createImm(Value)); 979 break; 980 } 981 982 case Hexagon::L4_ploadrbf_abs: 983 case Hexagon::L4_ploadrbt_abs: 984 case Hexagon::L4_ploadrbfnew_abs: 985 case Hexagon::L4_ploadrbtnew_abs: 986 case Hexagon::L4_ploadrhf_abs: 987 case Hexagon::L4_ploadrht_abs: 988 case Hexagon::L4_ploadrhfnew_abs: 989 case Hexagon::L4_ploadrhtnew_abs: 990 case Hexagon::L4_ploadrubf_abs: 991 case Hexagon::L4_ploadrubt_abs: 992 case Hexagon::L4_ploadrubfnew_abs: 993 case Hexagon::L4_ploadrubtnew_abs: 994 case Hexagon::L4_ploadruhf_abs: 995 case Hexagon::L4_ploadruht_abs: 996 case Hexagon::L4_ploadruhfnew_abs: 997 case Hexagon::L4_ploadruhtnew_abs: 998 case Hexagon::L4_ploadrif_abs: 999 case Hexagon::L4_ploadrit_abs: 1000 case Hexagon::L4_ploadrifnew_abs: 1001 case Hexagon::L4_ploadritnew_abs: 1002 // op: Rd 1003 Value = insn & UINT64_C(31); 1004 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1005 // op: Pt 1006 Value = (insn >> 9) & UINT64_C(3); 1007 DecodePredRegsRegisterClass(MI, Value, 0, 0); 1008 // op: u6 1009 Value = (insn >> 15) & UINT64_C(62); 1010 Value |= (insn >> 8) & UINT64_C(1); 1011 MI.addOperand(MCOperand::createImm(Value)); 1012 break; 1013 1014 // op: g16_2 1015 case (Hexagon::PS_loadriabs): 1016 ++shift; 1017 // op: g16_1 1018 case Hexagon::PS_loadrhabs: 1019 case Hexagon::PS_loadruhabs: 1020 ++shift; 1021 // op: g16_0 1022 case Hexagon::PS_loadrbabs: 1023 case Hexagon::PS_loadrubabs: { 1024 // op: Rd 1025 Value |= insn & UINT64_C(31); 1026 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1027 Value = (insn >> 11) & UINT64_C(49152); 1028 Value |= (insn >> 7) & UINT64_C(15872); 1029 Value |= (insn >> 5) & UINT64_C(511); 1030 MI.addOperand(MCOperand::createImm(Value << shift)); 1031 break; 1032 } 1033 1034 case Hexagon::PS_loadrdabs: { 1035 Value = insn & UINT64_C(31); 1036 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 1037 Value = (insn >> 11) & UINT64_C(49152); 1038 Value |= (insn >> 7) & UINT64_C(15872); 1039 Value |= (insn >> 5) & UINT64_C(511); 1040 MI.addOperand(MCOperand::createImm(Value << 3)); 1041 break; 1042 } 1043 1044 case Hexagon::PS_storerdabs: { 1045 // op: g16_3 1046 Value = (insn >> 11) & UINT64_C(49152); 1047 Value |= (insn >> 7) & UINT64_C(15872); 1048 Value |= (insn >> 5) & UINT64_C(256); 1049 Value |= insn & UINT64_C(255); 1050 MI.addOperand(MCOperand::createImm(Value << 3)); 1051 // op: Rtt 1052 Value = (insn >> 8) & UINT64_C(31); 1053 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 1054 break; 1055 } 1056 1057 // op: g16_2 1058 case Hexagon::PS_storerinewabs: 1059 ++shift; 1060 // op: g16_1 1061 case Hexagon::PS_storerhnewabs: 1062 ++shift; 1063 // op: g16_0 1064 case Hexagon::PS_storerbnewabs: { 1065 Value = (insn >> 11) & UINT64_C(49152); 1066 Value |= (insn >> 7) & UINT64_C(15872); 1067 Value |= (insn >> 5) & UINT64_C(256); 1068 Value |= insn & UINT64_C(255); 1069 MI.addOperand(MCOperand::createImm(Value << shift)); 1070 // op: Nt 1071 Value = (insn >> 8) & UINT64_C(7); 1072 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1073 break; 1074 } 1075 1076 // op: g16_2 1077 case Hexagon::PS_storeriabs: 1078 ++shift; 1079 // op: g16_1 1080 case Hexagon::PS_storerhabs: 1081 case Hexagon::PS_storerfabs: 1082 ++shift; 1083 // op: g16_0 1084 case Hexagon::PS_storerbabs: { 1085 Value = (insn >> 11) & UINT64_C(49152); 1086 Value |= (insn >> 7) & UINT64_C(15872); 1087 Value |= (insn >> 5) & UINT64_C(256); 1088 Value |= insn & UINT64_C(255); 1089 MI.addOperand(MCOperand::createImm(Value << shift)); 1090 // op: Rt 1091 Value = (insn >> 8) & UINT64_C(31); 1092 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1093 break; 1094 } 1095 } 1096 return MCDisassembler::Success; 1097 } 1098 return MCDisassembler::Fail; 1099 } 1100 1101 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, 1102 void const *Decoder) { 1103 1104 // Instruction Class for a constant a extender: bits 31:28 = 0x0000 1105 if ((~insn & 0xf0000000) == 0xf0000000) { 1106 unsigned Value; 1107 // 27:16 High 12 bits of 26-bit extender. 1108 Value = (insn & 0x0fff0000) << 4; 1109 // 13:0 Low 14 bits of 26-bit extender. 1110 Value |= ((insn & 0x3fff) << 6); 1111 MI.setOpcode(Hexagon::A4_ext); 1112 HexagonMCInstrInfo::addConstant(MI, Value, contextFromDecoder(Decoder)); 1113 return MCDisassembler::Success; 1114 } 1115 return MCDisassembler::Fail; 1116 } 1117 1118 // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td 1119 enum subInstBinaryValues { 1120 SA1_addi_BITS = 0x0000, 1121 SA1_addi_MASK = 0x1800, 1122 SA1_addrx_BITS = 0x1800, 1123 SA1_addrx_MASK = 0x1f00, 1124 SA1_addsp_BITS = 0x0c00, 1125 SA1_addsp_MASK = 0x1c00, 1126 SA1_and1_BITS = 0x1200, 1127 SA1_and1_MASK = 0x1f00, 1128 SA1_clrf_BITS = 0x1a70, 1129 SA1_clrf_MASK = 0x1e70, 1130 SA1_clrfnew_BITS = 0x1a50, 1131 SA1_clrfnew_MASK = 0x1e70, 1132 SA1_clrt_BITS = 0x1a60, 1133 SA1_clrt_MASK = 0x1e70, 1134 SA1_clrtnew_BITS = 0x1a40, 1135 SA1_clrtnew_MASK = 0x1e70, 1136 SA1_cmpeqi_BITS = 0x1900, 1137 SA1_cmpeqi_MASK = 0x1f00, 1138 SA1_combine0i_BITS = 0x1c00, 1139 SA1_combine0i_MASK = 0x1d18, 1140 SA1_combine1i_BITS = 0x1c08, 1141 SA1_combine1i_MASK = 0x1d18, 1142 SA1_combine2i_BITS = 0x1c10, 1143 SA1_combine2i_MASK = 0x1d18, 1144 SA1_combine3i_BITS = 0x1c18, 1145 SA1_combine3i_MASK = 0x1d18, 1146 SA1_combinerz_BITS = 0x1d08, 1147 SA1_combinerz_MASK = 0x1d08, 1148 SA1_combinezr_BITS = 0x1d00, 1149 SA1_combinezr_MASK = 0x1d08, 1150 SA1_dec_BITS = 0x1300, 1151 SA1_dec_MASK = 0x1f00, 1152 SA1_inc_BITS = 0x1100, 1153 SA1_inc_MASK = 0x1f00, 1154 SA1_seti_BITS = 0x0800, 1155 SA1_seti_MASK = 0x1c00, 1156 SA1_setin1_BITS = 0x1a00, 1157 SA1_setin1_MASK = 0x1e40, 1158 SA1_sxtb_BITS = 0x1500, 1159 SA1_sxtb_MASK = 0x1f00, 1160 SA1_sxth_BITS = 0x1400, 1161 SA1_sxth_MASK = 0x1f00, 1162 SA1_tfr_BITS = 0x1000, 1163 SA1_tfr_MASK = 0x1f00, 1164 SA1_zxtb_BITS = 0x1700, 1165 SA1_zxtb_MASK = 0x1f00, 1166 SA1_zxth_BITS = 0x1600, 1167 SA1_zxth_MASK = 0x1f00, 1168 SL1_loadri_io_BITS = 0x0000, 1169 SL1_loadri_io_MASK = 0x1000, 1170 SL1_loadrub_io_BITS = 0x1000, 1171 SL1_loadrub_io_MASK = 0x1000, 1172 SL2_deallocframe_BITS = 0x1f00, 1173 SL2_deallocframe_MASK = 0x1fc0, 1174 SL2_jumpr31_BITS = 0x1fc0, 1175 SL2_jumpr31_MASK = 0x1fc4, 1176 SL2_jumpr31_f_BITS = 0x1fc5, 1177 SL2_jumpr31_f_MASK = 0x1fc7, 1178 SL2_jumpr31_fnew_BITS = 0x1fc7, 1179 SL2_jumpr31_fnew_MASK = 0x1fc7, 1180 SL2_jumpr31_t_BITS = 0x1fc4, 1181 SL2_jumpr31_t_MASK = 0x1fc7, 1182 SL2_jumpr31_tnew_BITS = 0x1fc6, 1183 SL2_jumpr31_tnew_MASK = 0x1fc7, 1184 SL2_loadrb_io_BITS = 0x1000, 1185 SL2_loadrb_io_MASK = 0x1800, 1186 SL2_loadrd_sp_BITS = 0x1e00, 1187 SL2_loadrd_sp_MASK = 0x1f00, 1188 SL2_loadrh_io_BITS = 0x0000, 1189 SL2_loadrh_io_MASK = 0x1800, 1190 SL2_loadri_sp_BITS = 0x1c00, 1191 SL2_loadri_sp_MASK = 0x1e00, 1192 SL2_loadruh_io_BITS = 0x0800, 1193 SL2_loadruh_io_MASK = 0x1800, 1194 SL2_return_BITS = 0x1f40, 1195 SL2_return_MASK = 0x1fc4, 1196 SL2_return_f_BITS = 0x1f45, 1197 SL2_return_f_MASK = 0x1fc7, 1198 SL2_return_fnew_BITS = 0x1f47, 1199 SL2_return_fnew_MASK = 0x1fc7, 1200 SL2_return_t_BITS = 0x1f44, 1201 SL2_return_t_MASK = 0x1fc7, 1202 SL2_return_tnew_BITS = 0x1f46, 1203 SL2_return_tnew_MASK = 0x1fc7, 1204 SS1_storeb_io_BITS = 0x1000, 1205 SS1_storeb_io_MASK = 0x1000, 1206 SS1_storew_io_BITS = 0x0000, 1207 SS1_storew_io_MASK = 0x1000, 1208 SS2_allocframe_BITS = 0x1c00, 1209 SS2_allocframe_MASK = 0x1e00, 1210 SS2_storebi0_BITS = 0x1200, 1211 SS2_storebi0_MASK = 0x1f00, 1212 SS2_storebi1_BITS = 0x1300, 1213 SS2_storebi1_MASK = 0x1f00, 1214 SS2_stored_sp_BITS = 0x0a00, 1215 SS2_stored_sp_MASK = 0x1e00, 1216 SS2_storeh_io_BITS = 0x0000, 1217 SS2_storeh_io_MASK = 0x1800, 1218 SS2_storew_sp_BITS = 0x0800, 1219 SS2_storew_sp_MASK = 0x1e00, 1220 SS2_storewi0_BITS = 0x1000, 1221 SS2_storewi0_MASK = 0x1f00, 1222 SS2_storewi1_BITS = 0x1100, 1223 SS2_storewi1_MASK = 0x1f00 1224 }; 1225 1226 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 1227 raw_ostream &os) { 1228 switch (IClass) { 1229 case HexagonII::HSIG_L1: 1230 if ((inst & SL1_loadri_io_MASK) == SL1_loadri_io_BITS) 1231 op = Hexagon::SL1_loadri_io; 1232 else if ((inst & SL1_loadrub_io_MASK) == SL1_loadrub_io_BITS) 1233 op = Hexagon::SL1_loadrub_io; 1234 else { 1235 os << "<unknown subinstruction>"; 1236 return MCDisassembler::Fail; 1237 } 1238 break; 1239 case HexagonII::HSIG_L2: 1240 if ((inst & SL2_deallocframe_MASK) == SL2_deallocframe_BITS) 1241 op = Hexagon::SL2_deallocframe; 1242 else if ((inst & SL2_jumpr31_MASK) == SL2_jumpr31_BITS) 1243 op = Hexagon::SL2_jumpr31; 1244 else if ((inst & SL2_jumpr31_f_MASK) == SL2_jumpr31_f_BITS) 1245 op = Hexagon::SL2_jumpr31_f; 1246 else if ((inst & SL2_jumpr31_fnew_MASK) == SL2_jumpr31_fnew_BITS) 1247 op = Hexagon::SL2_jumpr31_fnew; 1248 else if ((inst & SL2_jumpr31_t_MASK) == SL2_jumpr31_t_BITS) 1249 op = Hexagon::SL2_jumpr31_t; 1250 else if ((inst & SL2_jumpr31_tnew_MASK) == SL2_jumpr31_tnew_BITS) 1251 op = Hexagon::SL2_jumpr31_tnew; 1252 else if ((inst & SL2_loadrb_io_MASK) == SL2_loadrb_io_BITS) 1253 op = Hexagon::SL2_loadrb_io; 1254 else if ((inst & SL2_loadrd_sp_MASK) == SL2_loadrd_sp_BITS) 1255 op = Hexagon::SL2_loadrd_sp; 1256 else if ((inst & SL2_loadrh_io_MASK) == SL2_loadrh_io_BITS) 1257 op = Hexagon::SL2_loadrh_io; 1258 else if ((inst & SL2_loadri_sp_MASK) == SL2_loadri_sp_BITS) 1259 op = Hexagon::SL2_loadri_sp; 1260 else if ((inst & SL2_loadruh_io_MASK) == SL2_loadruh_io_BITS) 1261 op = Hexagon::SL2_loadruh_io; 1262 else if ((inst & SL2_return_MASK) == SL2_return_BITS) 1263 op = Hexagon::SL2_return; 1264 else if ((inst & SL2_return_f_MASK) == SL2_return_f_BITS) 1265 op = Hexagon::SL2_return_f; 1266 else if ((inst & SL2_return_fnew_MASK) == SL2_return_fnew_BITS) 1267 op = Hexagon::SL2_return_fnew; 1268 else if ((inst & SL2_return_t_MASK) == SL2_return_t_BITS) 1269 op = Hexagon::SL2_return_t; 1270 else if ((inst & SL2_return_tnew_MASK) == SL2_return_tnew_BITS) 1271 op = Hexagon::SL2_return_tnew; 1272 else { 1273 os << "<unknown subinstruction>"; 1274 return MCDisassembler::Fail; 1275 } 1276 break; 1277 case HexagonII::HSIG_A: 1278 if ((inst & SA1_addi_MASK) == SA1_addi_BITS) 1279 op = Hexagon::SA1_addi; 1280 else if ((inst & SA1_addrx_MASK) == SA1_addrx_BITS) 1281 op = Hexagon::SA1_addrx; 1282 else if ((inst & SA1_addsp_MASK) == SA1_addsp_BITS) 1283 op = Hexagon::SA1_addsp; 1284 else if ((inst & SA1_and1_MASK) == SA1_and1_BITS) 1285 op = Hexagon::SA1_and1; 1286 else if ((inst & SA1_clrf_MASK) == SA1_clrf_BITS) 1287 op = Hexagon::SA1_clrf; 1288 else if ((inst & SA1_clrfnew_MASK) == SA1_clrfnew_BITS) 1289 op = Hexagon::SA1_clrfnew; 1290 else if ((inst & SA1_clrt_MASK) == SA1_clrt_BITS) 1291 op = Hexagon::SA1_clrt; 1292 else if ((inst & SA1_clrtnew_MASK) == SA1_clrtnew_BITS) 1293 op = Hexagon::SA1_clrtnew; 1294 else if ((inst & SA1_cmpeqi_MASK) == SA1_cmpeqi_BITS) 1295 op = Hexagon::SA1_cmpeqi; 1296 else if ((inst & SA1_combine0i_MASK) == SA1_combine0i_BITS) 1297 op = Hexagon::SA1_combine0i; 1298 else if ((inst & SA1_combine1i_MASK) == SA1_combine1i_BITS) 1299 op = Hexagon::SA1_combine1i; 1300 else if ((inst & SA1_combine2i_MASK) == SA1_combine2i_BITS) 1301 op = Hexagon::SA1_combine2i; 1302 else if ((inst & SA1_combine3i_MASK) == SA1_combine3i_BITS) 1303 op = Hexagon::SA1_combine3i; 1304 else if ((inst & SA1_combinerz_MASK) == SA1_combinerz_BITS) 1305 op = Hexagon::SA1_combinerz; 1306 else if ((inst & SA1_combinezr_MASK) == SA1_combinezr_BITS) 1307 op = Hexagon::SA1_combinezr; 1308 else if ((inst & SA1_dec_MASK) == SA1_dec_BITS) 1309 op = Hexagon::SA1_dec; 1310 else if ((inst & SA1_inc_MASK) == SA1_inc_BITS) 1311 op = Hexagon::SA1_inc; 1312 else if ((inst & SA1_seti_MASK) == SA1_seti_BITS) 1313 op = Hexagon::SA1_seti; 1314 else if ((inst & SA1_setin1_MASK) == SA1_setin1_BITS) 1315 op = Hexagon::SA1_setin1; 1316 else if ((inst & SA1_sxtb_MASK) == SA1_sxtb_BITS) 1317 op = Hexagon::SA1_sxtb; 1318 else if ((inst & SA1_sxth_MASK) == SA1_sxth_BITS) 1319 op = Hexagon::SA1_sxth; 1320 else if ((inst & SA1_tfr_MASK) == SA1_tfr_BITS) 1321 op = Hexagon::SA1_tfr; 1322 else if ((inst & SA1_zxtb_MASK) == SA1_zxtb_BITS) 1323 op = Hexagon::SA1_zxtb; 1324 else if ((inst & SA1_zxth_MASK) == SA1_zxth_BITS) 1325 op = Hexagon::SA1_zxth; 1326 else { 1327 os << "<unknown subinstruction>"; 1328 return MCDisassembler::Fail; 1329 } 1330 break; 1331 case HexagonII::HSIG_S1: 1332 if ((inst & SS1_storeb_io_MASK) == SS1_storeb_io_BITS) 1333 op = Hexagon::SS1_storeb_io; 1334 else if ((inst & SS1_storew_io_MASK) == SS1_storew_io_BITS) 1335 op = Hexagon::SS1_storew_io; 1336 else { 1337 os << "<unknown subinstruction>"; 1338 return MCDisassembler::Fail; 1339 } 1340 break; 1341 case HexagonII::HSIG_S2: 1342 if ((inst & SS2_allocframe_MASK) == SS2_allocframe_BITS) 1343 op = Hexagon::SS2_allocframe; 1344 else if ((inst & SS2_storebi0_MASK) == SS2_storebi0_BITS) 1345 op = Hexagon::SS2_storebi0; 1346 else if ((inst & SS2_storebi1_MASK) == SS2_storebi1_BITS) 1347 op = Hexagon::SS2_storebi1; 1348 else if ((inst & SS2_stored_sp_MASK) == SS2_stored_sp_BITS) 1349 op = Hexagon::SS2_stored_sp; 1350 else if ((inst & SS2_storeh_io_MASK) == SS2_storeh_io_BITS) 1351 op = Hexagon::SS2_storeh_io; 1352 else if ((inst & SS2_storew_sp_MASK) == SS2_storew_sp_BITS) 1353 op = Hexagon::SS2_storew_sp; 1354 else if ((inst & SS2_storewi0_MASK) == SS2_storewi0_BITS) 1355 op = Hexagon::SS2_storewi0; 1356 else if ((inst & SS2_storewi1_MASK) == SS2_storewi1_BITS) 1357 op = Hexagon::SS2_storewi1; 1358 else { 1359 os << "<unknown subinstruction>"; 1360 return MCDisassembler::Fail; 1361 } 1362 break; 1363 default: 1364 os << "<unknown>"; 1365 return MCDisassembler::Fail; 1366 } 1367 return MCDisassembler::Success; 1368 } 1369 1370 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) { 1371 if (encoded_reg < 8) 1372 return Hexagon::R0 + encoded_reg; 1373 else if (encoded_reg < 16) 1374 return Hexagon::R0 + encoded_reg + 8; 1375 1376 // patently false value 1377 return Hexagon::NoRegister; 1378 } 1379 1380 static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) { 1381 if (encoded_dreg < 4) 1382 return Hexagon::D0 + encoded_dreg; 1383 else if (encoded_dreg < 8) 1384 return Hexagon::D0 + encoded_dreg + 4; 1385 1386 // patently false value 1387 return Hexagon::NoRegister; 1388 } 1389 1390 void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode, 1391 unsigned inst) const { 1392 int64_t operand; 1393 MCOperand Op; 1394 switch (opcode) { 1395 case Hexagon::SL2_deallocframe: 1396 case Hexagon::SL2_jumpr31: 1397 case Hexagon::SL2_jumpr31_f: 1398 case Hexagon::SL2_jumpr31_fnew: 1399 case Hexagon::SL2_jumpr31_t: 1400 case Hexagon::SL2_jumpr31_tnew: 1401 case Hexagon::SL2_return: 1402 case Hexagon::SL2_return_f: 1403 case Hexagon::SL2_return_fnew: 1404 case Hexagon::SL2_return_t: 1405 case Hexagon::SL2_return_tnew: 1406 // no operands for these instructions 1407 break; 1408 case Hexagon::SS2_allocframe: 1409 // u 8-4{5_3} 1410 operand = ((inst & 0x1f0) >> 4) << 3; 1411 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1412 break; 1413 case Hexagon::SL1_loadri_io: 1414 // Rd 3-0, Rs 7-4, u 11-8{4_2} 1415 operand = getRegFromSubinstEncoding(inst & 0xf); 1416 Op = MCOperand::createReg(operand); 1417 MI->addOperand(Op); 1418 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1419 Op = MCOperand::createReg(operand); 1420 MI->addOperand(Op); 1421 operand = (inst & 0xf00) >> 6; 1422 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1423 break; 1424 case Hexagon::SL1_loadrub_io: 1425 // Rd 3-0, Rs 7-4, u 11-8 1426 operand = getRegFromSubinstEncoding(inst & 0xf); 1427 Op = MCOperand::createReg(operand); 1428 MI->addOperand(Op); 1429 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1430 Op = MCOperand::createReg(operand); 1431 MI->addOperand(Op); 1432 operand = (inst & 0xf00) >> 8; 1433 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1434 break; 1435 case Hexagon::SL2_loadrb_io: 1436 // Rd 3-0, Rs 7-4, u 10-8 1437 operand = getRegFromSubinstEncoding(inst & 0xf); 1438 Op = MCOperand::createReg(operand); 1439 MI->addOperand(Op); 1440 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1441 Op = MCOperand::createReg(operand); 1442 MI->addOperand(Op); 1443 operand = (inst & 0x700) >> 8; 1444 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1445 break; 1446 case Hexagon::SL2_loadrh_io: 1447 case Hexagon::SL2_loadruh_io: 1448 // Rd 3-0, Rs 7-4, u 10-8{3_1} 1449 operand = getRegFromSubinstEncoding(inst & 0xf); 1450 Op = MCOperand::createReg(operand); 1451 MI->addOperand(Op); 1452 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1453 Op = MCOperand::createReg(operand); 1454 MI->addOperand(Op); 1455 operand = ((inst & 0x700) >> 8) << 1; 1456 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1457 break; 1458 case Hexagon::SL2_loadrd_sp: 1459 // Rdd 2-0, u 7-3{5_3} 1460 operand = getDRegFromSubinstEncoding(inst & 0x7); 1461 Op = MCOperand::createReg(operand); 1462 MI->addOperand(Op); 1463 operand = ((inst & 0x0f8) >> 3) << 3; 1464 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1465 break; 1466 case Hexagon::SL2_loadri_sp: 1467 // Rd 3-0, u 8-4{5_2} 1468 operand = getRegFromSubinstEncoding(inst & 0xf); 1469 Op = MCOperand::createReg(operand); 1470 MI->addOperand(Op); 1471 operand = ((inst & 0x1f0) >> 4) << 2; 1472 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1473 break; 1474 case Hexagon::SA1_addi: 1475 // Rx 3-0 (x2), s7 10-4 1476 operand = getRegFromSubinstEncoding(inst & 0xf); 1477 Op = MCOperand::createReg(operand); 1478 MI->addOperand(Op); 1479 MI->addOperand(Op); 1480 operand = SignExtend64<7>((inst & 0x7f0) >> 4); 1481 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1482 break; 1483 case Hexagon::SA1_addrx: 1484 // Rx 3-0 (x2), Rs 7-4 1485 operand = getRegFromSubinstEncoding(inst & 0xf); 1486 Op = MCOperand::createReg(operand); 1487 MI->addOperand(Op); 1488 MI->addOperand(Op); 1489 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1490 Op = MCOperand::createReg(operand); 1491 MI->addOperand(Op); 1492 break; 1493 case Hexagon::SA1_and1: 1494 case Hexagon::SA1_dec: 1495 case Hexagon::SA1_inc: 1496 case Hexagon::SA1_sxtb: 1497 case Hexagon::SA1_sxth: 1498 case Hexagon::SA1_tfr: 1499 case Hexagon::SA1_zxtb: 1500 case Hexagon::SA1_zxth: 1501 // Rd 3-0, Rs 7-4 1502 operand = getRegFromSubinstEncoding(inst & 0xf); 1503 Op = MCOperand::createReg(operand); 1504 MI->addOperand(Op); 1505 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1506 Op = MCOperand::createReg(operand); 1507 MI->addOperand(Op); 1508 break; 1509 case Hexagon::SA1_addsp: 1510 // Rd 3-0, u 9-4{6_2} 1511 operand = getRegFromSubinstEncoding(inst & 0xf); 1512 Op = MCOperand::createReg(operand); 1513 MI->addOperand(Op); 1514 operand = ((inst & 0x3f0) >> 4) << 2; 1515 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1516 break; 1517 case Hexagon::SA1_seti: 1518 // Rd 3-0, u 9-4 1519 operand = getRegFromSubinstEncoding(inst & 0xf); 1520 Op = MCOperand::createReg(operand); 1521 MI->addOperand(Op); 1522 operand = (inst & 0x3f0) >> 4; 1523 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1524 break; 1525 case Hexagon::SA1_clrf: 1526 case Hexagon::SA1_clrfnew: 1527 case Hexagon::SA1_clrt: 1528 case Hexagon::SA1_clrtnew: 1529 case Hexagon::SA1_setin1: 1530 // Rd 3-0 1531 operand = getRegFromSubinstEncoding(inst & 0xf); 1532 Op = MCOperand::createReg(operand); 1533 MI->addOperand(Op); 1534 if (opcode == Hexagon::SA1_setin1) 1535 break; 1536 MI->addOperand(MCOperand::createReg(Hexagon::P0)); 1537 break; 1538 case Hexagon::SA1_cmpeqi: 1539 // Rs 7-4, u 1-0 1540 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1541 Op = MCOperand::createReg(operand); 1542 MI->addOperand(Op); 1543 operand = inst & 0x3; 1544 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1545 break; 1546 case Hexagon::SA1_combine0i: 1547 case Hexagon::SA1_combine1i: 1548 case Hexagon::SA1_combine2i: 1549 case Hexagon::SA1_combine3i: 1550 // Rdd 2-0, u 6-5 1551 operand = getDRegFromSubinstEncoding(inst & 0x7); 1552 Op = MCOperand::createReg(operand); 1553 MI->addOperand(Op); 1554 operand = (inst & 0x060) >> 5; 1555 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1556 break; 1557 case Hexagon::SA1_combinerz: 1558 case Hexagon::SA1_combinezr: 1559 // Rdd 2-0, Rs 7-4 1560 operand = getDRegFromSubinstEncoding(inst & 0x7); 1561 Op = MCOperand::createReg(operand); 1562 MI->addOperand(Op); 1563 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1564 Op = MCOperand::createReg(operand); 1565 MI->addOperand(Op); 1566 break; 1567 case Hexagon::SS1_storeb_io: 1568 // Rs 7-4, u 11-8, Rt 3-0 1569 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1570 Op = MCOperand::createReg(operand); 1571 MI->addOperand(Op); 1572 operand = (inst & 0xf00) >> 8; 1573 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1574 operand = getRegFromSubinstEncoding(inst & 0xf); 1575 Op = MCOperand::createReg(operand); 1576 MI->addOperand(Op); 1577 break; 1578 case Hexagon::SS1_storew_io: 1579 // Rs 7-4, u 11-8{4_2}, Rt 3-0 1580 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1581 Op = MCOperand::createReg(operand); 1582 MI->addOperand(Op); 1583 operand = ((inst & 0xf00) >> 8) << 2; 1584 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1585 operand = getRegFromSubinstEncoding(inst & 0xf); 1586 Op = MCOperand::createReg(operand); 1587 MI->addOperand(Op); 1588 break; 1589 case Hexagon::SS2_storebi0: 1590 case Hexagon::SS2_storebi1: 1591 // Rs 7-4, u 3-0 1592 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1593 Op = MCOperand::createReg(operand); 1594 MI->addOperand(Op); 1595 operand = inst & 0xf; 1596 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1597 break; 1598 case Hexagon::SS2_storewi0: 1599 case Hexagon::SS2_storewi1: 1600 // Rs 7-4, u 3-0{4_2} 1601 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1602 Op = MCOperand::createReg(operand); 1603 MI->addOperand(Op); 1604 operand = (inst & 0xf) << 2; 1605 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1606 break; 1607 case Hexagon::SS2_stored_sp: 1608 // s 8-3{6_3}, Rtt 2-0 1609 operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3); 1610 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1611 operand = getDRegFromSubinstEncoding(inst & 0x7); 1612 Op = MCOperand::createReg(operand); 1613 MI->addOperand(Op); 1614 break; 1615 case Hexagon::SS2_storeh_io: 1616 // Rs 7-4, u 10-8{3_1}, Rt 3-0 1617 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1618 Op = MCOperand::createReg(operand); 1619 MI->addOperand(Op); 1620 operand = ((inst & 0x700) >> 8) << 1; 1621 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1622 operand = getRegFromSubinstEncoding(inst & 0xf); 1623 Op = MCOperand::createReg(operand); 1624 MI->addOperand(Op); 1625 break; 1626 case Hexagon::SS2_storew_sp: 1627 // u 8-4{5_2}, Rd 3-0 1628 operand = ((inst & 0x1f0) >> 4) << 2; 1629 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1630 operand = getRegFromSubinstEncoding(inst & 0xf); 1631 Op = MCOperand::createReg(operand); 1632 MI->addOperand(Op); 1633 break; 1634 default: 1635 // don't crash with an invalid subinstruction 1636 // llvm_unreachable("Invalid subinstruction in duplex instruction"); 1637 break; 1638 } 1639 } 1640