1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCInstrInfo.h" 16 #include "MCTargetDesc/HexagonMCTargetDesc.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/Endian.h" 28 #include "llvm/Support/MathExtras.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include <cassert> 32 #include <cstddef> 33 #include <cstdint> 34 #include <memory> 35 36 using namespace llvm; 37 using namespace Hexagon; 38 39 using DecodeStatus = MCDisassembler::DecodeStatus; 40 41 namespace { 42 43 /// \brief Hexagon disassembler for all Hexagon platforms. 44 class HexagonDisassembler : public MCDisassembler { 45 public: 46 std::unique_ptr<MCInstrInfo const> const MCII; 47 std::unique_ptr<MCInst *> CurrentBundle; 48 49 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 50 MCInstrInfo const *MCII) 51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} 52 53 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 54 ArrayRef<uint8_t> Bytes, uint64_t Address, 55 raw_ostream &VStream, raw_ostream &CStream, 56 bool &Complete) const; 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &VStream, 60 raw_ostream &CStream) const override; 61 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; 62 }; 63 64 } // end anonymous namespace 65 66 static uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, 67 int64_t Value) { 68 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 69 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 70 if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 71 return Value; 72 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 73 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 74 int64_t Bits; 75 bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); 76 assert(Success); (void)Success; 77 uint32_t Upper26 = static_cast<uint32_t>(Bits); 78 uint32_t Operand = Upper26 | Lower6; 79 return Operand; 80 } 81 82 static HexagonDisassembler const &disassembler(void const *Decoder) { 83 return *static_cast<HexagonDisassembler const *>(Decoder); 84 } 85 86 template <size_t T> 87 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 88 HexagonDisassembler const &Disassembler = disassembler(Decoder); 89 int64_t FullValue = 90 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, 91 SignExtend64<T>(tmp)); 92 int64_t Extended = SignExtend64<32>(FullValue); 93 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 94 } 95 96 // Forward declare these because the auto-generated code will reference them. 97 // Definitions are further down. 98 99 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus 116 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 140 uint64_t /*Address*/, const void *Decoder); 141 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 142 const void *Decoder); 143 144 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 145 const void *Decoder) { 146 signedDecoder<4>(MI, tmp, Decoder); 147 return MCDisassembler::Success; 148 } 149 static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 150 const void *Decoder) { 151 signedDecoder<14>(MI, tmp, Decoder); 152 return MCDisassembler::Success; 153 } 154 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 155 const void *Decoder) { 156 signedDecoder<8>(MI, tmp, Decoder); 157 return MCDisassembler::Success; 158 } 159 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 160 const void *Decoder) { 161 signedDecoder<7>(MI, tmp, Decoder); 162 return MCDisassembler::Success; 163 } 164 static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 165 const void *Decoder) { 166 signedDecoder<12>(MI, tmp, Decoder); 167 return MCDisassembler::Success; 168 } 169 static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 170 const void *Decoder) { 171 signedDecoder<3>(MI, tmp, Decoder); 172 return MCDisassembler::Success; 173 } 174 static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 175 const void *Decoder) { 176 signedDecoder<13>(MI, tmp, Decoder); 177 return MCDisassembler::Success; 178 } 179 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 180 const void *Decoder) { 181 signedDecoder<6>(MI, tmp, Decoder); 182 return MCDisassembler::Success; 183 } 184 static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 185 const void *Decoder) { 186 signedDecoder<9>(MI, tmp, Decoder); 187 return MCDisassembler::Success; 188 } 189 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 190 const void *Decoder) { 191 signedDecoder<5>(MI, tmp, Decoder); 192 return MCDisassembler::Success; 193 } 194 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, 195 const void *Decoder) { 196 signedDecoder<6>(MI, tmp, Decoder); 197 return MCDisassembler::Success; 198 } 199 200 #include "HexagonGenDisassemblerTables.inc" 201 202 static MCDisassembler *createHexagonDisassembler(const Target &T, 203 const MCSubtargetInfo &STI, 204 MCContext &Ctx) { 205 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 206 } 207 208 extern "C" void LLVMInitializeHexagonDisassembler() { 209 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 210 createHexagonDisassembler); 211 } 212 213 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 214 ArrayRef<uint8_t> Bytes, 215 uint64_t Address, 216 raw_ostream &os, 217 raw_ostream &cs) const { 218 DecodeStatus Result = DecodeStatus::Success; 219 bool Complete = false; 220 Size = 0; 221 222 *CurrentBundle = &MI; 223 MI = HexagonMCInstrInfo::createBundle(); 224 while (Result == Success && !Complete) { 225 if (Bytes.size() < HEXAGON_INSTR_SIZE) 226 return MCDisassembler::Fail; 227 MCInst *Inst = new (getContext()) MCInst; 228 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 229 MI.addOperand(MCOperand::createInst(Inst)); 230 Size += HEXAGON_INSTR_SIZE; 231 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 232 } 233 if (Result == MCDisassembler::Fail) 234 return Result; 235 if (Size > HEXAGON_MAX_PACKET_SIZE) 236 return MCDisassembler::Fail; 237 HexagonMCChecker Checker(getContext(), *MCII, STI, MI, 238 *getContext().getRegisterInfo(), false); 239 if (!Checker.check()) 240 return MCDisassembler::Fail; 241 return MCDisassembler::Success; 242 } 243 244 static void adjustDuplex(MCInst &MI, MCContext &Context) { 245 switch (MI.getOpcode()) { 246 case Hexagon::SA1_setin1: 247 MI.insert(MI.begin() + 1, 248 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 249 break; 250 case Hexagon::SA1_dec: 251 MI.insert(MI.begin() + 2, 252 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 253 break; 254 default: 255 break; 256 } 257 } 258 259 DecodeStatus HexagonDisassembler::getSingleInstruction( 260 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 261 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 262 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 263 264 uint32_t Instruction = support::endian::read32le(Bytes.data()); 265 266 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 267 if ((Instruction & HexagonII::INST_PARSE_MASK) == 268 HexagonII::INST_PARSE_LOOP_END) { 269 if (BundleSize == 0) 270 HexagonMCInstrInfo::setInnerLoop(MCB); 271 else if (BundleSize == 1) 272 HexagonMCInstrInfo::setOuterLoop(MCB); 273 else 274 return DecodeStatus::Fail; 275 } 276 277 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 278 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 279 280 DecodeStatus Result = DecodeStatus::Fail; 281 if ((Instruction & HexagonII::INST_PARSE_MASK) == 282 HexagonII::INST_PARSE_DUPLEX) { 283 unsigned duplexIClass; 284 uint8_t const *DecodeLow, *DecodeHigh; 285 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 286 switch (duplexIClass) { 287 default: 288 return MCDisassembler::Fail; 289 case 0: 290 DecodeLow = DecoderTableSUBINSN_L132; 291 DecodeHigh = DecoderTableSUBINSN_L132; 292 break; 293 case 1: 294 DecodeLow = DecoderTableSUBINSN_L232; 295 DecodeHigh = DecoderTableSUBINSN_L132; 296 break; 297 case 2: 298 DecodeLow = DecoderTableSUBINSN_L232; 299 DecodeHigh = DecoderTableSUBINSN_L232; 300 break; 301 case 3: 302 DecodeLow = DecoderTableSUBINSN_A32; 303 DecodeHigh = DecoderTableSUBINSN_A32; 304 break; 305 case 4: 306 DecodeLow = DecoderTableSUBINSN_L132; 307 DecodeHigh = DecoderTableSUBINSN_A32; 308 break; 309 case 5: 310 DecodeLow = DecoderTableSUBINSN_L232; 311 DecodeHigh = DecoderTableSUBINSN_A32; 312 break; 313 case 6: 314 DecodeLow = DecoderTableSUBINSN_S132; 315 DecodeHigh = DecoderTableSUBINSN_A32; 316 break; 317 case 7: 318 DecodeLow = DecoderTableSUBINSN_S232; 319 DecodeHigh = DecoderTableSUBINSN_A32; 320 break; 321 case 8: 322 DecodeLow = DecoderTableSUBINSN_S132; 323 DecodeHigh = DecoderTableSUBINSN_L132; 324 break; 325 case 9: 326 DecodeLow = DecoderTableSUBINSN_S132; 327 DecodeHigh = DecoderTableSUBINSN_L232; 328 break; 329 case 10: 330 DecodeLow = DecoderTableSUBINSN_S132; 331 DecodeHigh = DecoderTableSUBINSN_S132; 332 break; 333 case 11: 334 DecodeLow = DecoderTableSUBINSN_S232; 335 DecodeHigh = DecoderTableSUBINSN_S132; 336 break; 337 case 12: 338 DecodeLow = DecoderTableSUBINSN_S232; 339 DecodeHigh = DecoderTableSUBINSN_L132; 340 break; 341 case 13: 342 DecodeLow = DecoderTableSUBINSN_S232; 343 DecodeHigh = DecoderTableSUBINSN_L232; 344 break; 345 case 14: 346 DecodeLow = DecoderTableSUBINSN_S232; 347 DecodeHigh = DecoderTableSUBINSN_S232; 348 break; 349 } 350 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); 351 MCInst *MILow = new (getContext()) MCInst; 352 MCInst *MIHigh = new (getContext()) MCInst; 353 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, 354 this, STI); 355 if (Result != DecodeStatus::Success) 356 return DecodeStatus::Fail; 357 adjustDuplex(*MILow, getContext()); 358 Result = decodeInstruction( 359 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); 360 if (Result != DecodeStatus::Success) 361 return DecodeStatus::Fail; 362 adjustDuplex(*MIHigh, getContext()); 363 MCOperand OPLow = MCOperand::createInst(MILow); 364 MCOperand OPHigh = MCOperand::createInst(MIHigh); 365 MI.addOperand(OPLow); 366 MI.addOperand(OPHigh); 367 Complete = true; 368 } else { 369 if ((Instruction & HexagonII::INST_PARSE_MASK) == 370 HexagonII::INST_PARSE_PACKET_END) 371 Complete = true; 372 373 if (Extender != nullptr) 374 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, 375 Address, this, STI); 376 377 if (Result != MCDisassembler::Success) 378 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, 379 STI); 380 381 if (Result != MCDisassembler::Success && 382 STI.getFeatureBits()[Hexagon::ExtensionHVX]) 383 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, 384 Address, this, STI); 385 386 } 387 388 switch (MI.getOpcode()) { 389 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 390 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 391 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 392 case Hexagon::J4_cmpeqn1_fp0_jump_t: 393 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 394 case Hexagon::J4_cmpeqn1_fp1_jump_t: 395 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 396 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 397 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 398 case Hexagon::J4_cmpeqn1_tp0_jump_t: 399 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 400 case Hexagon::J4_cmpeqn1_tp1_jump_t: 401 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 402 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 403 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 404 case Hexagon::J4_cmpgtn1_fp0_jump_t: 405 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 406 case Hexagon::J4_cmpgtn1_fp1_jump_t: 407 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 408 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 409 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 410 case Hexagon::J4_cmpgtn1_tp0_jump_t: 411 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 412 case Hexagon::J4_cmpgtn1_tp1_jump_t: 413 MI.insert(MI.begin() + 1, 414 MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 415 break; 416 default: 417 break; 418 } 419 420 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 421 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 422 MCOperand &MCO = MI.getOperand(OpIndex); 423 assert(MCO.isReg() && "New value consumers must be registers"); 424 unsigned Register = 425 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 426 if ((Register & 0x6) == 0) 427 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 428 return MCDisassembler::Fail; 429 unsigned Lookback = (Register & 0x6) >> 1; 430 unsigned Offset = 1; 431 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 432 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 433 auto i = Instructions.end() - 1; 434 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 435 if (i == n) 436 // Couldn't find producer 437 return MCDisassembler::Fail; 438 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) 439 // Skip scalars when calculating distances for vectors 440 ++Lookback; 441 if (HexagonMCInstrInfo::isImmext(*i->getInst())) 442 ++Lookback; 443 if (Offset == Lookback) 444 break; 445 } 446 auto const &Inst = *i->getInst(); 447 bool SubregBit = (Register & 0x1) != 0; 448 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 449 // If subreg bit is set we're selecting the second produced newvalue 450 unsigned Producer = 451 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 452 assert(Producer != Hexagon::NoRegister); 453 MCO.setReg(Producer); 454 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 455 unsigned Producer = 456 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 457 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 458 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 459 else if (SubregBit) 460 // Hexagon PRM 10.11 New-value operands 461 // Nt[0] is reserved and should always be encoded as zero. 462 return MCDisassembler::Fail; 463 assert(Producer != Hexagon::NoRegister); 464 MCO.setReg(Producer); 465 } else 466 return MCDisassembler::Fail; 467 } 468 469 if (Extender != nullptr) { 470 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) 471 ? *MI.getOperand(1).getInst() 472 : MI; 473 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 474 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 475 return MCDisassembler::Fail; 476 } 477 return Result; 478 } 479 480 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 481 ArrayRef<MCPhysReg> Table) { 482 if (RegNo < Table.size()) { 483 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 484 return MCDisassembler::Success; 485 } 486 487 return MCDisassembler::Fail; 488 } 489 490 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 491 uint64_t Address, 492 const void *Decoder) { 493 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 494 } 495 496 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 497 uint64_t Address, 498 const void *Decoder) { 499 static const MCPhysReg IntRegDecoderTable[] = { 500 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 501 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 502 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 503 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 504 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 505 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 506 Hexagon::R30, Hexagon::R31}; 507 508 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 509 } 510 511 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 512 unsigned RegNo, 513 uint64_t Address, 514 const void *Decoder) { 515 static const MCPhysReg GeneralSubRegDecoderTable[] = { 516 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 517 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, 518 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 519 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 520 }; 521 522 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); 523 } 524 525 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 526 uint64_t /*Address*/, 527 const void *Decoder) { 528 static const MCPhysReg HvxVRDecoderTable[] = { 529 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 530 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 531 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 532 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 533 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 534 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 535 Hexagon::V30, Hexagon::V31}; 536 537 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); 538 } 539 540 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 541 uint64_t /*Address*/, 542 const void *Decoder) { 543 static const MCPhysReg DoubleRegDecoderTable[] = { 544 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 545 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 546 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 547 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 548 549 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 550 } 551 552 static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( 553 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { 554 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { 555 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 556 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; 557 558 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); 559 } 560 561 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 562 uint64_t /*Address*/, 563 const void *Decoder) { 564 static const MCPhysReg HvxWRDecoderTable[] = { 565 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 566 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 567 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 568 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 569 570 return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable)); 571 } 572 573 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 574 uint64_t /*Address*/, 575 const void *Decoder) { 576 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 577 Hexagon::P2, Hexagon::P3}; 578 579 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 580 } 581 582 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 583 uint64_t /*Address*/, 584 const void *Decoder) { 585 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 586 Hexagon::Q2, Hexagon::Q3}; 587 588 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); 589 } 590 591 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 592 uint64_t /*Address*/, 593 const void *Decoder) { 594 using namespace Hexagon; 595 596 static const MCPhysReg CtrlRegDecoderTable[] = { 597 /* 0 */ SA0, LC0, SA1, LC1, 598 /* 4 */ P3_0, C5, M0, M1, 599 /* 8 */ USR, PC, UGP, GP, 600 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, 601 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, 602 /* 20 */ 0, 0, 0, 0, 603 /* 24 */ 0, 0, 0, 0, 604 /* 28 */ 0, 0, UTIMERLO, UTIMERHI 605 }; 606 607 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 608 return MCDisassembler::Fail; 609 610 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 611 if (CtrlRegDecoderTable[RegNo] == NoRegister) 612 return MCDisassembler::Fail; 613 614 unsigned Register = CtrlRegDecoderTable[RegNo]; 615 Inst.addOperand(MCOperand::createReg(Register)); 616 return MCDisassembler::Success; 617 } 618 619 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 620 uint64_t /*Address*/, 621 const void *Decoder) { 622 using namespace Hexagon; 623 624 static const MCPhysReg CtrlReg64DecoderTable[] = { 625 /* 0 */ C1_0, 0, C3_2, 0, 626 /* 4 */ C5_4, 0, C7_6, 0, 627 /* 8 */ C9_8, 0, C11_10, 0, 628 /* 12 */ CS, 0, UPCYCLE, 0, 629 /* 16 */ C17_16, 0, PKTCOUNT, 0, 630 /* 20 */ 0, 0, 0, 0, 631 /* 24 */ 0, 0, 0, 0, 632 /* 28 */ 0, 0, UTIMER, 0 633 }; 634 635 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 636 return MCDisassembler::Fail; 637 638 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 639 if (CtrlReg64DecoderTable[RegNo] == NoRegister) 640 return MCDisassembler::Fail; 641 642 unsigned Register = CtrlReg64DecoderTable[RegNo]; 643 Inst.addOperand(MCOperand::createReg(Register)); 644 return MCDisassembler::Success; 645 } 646 647 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 648 uint64_t /*Address*/, 649 const void *Decoder) { 650 unsigned Register = 0; 651 switch (RegNo) { 652 case 0: 653 Register = Hexagon::M0; 654 break; 655 case 1: 656 Register = Hexagon::M1; 657 break; 658 default: 659 return MCDisassembler::Fail; 660 } 661 Inst.addOperand(MCOperand::createReg(Register)); 662 return MCDisassembler::Success; 663 } 664 665 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 666 uint64_t /*Address*/, 667 const void *Decoder) { 668 HexagonDisassembler const &Disassembler = disassembler(Decoder); 669 int64_t FullValue = 670 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, tmp); 671 assert(FullValue >= 0 && "Negative in unsigned decoder"); 672 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 673 return MCDisassembler::Success; 674 } 675 676 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 677 uint64_t /*Address*/, const void *Decoder) { 678 HexagonDisassembler const &Disassembler = disassembler(Decoder); 679 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 680 tmp = SignExtend64(tmp, Bits); 681 signedDecoder<32>(MI, tmp, Decoder); 682 return MCDisassembler::Success; 683 } 684 685 // custom decoder for various jump/call immediates 686 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 687 const void *Decoder) { 688 HexagonDisassembler const &Disassembler = disassembler(Decoder); 689 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 690 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 691 if (Bits == 0) 692 Bits = 15; 693 uint32_t FullValue = 694 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, 695 SignExtend64(tmp, Bits)); 696 int64_t Extended = SignExtend64<32>(FullValue) + Address; 697 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) 698 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 699 return MCDisassembler::Success; 700 } 701