1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #define DEBUG_TYPE "hexagon-disassembler" 10 11 #include "MCTargetDesc/HexagonBaseInfo.h" 12 #include "MCTargetDesc/HexagonMCChecker.h" 13 #include "MCTargetDesc/HexagonMCInstrInfo.h" 14 #include "MCTargetDesc/HexagonMCTargetDesc.h" 15 #include "TargetInfo/HexagonTargetInfo.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/Endian.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/TargetRegistry.h" 29 #include "llvm/Support/raw_ostream.h" 30 #include <cassert> 31 #include <cstddef> 32 #include <cstdint> 33 #include <memory> 34 35 using namespace llvm; 36 using namespace Hexagon; 37 38 using DecodeStatus = MCDisassembler::DecodeStatus; 39 40 namespace { 41 42 /// Hexagon disassembler for all Hexagon platforms. 43 class HexagonDisassembler : public MCDisassembler { 44 public: 45 std::unique_ptr<MCInstrInfo const> const MCII; 46 std::unique_ptr<MCInst *> CurrentBundle; 47 mutable MCInst const *CurrentExtender; 48 49 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 50 MCInstrInfo const *MCII) 51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), 52 CurrentExtender(nullptr) {} 53 54 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 55 ArrayRef<uint8_t> Bytes, uint64_t Address, 56 raw_ostream &CStream, bool &Complete) const; 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &CStream) const override; 60 void remapInstruction(MCInst &Instr) const; 61 }; 62 63 static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI, 64 int64_t Value) { 65 MCInstrInfo MCII = *Disassembler.MCII; 66 if (!Disassembler.CurrentExtender || 67 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 68 return Value; 69 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 70 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 71 int64_t Bits; 72 bool Success = 73 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute( 74 Bits); 75 assert(Success); 76 (void)Success; 77 uint64_t Upper26 = static_cast<uint64_t>(Bits); 78 uint64_t Operand = Upper26 | Lower6; 79 return Operand; 80 } 81 static HexagonDisassembler const &disassembler(void const *Decoder) { 82 return *static_cast<HexagonDisassembler const *>(Decoder); 83 } 84 template <size_t T> 85 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 86 HexagonDisassembler const &Disassembler = disassembler(Decoder); 87 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp)); 88 int64_t Extended = SignExtend64<32>(FullValue); 89 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 90 } 91 } 92 93 // Forward declare these because the auto-generated code will reference them. 94 // Definitions are further down. 95 96 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 97 uint64_t Address, 98 const void *Decoder); 99 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 100 unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus 113 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, 117 const void *Decoder); 118 static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, 132 uint64_t Address, 133 const void *Decoder); 134 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 135 uint64_t Address, 136 const void *Decoder); 137 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 141 uint64_t Address, 142 const void *Decoder); 143 144 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 147 uint64_t /*Address*/, const void *Decoder); 148 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 149 const void *Decoder); 150 #include "HexagonDepDecoders.inc" 151 #include "HexagonGenDisassemblerTables.inc" 152 153 static MCDisassembler *createHexagonDisassembler(const Target &T, 154 const MCSubtargetInfo &STI, 155 MCContext &Ctx) { 156 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 157 } 158 159 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler() { 160 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 161 createHexagonDisassembler); 162 } 163 164 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 165 ArrayRef<uint8_t> Bytes, 166 uint64_t Address, 167 raw_ostream &cs) const { 168 DecodeStatus Result = DecodeStatus::Success; 169 bool Complete = false; 170 Size = 0; 171 172 *CurrentBundle = &MI; 173 MI.setOpcode(Hexagon::BUNDLE); 174 MI.addOperand(MCOperand::createImm(0)); 175 while (Result == Success && !Complete) { 176 if (Bytes.size() < HEXAGON_INSTR_SIZE) 177 return MCDisassembler::Fail; 178 MCInst *Inst = new (getContext()) MCInst; 179 Result = getSingleInstruction(*Inst, MI, Bytes, Address, cs, Complete); 180 MI.addOperand(MCOperand::createInst(Inst)); 181 Size += HEXAGON_INSTR_SIZE; 182 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 183 } 184 if (Result == MCDisassembler::Fail) 185 return Result; 186 if (Size > HEXAGON_MAX_PACKET_SIZE) 187 return MCDisassembler::Fail; 188 189 const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI); 190 const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI; 191 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI, 192 *getContext().getRegisterInfo(), false); 193 if (!Checker.check()) 194 return MCDisassembler::Fail; 195 remapInstruction(MI); 196 return MCDisassembler::Success; 197 } 198 199 void HexagonDisassembler::remapInstruction(MCInst &Instr) const { 200 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) { 201 auto &MI = const_cast<MCInst &>(*I.getInst()); 202 switch (MI.getOpcode()) { 203 case Hexagon::S2_allocframe: 204 if (MI.getOperand(0).getReg() == Hexagon::R29) { 205 MI.setOpcode(Hexagon::S6_allocframe_to_raw); 206 MI.erase(MI.begin () + 1); 207 MI.erase(MI.begin ()); 208 } 209 break; 210 case Hexagon::L2_deallocframe: 211 if (MI.getOperand(0).getReg() == Hexagon::D15 && 212 MI.getOperand(1).getReg() == Hexagon::R30) { 213 MI.setOpcode(L6_deallocframe_map_to_raw); 214 MI.erase(MI.begin () + 1); 215 MI.erase(MI.begin ()); 216 } 217 break; 218 case Hexagon::L4_return: 219 if (MI.getOperand(0).getReg() == Hexagon::D15 && 220 MI.getOperand(1).getReg() == Hexagon::R30) { 221 MI.setOpcode(L6_return_map_to_raw); 222 MI.erase(MI.begin () + 1); 223 MI.erase(MI.begin ()); 224 } 225 break; 226 case Hexagon::L4_return_t: 227 if (MI.getOperand(0).getReg() == Hexagon::D15 && 228 MI.getOperand(2).getReg() == Hexagon::R30) { 229 MI.setOpcode(L4_return_map_to_raw_t); 230 MI.erase(MI.begin () + 2); 231 MI.erase(MI.begin ()); 232 } 233 break; 234 case Hexagon::L4_return_f: 235 if (MI.getOperand(0).getReg() == Hexagon::D15 && 236 MI.getOperand(2).getReg() == Hexagon::R30) { 237 MI.setOpcode(L4_return_map_to_raw_f); 238 MI.erase(MI.begin () + 2); 239 MI.erase(MI.begin ()); 240 } 241 break; 242 case Hexagon::L4_return_tnew_pt: 243 if (MI.getOperand(0).getReg() == Hexagon::D15 && 244 MI.getOperand(2).getReg() == Hexagon::R30) { 245 MI.setOpcode(L4_return_map_to_raw_tnew_pt); 246 MI.erase(MI.begin () + 2); 247 MI.erase(MI.begin ()); 248 } 249 break; 250 case Hexagon::L4_return_fnew_pt: 251 if (MI.getOperand(0).getReg() == Hexagon::D15 && 252 MI.getOperand(2).getReg() == Hexagon::R30) { 253 MI.setOpcode(L4_return_map_to_raw_fnew_pt); 254 MI.erase(MI.begin () + 2); 255 MI.erase(MI.begin ()); 256 } 257 break; 258 case Hexagon::L4_return_tnew_pnt: 259 if (MI.getOperand(0).getReg() == Hexagon::D15 && 260 MI.getOperand(2).getReg() == Hexagon::R30) { 261 MI.setOpcode(L4_return_map_to_raw_tnew_pnt); 262 MI.erase(MI.begin () + 2); 263 MI.erase(MI.begin ()); 264 } 265 break; 266 case Hexagon::L4_return_fnew_pnt: 267 if (MI.getOperand(0).getReg() == Hexagon::D15 && 268 MI.getOperand(2).getReg() == Hexagon::R30) { 269 MI.setOpcode(L4_return_map_to_raw_fnew_pnt); 270 MI.erase(MI.begin () + 2); 271 MI.erase(MI.begin ()); 272 } 273 break; 274 } 275 } 276 } 277 278 static void adjustDuplex(MCInst &MI, MCContext &Context) { 279 switch (MI.getOpcode()) { 280 case Hexagon::SA1_setin1: 281 MI.insert(MI.begin() + 1, 282 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 283 break; 284 case Hexagon::SA1_dec: 285 MI.insert(MI.begin() + 2, 286 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 287 break; 288 default: 289 break; 290 } 291 } 292 293 DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB, 294 ArrayRef<uint8_t> Bytes, 295 uint64_t Address, 296 raw_ostream &cs, 297 bool &Complete) const { 298 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 299 300 uint32_t Instruction = support::endian::read32le(Bytes.data()); 301 302 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 303 if ((Instruction & HexagonII::INST_PARSE_MASK) == 304 HexagonII::INST_PARSE_LOOP_END) { 305 if (BundleSize == 0) 306 HexagonMCInstrInfo::setInnerLoop(MCB); 307 else if (BundleSize == 1) 308 HexagonMCInstrInfo::setOuterLoop(MCB); 309 else 310 return DecodeStatus::Fail; 311 } 312 313 CurrentExtender = HexagonMCInstrInfo::extenderForIndex( 314 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 315 316 DecodeStatus Result = DecodeStatus::Fail; 317 if ((Instruction & HexagonII::INST_PARSE_MASK) == 318 HexagonII::INST_PARSE_DUPLEX) { 319 unsigned duplexIClass; 320 uint8_t const *DecodeLow, *DecodeHigh; 321 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 322 switch (duplexIClass) { 323 default: 324 return MCDisassembler::Fail; 325 case 0: 326 DecodeLow = DecoderTableSUBINSN_L132; 327 DecodeHigh = DecoderTableSUBINSN_L132; 328 break; 329 case 1: 330 DecodeLow = DecoderTableSUBINSN_L232; 331 DecodeHigh = DecoderTableSUBINSN_L132; 332 break; 333 case 2: 334 DecodeLow = DecoderTableSUBINSN_L232; 335 DecodeHigh = DecoderTableSUBINSN_L232; 336 break; 337 case 3: 338 DecodeLow = DecoderTableSUBINSN_A32; 339 DecodeHigh = DecoderTableSUBINSN_A32; 340 break; 341 case 4: 342 DecodeLow = DecoderTableSUBINSN_L132; 343 DecodeHigh = DecoderTableSUBINSN_A32; 344 break; 345 case 5: 346 DecodeLow = DecoderTableSUBINSN_L232; 347 DecodeHigh = DecoderTableSUBINSN_A32; 348 break; 349 case 6: 350 DecodeLow = DecoderTableSUBINSN_S132; 351 DecodeHigh = DecoderTableSUBINSN_A32; 352 break; 353 case 7: 354 DecodeLow = DecoderTableSUBINSN_S232; 355 DecodeHigh = DecoderTableSUBINSN_A32; 356 break; 357 case 8: 358 DecodeLow = DecoderTableSUBINSN_S132; 359 DecodeHigh = DecoderTableSUBINSN_L132; 360 break; 361 case 9: 362 DecodeLow = DecoderTableSUBINSN_S132; 363 DecodeHigh = DecoderTableSUBINSN_L232; 364 break; 365 case 10: 366 DecodeLow = DecoderTableSUBINSN_S132; 367 DecodeHigh = DecoderTableSUBINSN_S132; 368 break; 369 case 11: 370 DecodeLow = DecoderTableSUBINSN_S232; 371 DecodeHigh = DecoderTableSUBINSN_S132; 372 break; 373 case 12: 374 DecodeLow = DecoderTableSUBINSN_S232; 375 DecodeHigh = DecoderTableSUBINSN_L132; 376 break; 377 case 13: 378 DecodeLow = DecoderTableSUBINSN_S232; 379 DecodeHigh = DecoderTableSUBINSN_L232; 380 break; 381 case 14: 382 DecodeLow = DecoderTableSUBINSN_S232; 383 DecodeHigh = DecoderTableSUBINSN_S232; 384 break; 385 } 386 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); 387 MCInst *MILow = new (getContext()) MCInst; 388 MCInst *MIHigh = new (getContext()) MCInst; 389 auto TmpExtender = CurrentExtender; 390 CurrentExtender = 391 nullptr; // constant extenders in duplex must always be in slot 1 392 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, 393 this, STI); 394 CurrentExtender = TmpExtender; 395 if (Result != DecodeStatus::Success) 396 return DecodeStatus::Fail; 397 adjustDuplex(*MILow, getContext()); 398 Result = decodeInstruction( 399 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); 400 if (Result != DecodeStatus::Success) 401 return DecodeStatus::Fail; 402 adjustDuplex(*MIHigh, getContext()); 403 MCOperand OPLow = MCOperand::createInst(MILow); 404 MCOperand OPHigh = MCOperand::createInst(MIHigh); 405 MI.addOperand(OPLow); 406 MI.addOperand(OPHigh); 407 Complete = true; 408 } else { 409 if ((Instruction & HexagonII::INST_PARSE_MASK) == 410 HexagonII::INST_PARSE_PACKET_END) 411 Complete = true; 412 413 if (CurrentExtender != nullptr) 414 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, 415 Address, this, STI); 416 417 if (Result != MCDisassembler::Success) 418 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, 419 STI); 420 421 if (Result != MCDisassembler::Success && 422 STI.getFeatureBits()[Hexagon::ExtensionHVX]) 423 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, 424 Address, this, STI); 425 426 } 427 428 switch (MI.getOpcode()) { 429 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 430 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 431 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 432 case Hexagon::J4_cmpeqn1_fp0_jump_t: 433 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 434 case Hexagon::J4_cmpeqn1_fp1_jump_t: 435 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 436 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 437 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 438 case Hexagon::J4_cmpeqn1_tp0_jump_t: 439 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 440 case Hexagon::J4_cmpeqn1_tp1_jump_t: 441 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 442 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 443 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 444 case Hexagon::J4_cmpgtn1_fp0_jump_t: 445 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 446 case Hexagon::J4_cmpgtn1_fp1_jump_t: 447 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 448 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 449 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 450 case Hexagon::J4_cmpgtn1_tp0_jump_t: 451 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 452 case Hexagon::J4_cmpgtn1_tp1_jump_t: 453 MI.insert(MI.begin() + 1, 454 MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 455 break; 456 default: 457 break; 458 } 459 460 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 461 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 462 MCOperand &MCO = MI.getOperand(OpIndex); 463 assert(MCO.isReg() && "New value consumers must be registers"); 464 unsigned Register = 465 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 466 if ((Register & 0x6) == 0) 467 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 468 return MCDisassembler::Fail; 469 unsigned Lookback = (Register & 0x6) >> 1; 470 unsigned Offset = 1; 471 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 472 bool PrevVector = false; 473 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 474 auto i = Instructions.end() - 1; 475 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 476 if (i == n) 477 // Couldn't find producer 478 return MCDisassembler::Fail; 479 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst()); 480 if (Vector && !CurrentVector) 481 // Skip scalars when calculating distances for vectors 482 ++Lookback; 483 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector)) 484 ++Lookback; 485 PrevVector = CurrentVector; 486 if (Offset == Lookback) 487 break; 488 } 489 auto const &Inst = *i->getInst(); 490 bool SubregBit = (Register & 0x1) != 0; 491 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 492 // If subreg bit is set we're selecting the second produced newvalue 493 unsigned Producer = SubregBit ? 494 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() : 495 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 496 assert(Producer != Hexagon::NoRegister); 497 MCO.setReg(Producer); 498 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 499 unsigned Producer = 500 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 501 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 502 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 503 else if (SubregBit) 504 // Hexagon PRM 10.11 New-value operands 505 // Nt[0] is reserved and should always be encoded as zero. 506 return MCDisassembler::Fail; 507 assert(Producer != Hexagon::NoRegister); 508 MCO.setReg(Producer); 509 } else 510 return MCDisassembler::Fail; 511 } 512 513 if (CurrentExtender != nullptr) { 514 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) 515 ? *MI.getOperand(1).getInst() 516 : MI; 517 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 518 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 519 return MCDisassembler::Fail; 520 } 521 return Result; 522 } 523 524 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 525 ArrayRef<MCPhysReg> Table) { 526 if (RegNo < Table.size()) { 527 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 528 return MCDisassembler::Success; 529 } 530 531 return MCDisassembler::Fail; 532 } 533 534 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 535 uint64_t Address, 536 const void *Decoder) { 537 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 538 } 539 540 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 541 uint64_t Address, 542 const void *Decoder) { 543 static const MCPhysReg IntRegDecoderTable[] = { 544 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 545 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 546 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 547 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 548 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 549 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 550 Hexagon::R30, Hexagon::R31}; 551 552 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 553 } 554 555 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 556 unsigned RegNo, 557 uint64_t Address, 558 const void *Decoder) { 559 static const MCPhysReg GeneralSubRegDecoderTable[] = { 560 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 561 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, 562 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 563 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 564 }; 565 566 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); 567 } 568 569 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 570 uint64_t /*Address*/, 571 const void *Decoder) { 572 static const MCPhysReg HvxVRDecoderTable[] = { 573 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 574 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 575 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 576 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 577 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 578 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 579 Hexagon::V30, Hexagon::V31}; 580 581 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); 582 } 583 584 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 585 uint64_t /*Address*/, 586 const void *Decoder) { 587 static const MCPhysReg DoubleRegDecoderTable[] = { 588 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 589 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 590 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 591 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 592 593 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 594 } 595 596 static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( 597 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { 598 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { 599 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 600 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; 601 602 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); 603 } 604 605 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 606 uint64_t /*Address*/, 607 const void *Decoder) { 608 static const MCPhysReg HvxWRDecoderTable[] = { 609 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 610 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 611 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 612 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 613 614 return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable)); 615 } 616 617 LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily. 618 static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, 619 unsigned RegNo, 620 uint64_t /*Address*/, 621 const void *Decoder) { 622 static const MCPhysReg HvxVQRDecoderTable[] = { 623 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, 624 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7}; 625 626 return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable); 627 } 628 629 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 630 uint64_t /*Address*/, 631 const void *Decoder) { 632 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 633 Hexagon::P2, Hexagon::P3}; 634 635 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 636 } 637 638 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 639 uint64_t /*Address*/, 640 const void *Decoder) { 641 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 642 Hexagon::Q2, Hexagon::Q3}; 643 644 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); 645 } 646 647 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 648 uint64_t /*Address*/, 649 const void *Decoder) { 650 using namespace Hexagon; 651 652 static const MCPhysReg CtrlRegDecoderTable[] = { 653 /* 0 */ SA0, LC0, SA1, LC1, 654 /* 4 */ P3_0, C5, M0, M1, 655 /* 8 */ USR, PC, UGP, GP, 656 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, 657 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, 658 /* 20 */ 0, 0, 0, 0, 659 /* 24 */ 0, 0, 0, 0, 660 /* 28 */ 0, 0, UTIMERLO, UTIMERHI 661 }; 662 663 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 664 return MCDisassembler::Fail; 665 666 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 667 if (CtrlRegDecoderTable[RegNo] == NoRegister) 668 return MCDisassembler::Fail; 669 670 unsigned Register = CtrlRegDecoderTable[RegNo]; 671 Inst.addOperand(MCOperand::createReg(Register)); 672 return MCDisassembler::Success; 673 } 674 675 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 676 uint64_t /*Address*/, 677 const void *Decoder) { 678 using namespace Hexagon; 679 680 static const MCPhysReg CtrlReg64DecoderTable[] = { 681 /* 0 */ C1_0, 0, C3_2, 0, 682 /* 4 */ C5_4, 0, C7_6, 0, 683 /* 8 */ C9_8, 0, C11_10, 0, 684 /* 12 */ CS, 0, UPCYCLE, 0, 685 /* 16 */ C17_16, 0, PKTCOUNT, 0, 686 /* 20 */ 0, 0, 0, 0, 687 /* 24 */ 0, 0, 0, 0, 688 /* 28 */ 0, 0, UTIMER, 0 689 }; 690 691 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 692 return MCDisassembler::Fail; 693 694 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 695 if (CtrlReg64DecoderTable[RegNo] == NoRegister) 696 return MCDisassembler::Fail; 697 698 unsigned Register = CtrlReg64DecoderTable[RegNo]; 699 Inst.addOperand(MCOperand::createReg(Register)); 700 return MCDisassembler::Success; 701 } 702 703 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 704 uint64_t /*Address*/, 705 const void *Decoder) { 706 unsigned Register = 0; 707 switch (RegNo) { 708 case 0: 709 Register = Hexagon::M0; 710 break; 711 case 1: 712 Register = Hexagon::M1; 713 break; 714 default: 715 return MCDisassembler::Fail; 716 } 717 Inst.addOperand(MCOperand::createReg(Register)); 718 return MCDisassembler::Success; 719 } 720 721 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 722 uint64_t /*Address*/, 723 const void *Decoder) { 724 HexagonDisassembler const &Disassembler = disassembler(Decoder); 725 int64_t FullValue = fullValue(Disassembler, MI, tmp); 726 assert(FullValue >= 0 && "Negative in unsigned decoder"); 727 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 728 return MCDisassembler::Success; 729 } 730 731 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 732 uint64_t /*Address*/, const void *Decoder) { 733 HexagonDisassembler const &Disassembler = disassembler(Decoder); 734 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 735 tmp = SignExtend64(tmp, Bits); 736 signedDecoder<32>(MI, tmp, Decoder); 737 return MCDisassembler::Success; 738 } 739 740 // custom decoder for various jump/call immediates 741 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 742 const void *Decoder) { 743 HexagonDisassembler const &Disassembler = disassembler(Decoder); 744 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 745 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 746 if (Bits == 0) 747 Bits = 15; 748 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits)); 749 uint32_t Extended = FullValue + Address; 750 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) 751 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 752 return MCDisassembler::Success; 753 } 754 755 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, 756 uint64_t /*Address*/, 757 const void *Decoder) { 758 using namespace Hexagon; 759 760 static const MCPhysReg GuestRegDecoderTable[] = { 761 /* 0 */ GELR, GSR, GOSP, G3, 762 /* 4 */ G4, G5, G6, G7, 763 /* 8 */ G8, G9, G10, G11, 764 /* 12 */ G12, G13, G14, G15, 765 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7, 766 /* 20 */ G20, G21, G22, G23, 767 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1, 768 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31 769 }; 770 771 if (RegNo >= array_lengthof(GuestRegDecoderTable)) 772 return MCDisassembler::Fail; 773 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister) 774 return MCDisassembler::Fail; 775 776 unsigned Register = GuestRegDecoderTable[RegNo]; 777 Inst.addOperand(MCOperand::createReg(Register)); 778 return MCDisassembler::Success; 779 } 780 781 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 782 uint64_t /*Address*/, 783 const void *Decoder) { 784 using namespace Hexagon; 785 786 static const MCPhysReg GuestReg64DecoderTable[] = { 787 /* 0 */ G1_0, 0, G3_2, 0, 788 /* 4 */ G5_4, 0, G7_6, 0, 789 /* 8 */ G9_8, 0, G11_10, 0, 790 /* 12 */ G13_12, 0, G15_14, 0, 791 /* 16 */ G17_16, 0, G19_18, 0, 792 /* 20 */ G21_20, 0, G23_22, 0, 793 /* 24 */ G25_24, 0, G27_26, 0, 794 /* 28 */ G29_28, 0, G31_30, 0 795 }; 796 797 if (RegNo >= array_lengthof(GuestReg64DecoderTable)) 798 return MCDisassembler::Fail; 799 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister) 800 return MCDisassembler::Fail; 801 802 unsigned Register = GuestReg64DecoderTable[RegNo]; 803 Inst.addOperand(MCOperand::createReg(Register)); 804 return MCDisassembler::Success; 805 } 806