1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCTargetDesc.h" 16 #include "MCTargetDesc/HexagonMCInstrInfo.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include <cassert> 31 #include <cstddef> 32 #include <cstdint> 33 #include <memory> 34 35 using namespace llvm; 36 using namespace Hexagon; 37 38 typedef MCDisassembler::DecodeStatus DecodeStatus; 39 40 namespace { 41 42 /// \brief Hexagon disassembler for all Hexagon platforms. 43 class HexagonDisassembler : public MCDisassembler { 44 public: 45 std::unique_ptr<MCInstrInfo const> const MCII; 46 std::unique_ptr<MCInst *> CurrentBundle; 47 48 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 49 MCInstrInfo const *MCII) 50 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} 51 52 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 53 ArrayRef<uint8_t> Bytes, uint64_t Address, 54 raw_ostream &VStream, raw_ostream &CStream, 55 bool &Complete) const; 56 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 57 ArrayRef<uint8_t> Bytes, uint64_t Address, 58 raw_ostream &VStream, 59 raw_ostream &CStream) const override; 60 61 void adjustExtendedInstructions(MCInst &MCI, MCInst const &MCB) const; 62 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; 63 }; 64 65 } // end anonymous namespace 66 67 // Forward declare these because the auto-generated code will reference them. 68 // Definitions are further down. 69 70 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 71 uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 101 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn); 102 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, 103 void const *Decoder); 104 105 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 106 raw_ostream &os); 107 108 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg); 109 110 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 113 const void *Decoder); 114 static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 115 const void *Decoder); 116 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 117 const void *Decoder); 118 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 119 const void *Decoder); 120 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 121 const void *Decoder); 122 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 125 const void *Decoder); 126 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 131 const void *Decoder); 132 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 133 const void *Decoder); 134 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 135 const void *Decoder); 136 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 137 const void *Decoder); 138 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 139 const void *Decoder); 140 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 141 const void *Decoder); 142 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 143 const void *Decoder); 144 145 #include "HexagonGenDisassemblerTables.inc" 146 147 static MCDisassembler *createHexagonDisassembler(const Target &T, 148 const MCSubtargetInfo &STI, 149 MCContext &Ctx) { 150 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 151 } 152 153 extern "C" void LLVMInitializeHexagonDisassembler() { 154 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 155 createHexagonDisassembler); 156 } 157 158 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 159 ArrayRef<uint8_t> Bytes, 160 uint64_t Address, 161 raw_ostream &os, 162 raw_ostream &cs) const { 163 DecodeStatus Result = DecodeStatus::Success; 164 bool Complete = false; 165 Size = 0; 166 167 *CurrentBundle = &MI; 168 MI = HexagonMCInstrInfo::createBundle(); 169 while (Result == Success && !Complete) { 170 if (Bytes.size() < HEXAGON_INSTR_SIZE) 171 return MCDisassembler::Fail; 172 MCInst *Inst = new (getContext()) MCInst; 173 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 174 MI.addOperand(MCOperand::createInst(Inst)); 175 Size += HEXAGON_INSTR_SIZE; 176 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 177 } 178 if(Result == MCDisassembler::Fail) 179 return Result; 180 HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo()); 181 if(!Checker.check()) 182 return MCDisassembler::Fail; 183 return MCDisassembler::Success; 184 } 185 186 static HexagonDisassembler const &disassembler(void const *Decoder) { 187 return *static_cast<HexagonDisassembler const *>(Decoder); 188 } 189 190 static MCContext &contextFromDecoder(void const *Decoder) { 191 return disassembler(Decoder).getContext(); 192 } 193 194 DecodeStatus HexagonDisassembler::getSingleInstruction( 195 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 196 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 197 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 198 199 uint32_t Instruction = 200 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 201 202 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 203 if ((Instruction & HexagonII::INST_PARSE_MASK) == 204 HexagonII::INST_PARSE_LOOP_END) { 205 if (BundleSize == 0) 206 HexagonMCInstrInfo::setInnerLoop(MCB); 207 else if (BundleSize == 1) 208 HexagonMCInstrInfo::setOuterLoop(MCB); 209 else 210 return DecodeStatus::Fail; 211 } 212 213 DecodeStatus Result = DecodeStatus::Success; 214 if ((Instruction & HexagonII::INST_PARSE_MASK) == 215 HexagonII::INST_PARSE_DUPLEX) { 216 // Determine the instruction class of each instruction in the duplex. 217 unsigned duplexIClass, IClassLow, IClassHigh; 218 219 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 220 switch (duplexIClass) { 221 default: 222 return MCDisassembler::Fail; 223 case 0: 224 IClassLow = HexagonII::HSIG_L1; 225 IClassHigh = HexagonII::HSIG_L1; 226 break; 227 case 1: 228 IClassLow = HexagonII::HSIG_L2; 229 IClassHigh = HexagonII::HSIG_L1; 230 break; 231 case 2: 232 IClassLow = HexagonII::HSIG_L2; 233 IClassHigh = HexagonII::HSIG_L2; 234 break; 235 case 3: 236 IClassLow = HexagonII::HSIG_A; 237 IClassHigh = HexagonII::HSIG_A; 238 break; 239 case 4: 240 IClassLow = HexagonII::HSIG_L1; 241 IClassHigh = HexagonII::HSIG_A; 242 break; 243 case 5: 244 IClassLow = HexagonII::HSIG_L2; 245 IClassHigh = HexagonII::HSIG_A; 246 break; 247 case 6: 248 IClassLow = HexagonII::HSIG_S1; 249 IClassHigh = HexagonII::HSIG_A; 250 break; 251 case 7: 252 IClassLow = HexagonII::HSIG_S2; 253 IClassHigh = HexagonII::HSIG_A; 254 break; 255 case 8: 256 IClassLow = HexagonII::HSIG_S1; 257 IClassHigh = HexagonII::HSIG_L1; 258 break; 259 case 9: 260 IClassLow = HexagonII::HSIG_S1; 261 IClassHigh = HexagonII::HSIG_L2; 262 break; 263 case 10: 264 IClassLow = HexagonII::HSIG_S1; 265 IClassHigh = HexagonII::HSIG_S1; 266 break; 267 case 11: 268 IClassLow = HexagonII::HSIG_S2; 269 IClassHigh = HexagonII::HSIG_S1; 270 break; 271 case 12: 272 IClassLow = HexagonII::HSIG_S2; 273 IClassHigh = HexagonII::HSIG_L1; 274 break; 275 case 13: 276 IClassLow = HexagonII::HSIG_S2; 277 IClassHigh = HexagonII::HSIG_L2; 278 break; 279 case 14: 280 IClassLow = HexagonII::HSIG_S2; 281 IClassHigh = HexagonII::HSIG_S2; 282 break; 283 } 284 285 // Set the MCInst to be a duplex instruction. Which one doesn't matter. 286 MI.setOpcode(Hexagon::DuplexIClass0); 287 288 // Decode each instruction in the duplex. 289 // Create an MCInst for each instruction. 290 unsigned instLow = Instruction & 0x1fff; 291 unsigned instHigh = (Instruction >> 16) & 0x1fff; 292 unsigned opLow; 293 if (GetSubinstOpcode(IClassLow, instLow, opLow, os) != 294 MCDisassembler::Success) 295 return MCDisassembler::Fail; 296 unsigned opHigh; 297 if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) != 298 MCDisassembler::Success) 299 return MCDisassembler::Fail; 300 MCInst *MILow = new (getContext()) MCInst; 301 MILow->setOpcode(opLow); 302 MCInst *MIHigh = new (getContext()) MCInst; 303 MIHigh->setOpcode(opHigh); 304 addSubinstOperands(MILow, opLow, instLow); 305 addSubinstOperands(MIHigh, opHigh, instHigh); 306 // see ConvertToSubInst() in 307 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 308 309 // Add the duplex instruction MCInsts as operands to the passed in MCInst. 310 MCOperand OPLow = MCOperand::createInst(MILow); 311 MCOperand OPHigh = MCOperand::createInst(MIHigh); 312 MI.addOperand(OPLow); 313 MI.addOperand(OPHigh); 314 Complete = true; 315 } else { 316 if ((Instruction & HexagonII::INST_PARSE_MASK) == 317 HexagonII::INST_PARSE_PACKET_END) 318 Complete = true; 319 // Calling the auto-generated decoder function. 320 Result = 321 decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); 322 323 // If a, "standard" insn isn't found check special cases. 324 if (MCDisassembler::Success != Result || 325 MI.getOpcode() == Hexagon::A4_ext) { 326 Result = decodeImmext(MI, Instruction, this); 327 if (MCDisassembler::Success != Result) { 328 Result = decodeSpecial(MI, Instruction); 329 } 330 } else { 331 // If the instruction is a compound instruction, register values will 332 // follow the duplex model, so the register values in the MCInst are 333 // incorrect. If the instruction is a compound, loop through the 334 // operands and change registers appropriately. 335 if (HexagonMCInstrInfo::getType(*MCII, MI) == HexagonII::TypeCOMPOUND) { 336 for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) { 337 if (i->isReg()) { 338 unsigned reg = i->getReg() - Hexagon::R0; 339 i->setReg(getRegFromSubinstEncoding(reg)); 340 } 341 } 342 } 343 } 344 } 345 346 switch(MI.getOpcode()) { 347 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 348 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 349 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 350 case Hexagon::J4_cmpeqn1_fp0_jump_t: 351 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 352 case Hexagon::J4_cmpeqn1_fp1_jump_t: 353 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 354 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 355 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 356 case Hexagon::J4_cmpeqn1_tp0_jump_t: 357 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 358 case Hexagon::J4_cmpeqn1_tp1_jump_t: 359 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 360 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 361 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 362 case Hexagon::J4_cmpgtn1_fp0_jump_t: 363 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 364 case Hexagon::J4_cmpgtn1_fp1_jump_t: 365 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 366 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 367 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 368 case Hexagon::J4_cmpgtn1_tp0_jump_t: 369 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 370 case Hexagon::J4_cmpgtn1_tp1_jump_t: 371 MI.insert(MI.begin() + 1, MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 372 break; 373 default: 374 break; 375 } 376 377 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 378 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 379 MCOperand &MCO = MI.getOperand(OpIndex); 380 assert(MCO.isReg() && "New value consumers must be registers"); 381 unsigned Register = 382 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 383 if ((Register & 0x6) == 0) 384 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 385 return MCDisassembler::Fail; 386 unsigned Lookback = (Register & 0x6) >> 1; 387 unsigned Offset = 1; 388 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 389 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 390 auto i = Instructions.end() - 1; 391 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 392 if (i == n) 393 // Couldn't find producer 394 return MCDisassembler::Fail; 395 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) 396 // Skip scalars when calculating distances for vectors 397 ++Lookback; 398 if (HexagonMCInstrInfo::isImmext(*i->getInst())) 399 ++Lookback; 400 if (Offset == Lookback) 401 break; 402 } 403 auto const &Inst = *i->getInst(); 404 bool SubregBit = (Register & 0x1) != 0; 405 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 406 // If subreg bit is set we're selecting the second produced newvalue 407 unsigned Producer = 408 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 409 assert(Producer != Hexagon::NoRegister); 410 MCO.setReg(Producer); 411 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 412 unsigned Producer = 413 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 414 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 415 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 416 else if (SubregBit) 417 // Hexagon PRM 10.11 New-value operands 418 // Nt[0] is reserved and should always be encoded as zero. 419 return MCDisassembler::Fail; 420 assert(Producer != Hexagon::NoRegister); 421 MCO.setReg(Producer); 422 } else 423 return MCDisassembler::Fail; 424 } 425 426 adjustExtendedInstructions(MI, MCB); 427 MCInst const *Extender = 428 HexagonMCInstrInfo::extenderForIndex(MCB, 429 HexagonMCInstrInfo::bundleSize(MCB)); 430 if(Extender != nullptr) { 431 MCInst const & Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ? 432 *MI.getOperand(1).getInst() : MI; 433 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 434 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 435 return MCDisassembler::Fail; 436 } 437 return Result; 438 } 439 440 void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI, 441 MCInst const &MCB) const { 442 if (!HexagonMCInstrInfo::hasExtenderForIndex( 443 MCB, HexagonMCInstrInfo::bundleSize(MCB))) { 444 unsigned opcode; 445 // This code is used by the disassembler to disambiguate between GP 446 // relative and absolute addressing instructions since they both have 447 // same encoding bits. However, an absolute addressing instruction must 448 // follow an immediate extender. Disassembler alwaus select absolute 449 // addressing instructions first and uses this code to change them into 450 // GP relative instruction in the absence of the corresponding immediate 451 // extender. 452 switch (MCI.getOpcode()) { 453 case Hexagon::PS_storerbabs: 454 opcode = Hexagon::S2_storerbgp; 455 break; 456 case Hexagon::PS_storerhabs: 457 opcode = Hexagon::S2_storerhgp; 458 break; 459 case Hexagon::PS_storerfabs: 460 opcode = Hexagon::S2_storerfgp; 461 break; 462 case Hexagon::PS_storeriabs: 463 opcode = Hexagon::S2_storerigp; 464 break; 465 case Hexagon::PS_storerbnewabs: 466 opcode = Hexagon::S2_storerbnewgp; 467 break; 468 case Hexagon::PS_storerhnewabs: 469 opcode = Hexagon::S2_storerhnewgp; 470 break; 471 case Hexagon::PS_storerinewabs: 472 opcode = Hexagon::S2_storerinewgp; 473 break; 474 case Hexagon::PS_storerdabs: 475 opcode = Hexagon::S2_storerdgp; 476 break; 477 case Hexagon::PS_loadrbabs: 478 opcode = Hexagon::L2_loadrbgp; 479 break; 480 case Hexagon::PS_loadrubabs: 481 opcode = Hexagon::L2_loadrubgp; 482 break; 483 case Hexagon::PS_loadrhabs: 484 opcode = Hexagon::L2_loadrhgp; 485 break; 486 case Hexagon::PS_loadruhabs: 487 opcode = Hexagon::L2_loadruhgp; 488 break; 489 case Hexagon::PS_loadriabs: 490 opcode = Hexagon::L2_loadrigp; 491 break; 492 case Hexagon::PS_loadrdabs: 493 opcode = Hexagon::L2_loadrdgp; 494 break; 495 default: 496 opcode = MCI.getOpcode(); 497 } 498 MCI.setOpcode(opcode); 499 } 500 } 501 502 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 503 ArrayRef<MCPhysReg> Table) { 504 if (RegNo < Table.size()) { 505 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 506 return MCDisassembler::Success; 507 } 508 509 return MCDisassembler::Fail; 510 } 511 512 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 513 uint64_t Address, 514 const void *Decoder) { 515 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 516 } 517 518 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 519 uint64_t Address, 520 const void *Decoder) { 521 static const MCPhysReg IntRegDecoderTable[] = { 522 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 523 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 524 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 525 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 526 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 527 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 528 Hexagon::R30, Hexagon::R31}; 529 530 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 531 } 532 533 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 534 uint64_t /*Address*/, 535 const void *Decoder) { 536 static const MCPhysReg VecRegDecoderTable[] = { 537 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 538 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 539 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 540 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 541 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 542 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 543 Hexagon::V30, Hexagon::V31}; 544 545 return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable); 546 } 547 548 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 549 uint64_t /*Address*/, 550 const void *Decoder) { 551 static const MCPhysReg DoubleRegDecoderTable[] = { 552 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 553 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 554 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 555 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 556 557 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 558 } 559 560 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 561 uint64_t /*Address*/, 562 const void *Decoder) { 563 static const MCPhysReg VecDblRegDecoderTable[] = { 564 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 565 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 566 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 567 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 568 569 return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable)); 570 } 571 572 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 573 uint64_t /*Address*/, 574 const void *Decoder) { 575 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 576 Hexagon::P2, Hexagon::P3}; 577 578 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 579 } 580 581 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 582 uint64_t /*Address*/, 583 const void *Decoder) { 584 static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 585 Hexagon::Q2, Hexagon::Q3}; 586 587 return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable); 588 } 589 590 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 591 uint64_t /*Address*/, 592 const void *Decoder) { 593 static const MCPhysReg CtrlRegDecoderTable[] = { 594 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, 595 Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7, 596 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, 597 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC 598 }; 599 600 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 601 return MCDisassembler::Fail; 602 603 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister) 604 return MCDisassembler::Fail; 605 606 unsigned Register = CtrlRegDecoderTable[RegNo]; 607 Inst.addOperand(MCOperand::createReg(Register)); 608 return MCDisassembler::Success; 609 } 610 611 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 612 uint64_t /*Address*/, 613 const void *Decoder) { 614 static const MCPhysReg CtrlReg64DecoderTable[] = { 615 Hexagon::C1_0, Hexagon::NoRegister, 616 Hexagon::C3_2, Hexagon::NoRegister, 617 Hexagon::C7_6, Hexagon::NoRegister, 618 Hexagon::C9_8, Hexagon::NoRegister, 619 Hexagon::C11_10, Hexagon::NoRegister, 620 Hexagon::CS, Hexagon::NoRegister, 621 Hexagon::UPC, Hexagon::NoRegister 622 }; 623 624 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 625 return MCDisassembler::Fail; 626 627 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister) 628 return MCDisassembler::Fail; 629 630 unsigned Register = CtrlReg64DecoderTable[RegNo]; 631 Inst.addOperand(MCOperand::createReg(Register)); 632 return MCDisassembler::Success; 633 } 634 635 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 636 uint64_t /*Address*/, 637 const void *Decoder) { 638 unsigned Register = 0; 639 switch (RegNo) { 640 case 0: 641 Register = Hexagon::M0; 642 break; 643 case 1: 644 Register = Hexagon::M1; 645 break; 646 default: 647 return MCDisassembler::Fail; 648 } 649 Inst.addOperand(MCOperand::createReg(Register)); 650 return MCDisassembler::Success; 651 } 652 653 static uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, 654 int64_t Value) { 655 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 656 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 657 if(!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 658 return Value; 659 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 660 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 661 int64_t Bits; 662 bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); 663 assert(Success);(void)Success; 664 uint32_t Upper26 = static_cast<uint32_t>(Bits); 665 uint32_t Operand = Upper26 | Lower6; 666 return Operand; 667 } 668 669 template <size_t T> 670 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 671 HexagonDisassembler const &Disassembler = disassembler(Decoder); 672 int64_t FullValue = fullValue(*Disassembler.MCII, 673 **Disassembler.CurrentBundle, 674 MI, SignExtend64<T>(tmp)); 675 int64_t Extended = SignExtend64<32>(FullValue); 676 HexagonMCInstrInfo::addConstant(MI, Extended, 677 Disassembler.getContext()); 678 } 679 680 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 681 uint64_t /*Address*/, 682 const void *Decoder) { 683 HexagonDisassembler const &Disassembler = disassembler(Decoder); 684 int64_t FullValue = fullValue(*Disassembler.MCII, 685 **Disassembler.CurrentBundle, 686 MI, tmp); 687 assert(FullValue >= 0 && "Negative in unsigned decoder"); 688 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 689 return MCDisassembler::Success; 690 } 691 692 static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, 693 uint64_t /*Address*/, const void *Decoder) { 694 signedDecoder<16>(MI, tmp, Decoder); 695 return MCDisassembler::Success; 696 } 697 698 static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, 699 uint64_t /*Address*/, const void *Decoder) { 700 signedDecoder<12>(MI, tmp, Decoder); 701 return MCDisassembler::Success; 702 } 703 704 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, 705 uint64_t /*Address*/, const void *Decoder) { 706 signedDecoder<11>(MI, tmp, Decoder); 707 return MCDisassembler::Success; 708 } 709 710 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, 711 uint64_t /*Address*/, const void *Decoder) { 712 HexagonMCInstrInfo::addConstant(MI, SignExtend64<12>(tmp), contextFromDecoder(Decoder)); 713 return MCDisassembler::Success; 714 } 715 716 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, 717 uint64_t /*Address*/, const void *Decoder) { 718 signedDecoder<13>(MI, tmp, Decoder); 719 return MCDisassembler::Success; 720 } 721 722 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, 723 uint64_t /*Address*/, const void *Decoder) { 724 signedDecoder<14>(MI, tmp, Decoder); 725 return MCDisassembler::Success; 726 } 727 728 static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, 729 uint64_t /*Address*/, const void *Decoder) { 730 signedDecoder<10>(MI, tmp, Decoder); 731 return MCDisassembler::Success; 732 } 733 734 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, 735 const void *Decoder) { 736 signedDecoder<8>(MI, tmp, Decoder); 737 return MCDisassembler::Success; 738 } 739 740 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, 741 uint64_t /*Address*/, const void *Decoder) { 742 signedDecoder<6>(MI, tmp, Decoder); 743 return MCDisassembler::Success; 744 } 745 746 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, 747 uint64_t /*Address*/, const void *Decoder) { 748 signedDecoder<4>(MI, tmp, Decoder); 749 return MCDisassembler::Success; 750 } 751 752 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, 753 uint64_t /*Address*/, const void *Decoder) { 754 signedDecoder<5>(MI, tmp, Decoder); 755 return MCDisassembler::Success; 756 } 757 758 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, 759 uint64_t /*Address*/, const void *Decoder) { 760 signedDecoder<6>(MI, tmp, Decoder); 761 return MCDisassembler::Success; 762 } 763 764 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, 765 uint64_t /*Address*/, const void *Decoder) { 766 signedDecoder<7>(MI, tmp, Decoder); 767 return MCDisassembler::Success; 768 } 769 770 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, 771 uint64_t /*Address*/, const void *Decoder) { 772 signedDecoder<10>(MI, tmp, Decoder); 773 return MCDisassembler::Success; 774 } 775 776 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, 777 uint64_t /*Address*/, const void *Decoder) { 778 signedDecoder<19>(MI, tmp, Decoder); 779 return MCDisassembler::Success; 780 } 781 782 // custom decoder for various jump/call immediates 783 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 784 const void *Decoder) { 785 HexagonDisassembler const &Disassembler = disassembler(Decoder); 786 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 787 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 788 if (Bits == 0) 789 Bits = 15; 790 uint32_t FullValue = fullValue(*Disassembler.MCII, 791 **Disassembler.CurrentBundle, 792 MI, SignExtend64(tmp, Bits)); 793 int64_t Extended = SignExtend64<32>(FullValue) + Address; 794 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 795 0, 4)) 796 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 797 return MCDisassembler::Success; 798 } 799 800 // Addressing mode dependent load store opcode map. 801 // - If an insn is preceded by an extender the address is absolute. 802 // - memw(##symbol) = r0 803 // - If an insn is not preceded by an extender the address is GP relative. 804 // - memw(gp + #symbol) = r0 805 // Please note that the instructions must be ordered in the descending order 806 // of their opcode. 807 // HexagonII::INST_ICLASS_ST 808 static const unsigned int StoreConditionalOpcodeData[][2] = { 809 {S4_pstorerdfnew_abs, 0xafc02084}, 810 {S4_pstorerdtnew_abs, 0xafc02080}, 811 {S4_pstorerdf_abs, 0xafc00084}, 812 {S4_pstorerdt_abs, 0xafc00080}, 813 {S4_pstorerinewfnew_abs, 0xafa03084}, 814 {S4_pstorerinewtnew_abs, 0xafa03080}, 815 {S4_pstorerhnewfnew_abs, 0xafa02884}, 816 {S4_pstorerhnewtnew_abs, 0xafa02880}, 817 {S4_pstorerbnewfnew_abs, 0xafa02084}, 818 {S4_pstorerbnewtnew_abs, 0xafa02080}, 819 {S4_pstorerinewf_abs, 0xafa01084}, 820 {S4_pstorerinewt_abs, 0xafa01080}, 821 {S4_pstorerhnewf_abs, 0xafa00884}, 822 {S4_pstorerhnewt_abs, 0xafa00880}, 823 {S4_pstorerbnewf_abs, 0xafa00084}, 824 {S4_pstorerbnewt_abs, 0xafa00080}, 825 {S4_pstorerifnew_abs, 0xaf802084}, 826 {S4_pstoreritnew_abs, 0xaf802080}, 827 {S4_pstorerif_abs, 0xaf800084}, 828 {S4_pstorerit_abs, 0xaf800080}, 829 {S4_pstorerhfnew_abs, 0xaf402084}, 830 {S4_pstorerhtnew_abs, 0xaf402080}, 831 {S4_pstorerhf_abs, 0xaf400084}, 832 {S4_pstorerht_abs, 0xaf400080}, 833 {S4_pstorerbfnew_abs, 0xaf002084}, 834 {S4_pstorerbtnew_abs, 0xaf002080}, 835 {S4_pstorerbf_abs, 0xaf000084}, 836 {S4_pstorerbt_abs, 0xaf000080}}; 837 // HexagonII::INST_ICLASS_LD 838 839 // HexagonII::INST_ICLASS_LD_ST_2 840 static unsigned int LoadStoreOpcodeData[][2] = {{PS_loadrdabs, 0x49c00000}, 841 {PS_loadriabs, 0x49800000}, 842 {PS_loadruhabs, 0x49600000}, 843 {PS_loadrhabs, 0x49400000}, 844 {PS_loadrubabs, 0x49200000}, 845 {PS_loadrbabs, 0x49000000}, 846 {PS_storerdabs, 0x48c00000}, 847 {PS_storerinewabs, 0x48a01000}, 848 {PS_storerhnewabs, 0x48a00800}, 849 {PS_storerbnewabs, 0x48a00000}, 850 {PS_storeriabs, 0x48800000}, 851 {PS_storerfabs, 0x48600000}, 852 {PS_storerhabs, 0x48400000}, 853 {PS_storerbabs, 0x48000000}}; 854 static const size_t NumCondS = array_lengthof(StoreConditionalOpcodeData); 855 static const size_t NumLS = array_lengthof(LoadStoreOpcodeData); 856 857 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) { 858 unsigned MachineOpcode = 0; 859 unsigned LLVMOpcode = 0; 860 861 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_ST) { 862 for (size_t i = 0; i < NumCondS; ++i) { 863 if ((insn & StoreConditionalOpcodeData[i][1]) == 864 StoreConditionalOpcodeData[i][1]) { 865 MachineOpcode = StoreConditionalOpcodeData[i][1]; 866 LLVMOpcode = StoreConditionalOpcodeData[i][0]; 867 break; 868 } 869 } 870 } 871 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_LD_ST_2) { 872 for (size_t i = 0; i < NumLS; ++i) { 873 if ((insn & LoadStoreOpcodeData[i][1]) == LoadStoreOpcodeData[i][1]) { 874 MachineOpcode = LoadStoreOpcodeData[i][1]; 875 LLVMOpcode = LoadStoreOpcodeData[i][0]; 876 break; 877 } 878 } 879 } 880 881 if (MachineOpcode) { 882 unsigned Value = 0; 883 unsigned shift = 0; 884 MI.setOpcode(LLVMOpcode); 885 // Remove the parse bits from the insn. 886 insn &= ~HexagonII::INST_PARSE_MASK; 887 888 switch (LLVMOpcode) { 889 default: 890 return MCDisassembler::Fail; 891 break; 892 893 case Hexagon::S4_pstorerdf_abs: 894 case Hexagon::S4_pstorerdt_abs: 895 case Hexagon::S4_pstorerdfnew_abs: 896 case Hexagon::S4_pstorerdtnew_abs: 897 // op: Pv 898 Value = insn & UINT64_C(3); 899 DecodePredRegsRegisterClass(MI, Value, 0, nullptr); 900 // op: u6 901 Value = (insn >> 12) & UINT64_C(48); 902 Value |= (insn >> 3) & UINT64_C(15); 903 MI.addOperand(MCOperand::createImm(Value)); 904 // op: Rtt 905 Value = (insn >> 8) & UINT64_C(31); 906 DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); 907 break; 908 909 case Hexagon::S4_pstorerbnewf_abs: 910 case Hexagon::S4_pstorerbnewt_abs: 911 case Hexagon::S4_pstorerbnewfnew_abs: 912 case Hexagon::S4_pstorerbnewtnew_abs: 913 case Hexagon::S4_pstorerhnewf_abs: 914 case Hexagon::S4_pstorerhnewt_abs: 915 case Hexagon::S4_pstorerhnewfnew_abs: 916 case Hexagon::S4_pstorerhnewtnew_abs: 917 case Hexagon::S4_pstorerinewf_abs: 918 case Hexagon::S4_pstorerinewt_abs: 919 case Hexagon::S4_pstorerinewfnew_abs: 920 case Hexagon::S4_pstorerinewtnew_abs: 921 // op: Pv 922 Value = insn & UINT64_C(3); 923 DecodePredRegsRegisterClass(MI, Value, 0, nullptr); 924 // op: u6 925 Value = (insn >> 12) & UINT64_C(48); 926 Value |= (insn >> 3) & UINT64_C(15); 927 MI.addOperand(MCOperand::createImm(Value)); 928 // op: Nt 929 Value = (insn >> 8) & UINT64_C(7); 930 DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); 931 break; 932 933 case Hexagon::S4_pstorerbf_abs: 934 case Hexagon::S4_pstorerbt_abs: 935 case Hexagon::S4_pstorerbfnew_abs: 936 case Hexagon::S4_pstorerbtnew_abs: 937 case Hexagon::S4_pstorerhf_abs: 938 case Hexagon::S4_pstorerht_abs: 939 case Hexagon::S4_pstorerhfnew_abs: 940 case Hexagon::S4_pstorerhtnew_abs: 941 case Hexagon::S4_pstorerif_abs: 942 case Hexagon::S4_pstorerit_abs: 943 case Hexagon::S4_pstorerifnew_abs: 944 case Hexagon::S4_pstoreritnew_abs: 945 // op: Pv 946 Value = insn & UINT64_C(3); 947 DecodePredRegsRegisterClass(MI, Value, 0, nullptr); 948 // op: u6 949 Value = (insn >> 12) & UINT64_C(48); 950 Value |= (insn >> 3) & UINT64_C(15); 951 MI.addOperand(MCOperand::createImm(Value)); 952 // op: Rt 953 Value = (insn >> 8) & UINT64_C(31); 954 DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); 955 break; 956 957 case Hexagon::L4_ploadrdf_abs: 958 case Hexagon::L4_ploadrdt_abs: 959 case Hexagon::L4_ploadrdfnew_abs: 960 case Hexagon::L4_ploadrdtnew_abs: 961 // op: Rdd 962 Value = insn & UINT64_C(31); 963 DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); 964 // op: Pt 965 Value = ((insn >> 9) & UINT64_C(3)); 966 DecodePredRegsRegisterClass(MI, Value, 0, nullptr); 967 // op: u6 968 Value = ((insn >> 15) & UINT64_C(62)); 969 Value |= ((insn >> 8) & UINT64_C(1)); 970 MI.addOperand(MCOperand::createImm(Value)); 971 break; 972 973 case Hexagon::L4_ploadrbf_abs: 974 case Hexagon::L4_ploadrbt_abs: 975 case Hexagon::L4_ploadrbfnew_abs: 976 case Hexagon::L4_ploadrbtnew_abs: 977 case Hexagon::L4_ploadrhf_abs: 978 case Hexagon::L4_ploadrht_abs: 979 case Hexagon::L4_ploadrhfnew_abs: 980 case Hexagon::L4_ploadrhtnew_abs: 981 case Hexagon::L4_ploadrubf_abs: 982 case Hexagon::L4_ploadrubt_abs: 983 case Hexagon::L4_ploadrubfnew_abs: 984 case Hexagon::L4_ploadrubtnew_abs: 985 case Hexagon::L4_ploadruhf_abs: 986 case Hexagon::L4_ploadruht_abs: 987 case Hexagon::L4_ploadruhfnew_abs: 988 case Hexagon::L4_ploadruhtnew_abs: 989 case Hexagon::L4_ploadrif_abs: 990 case Hexagon::L4_ploadrit_abs: 991 case Hexagon::L4_ploadrifnew_abs: 992 case Hexagon::L4_ploadritnew_abs: 993 // op: Rd 994 Value = insn & UINT64_C(31); 995 DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); 996 // op: Pt 997 Value = (insn >> 9) & UINT64_C(3); 998 DecodePredRegsRegisterClass(MI, Value, 0, nullptr); 999 // op: u6 1000 Value = (insn >> 15) & UINT64_C(62); 1001 Value |= (insn >> 8) & UINT64_C(1); 1002 MI.addOperand(MCOperand::createImm(Value)); 1003 break; 1004 1005 // op: g16_2 1006 case (Hexagon::PS_loadriabs): 1007 ++shift; 1008 // op: g16_1 1009 case Hexagon::PS_loadrhabs: 1010 case Hexagon::PS_loadruhabs: 1011 ++shift; 1012 // op: g16_0 1013 case Hexagon::PS_loadrbabs: 1014 case Hexagon::PS_loadrubabs: 1015 // op: Rd 1016 Value |= insn & UINT64_C(31); 1017 DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); 1018 Value = (insn >> 11) & UINT64_C(49152); 1019 Value |= (insn >> 7) & UINT64_C(15872); 1020 Value |= (insn >> 5) & UINT64_C(511); 1021 MI.addOperand(MCOperand::createImm(Value << shift)); 1022 break; 1023 1024 case Hexagon::PS_loadrdabs: 1025 Value = insn & UINT64_C(31); 1026 DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); 1027 Value = (insn >> 11) & UINT64_C(49152); 1028 Value |= (insn >> 7) & UINT64_C(15872); 1029 Value |= (insn >> 5) & UINT64_C(511); 1030 MI.addOperand(MCOperand::createImm(Value << 3)); 1031 break; 1032 1033 case Hexagon::PS_storerdabs: 1034 // op: g16_3 1035 Value = (insn >> 11) & UINT64_C(49152); 1036 Value |= (insn >> 7) & UINT64_C(15872); 1037 Value |= (insn >> 5) & UINT64_C(256); 1038 Value |= insn & UINT64_C(255); 1039 MI.addOperand(MCOperand::createImm(Value << 3)); 1040 // op: Rtt 1041 Value = (insn >> 8) & UINT64_C(31); 1042 DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); 1043 break; 1044 1045 // op: g16_2 1046 case Hexagon::PS_storerinewabs: 1047 ++shift; 1048 // op: g16_1 1049 case Hexagon::PS_storerhnewabs: 1050 ++shift; 1051 // op: g16_0 1052 case Hexagon::PS_storerbnewabs: 1053 Value = (insn >> 11) & UINT64_C(49152); 1054 Value |= (insn >> 7) & UINT64_C(15872); 1055 Value |= (insn >> 5) & UINT64_C(256); 1056 Value |= insn & UINT64_C(255); 1057 MI.addOperand(MCOperand::createImm(Value << shift)); 1058 // op: Nt 1059 Value = (insn >> 8) & UINT64_C(7); 1060 DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); 1061 break; 1062 1063 // op: g16_2 1064 case Hexagon::PS_storeriabs: 1065 ++shift; 1066 // op: g16_1 1067 case Hexagon::PS_storerhabs: 1068 case Hexagon::PS_storerfabs: 1069 ++shift; 1070 // op: g16_0 1071 case Hexagon::PS_storerbabs: 1072 Value = (insn >> 11) & UINT64_C(49152); 1073 Value |= (insn >> 7) & UINT64_C(15872); 1074 Value |= (insn >> 5) & UINT64_C(256); 1075 Value |= insn & UINT64_C(255); 1076 MI.addOperand(MCOperand::createImm(Value << shift)); 1077 // op: Rt 1078 Value = (insn >> 8) & UINT64_C(31); 1079 DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); 1080 break; 1081 } 1082 return MCDisassembler::Success; 1083 } 1084 return MCDisassembler::Fail; 1085 } 1086 1087 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, 1088 void const *Decoder) { 1089 // Instruction Class for a constant a extender: bits 31:28 = 0x0000 1090 if ((~insn & 0xf0000000) == 0xf0000000) { 1091 unsigned Value; 1092 // 27:16 High 12 bits of 26-bit extender. 1093 Value = (insn & 0x0fff0000) << 4; 1094 // 13:0 Low 14 bits of 26-bit extender. 1095 Value |= ((insn & 0x3fff) << 6); 1096 MI.setOpcode(Hexagon::A4_ext); 1097 HexagonMCInstrInfo::addConstant(MI, Value, contextFromDecoder(Decoder)); 1098 return MCDisassembler::Success; 1099 } 1100 return MCDisassembler::Fail; 1101 } 1102 1103 // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td 1104 enum subInstBinaryValues { 1105 SA1_addi_BITS = 0x0000, 1106 SA1_addi_MASK = 0x1800, 1107 SA1_addrx_BITS = 0x1800, 1108 SA1_addrx_MASK = 0x1f00, 1109 SA1_addsp_BITS = 0x0c00, 1110 SA1_addsp_MASK = 0x1c00, 1111 SA1_and1_BITS = 0x1200, 1112 SA1_and1_MASK = 0x1f00, 1113 SA1_clrf_BITS = 0x1a70, 1114 SA1_clrf_MASK = 0x1e70, 1115 SA1_clrfnew_BITS = 0x1a50, 1116 SA1_clrfnew_MASK = 0x1e70, 1117 SA1_clrt_BITS = 0x1a60, 1118 SA1_clrt_MASK = 0x1e70, 1119 SA1_clrtnew_BITS = 0x1a40, 1120 SA1_clrtnew_MASK = 0x1e70, 1121 SA1_cmpeqi_BITS = 0x1900, 1122 SA1_cmpeqi_MASK = 0x1f00, 1123 SA1_combine0i_BITS = 0x1c00, 1124 SA1_combine0i_MASK = 0x1d18, 1125 SA1_combine1i_BITS = 0x1c08, 1126 SA1_combine1i_MASK = 0x1d18, 1127 SA1_combine2i_BITS = 0x1c10, 1128 SA1_combine2i_MASK = 0x1d18, 1129 SA1_combine3i_BITS = 0x1c18, 1130 SA1_combine3i_MASK = 0x1d18, 1131 SA1_combinerz_BITS = 0x1d08, 1132 SA1_combinerz_MASK = 0x1d08, 1133 SA1_combinezr_BITS = 0x1d00, 1134 SA1_combinezr_MASK = 0x1d08, 1135 SA1_dec_BITS = 0x1300, 1136 SA1_dec_MASK = 0x1f00, 1137 SA1_inc_BITS = 0x1100, 1138 SA1_inc_MASK = 0x1f00, 1139 SA1_seti_BITS = 0x0800, 1140 SA1_seti_MASK = 0x1c00, 1141 SA1_setin1_BITS = 0x1a00, 1142 SA1_setin1_MASK = 0x1e40, 1143 SA1_sxtb_BITS = 0x1500, 1144 SA1_sxtb_MASK = 0x1f00, 1145 SA1_sxth_BITS = 0x1400, 1146 SA1_sxth_MASK = 0x1f00, 1147 SA1_tfr_BITS = 0x1000, 1148 SA1_tfr_MASK = 0x1f00, 1149 SA1_zxtb_BITS = 0x1700, 1150 SA1_zxtb_MASK = 0x1f00, 1151 SA1_zxth_BITS = 0x1600, 1152 SA1_zxth_MASK = 0x1f00, 1153 SL1_loadri_io_BITS = 0x0000, 1154 SL1_loadri_io_MASK = 0x1000, 1155 SL1_loadrub_io_BITS = 0x1000, 1156 SL1_loadrub_io_MASK = 0x1000, 1157 SL2_deallocframe_BITS = 0x1f00, 1158 SL2_deallocframe_MASK = 0x1fc0, 1159 SL2_jumpr31_BITS = 0x1fc0, 1160 SL2_jumpr31_MASK = 0x1fc4, 1161 SL2_jumpr31_f_BITS = 0x1fc5, 1162 SL2_jumpr31_f_MASK = 0x1fc7, 1163 SL2_jumpr31_fnew_BITS = 0x1fc7, 1164 SL2_jumpr31_fnew_MASK = 0x1fc7, 1165 SL2_jumpr31_t_BITS = 0x1fc4, 1166 SL2_jumpr31_t_MASK = 0x1fc7, 1167 SL2_jumpr31_tnew_BITS = 0x1fc6, 1168 SL2_jumpr31_tnew_MASK = 0x1fc7, 1169 SL2_loadrb_io_BITS = 0x1000, 1170 SL2_loadrb_io_MASK = 0x1800, 1171 SL2_loadrd_sp_BITS = 0x1e00, 1172 SL2_loadrd_sp_MASK = 0x1f00, 1173 SL2_loadrh_io_BITS = 0x0000, 1174 SL2_loadrh_io_MASK = 0x1800, 1175 SL2_loadri_sp_BITS = 0x1c00, 1176 SL2_loadri_sp_MASK = 0x1e00, 1177 SL2_loadruh_io_BITS = 0x0800, 1178 SL2_loadruh_io_MASK = 0x1800, 1179 SL2_return_BITS = 0x1f40, 1180 SL2_return_MASK = 0x1fc4, 1181 SL2_return_f_BITS = 0x1f45, 1182 SL2_return_f_MASK = 0x1fc7, 1183 SL2_return_fnew_BITS = 0x1f47, 1184 SL2_return_fnew_MASK = 0x1fc7, 1185 SL2_return_t_BITS = 0x1f44, 1186 SL2_return_t_MASK = 0x1fc7, 1187 SL2_return_tnew_BITS = 0x1f46, 1188 SL2_return_tnew_MASK = 0x1fc7, 1189 SS1_storeb_io_BITS = 0x1000, 1190 SS1_storeb_io_MASK = 0x1000, 1191 SS1_storew_io_BITS = 0x0000, 1192 SS1_storew_io_MASK = 0x1000, 1193 SS2_allocframe_BITS = 0x1c00, 1194 SS2_allocframe_MASK = 0x1e00, 1195 SS2_storebi0_BITS = 0x1200, 1196 SS2_storebi0_MASK = 0x1f00, 1197 SS2_storebi1_BITS = 0x1300, 1198 SS2_storebi1_MASK = 0x1f00, 1199 SS2_stored_sp_BITS = 0x0a00, 1200 SS2_stored_sp_MASK = 0x1e00, 1201 SS2_storeh_io_BITS = 0x0000, 1202 SS2_storeh_io_MASK = 0x1800, 1203 SS2_storew_sp_BITS = 0x0800, 1204 SS2_storew_sp_MASK = 0x1e00, 1205 SS2_storewi0_BITS = 0x1000, 1206 SS2_storewi0_MASK = 0x1f00, 1207 SS2_storewi1_BITS = 0x1100, 1208 SS2_storewi1_MASK = 0x1f00 1209 }; 1210 1211 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 1212 raw_ostream &os) { 1213 switch (IClass) { 1214 case HexagonII::HSIG_L1: 1215 if ((inst & SL1_loadri_io_MASK) == SL1_loadri_io_BITS) 1216 op = Hexagon::SL1_loadri_io; 1217 else if ((inst & SL1_loadrub_io_MASK) == SL1_loadrub_io_BITS) 1218 op = Hexagon::SL1_loadrub_io; 1219 else { 1220 os << "<unknown subinstruction>"; 1221 return MCDisassembler::Fail; 1222 } 1223 break; 1224 case HexagonII::HSIG_L2: 1225 if ((inst & SL2_deallocframe_MASK) == SL2_deallocframe_BITS) 1226 op = Hexagon::SL2_deallocframe; 1227 else if ((inst & SL2_jumpr31_MASK) == SL2_jumpr31_BITS) 1228 op = Hexagon::SL2_jumpr31; 1229 else if ((inst & SL2_jumpr31_f_MASK) == SL2_jumpr31_f_BITS) 1230 op = Hexagon::SL2_jumpr31_f; 1231 else if ((inst & SL2_jumpr31_fnew_MASK) == SL2_jumpr31_fnew_BITS) 1232 op = Hexagon::SL2_jumpr31_fnew; 1233 else if ((inst & SL2_jumpr31_t_MASK) == SL2_jumpr31_t_BITS) 1234 op = Hexagon::SL2_jumpr31_t; 1235 else if ((inst & SL2_jumpr31_tnew_MASK) == SL2_jumpr31_tnew_BITS) 1236 op = Hexagon::SL2_jumpr31_tnew; 1237 else if ((inst & SL2_loadrb_io_MASK) == SL2_loadrb_io_BITS) 1238 op = Hexagon::SL2_loadrb_io; 1239 else if ((inst & SL2_loadrd_sp_MASK) == SL2_loadrd_sp_BITS) 1240 op = Hexagon::SL2_loadrd_sp; 1241 else if ((inst & SL2_loadrh_io_MASK) == SL2_loadrh_io_BITS) 1242 op = Hexagon::SL2_loadrh_io; 1243 else if ((inst & SL2_loadri_sp_MASK) == SL2_loadri_sp_BITS) 1244 op = Hexagon::SL2_loadri_sp; 1245 else if ((inst & SL2_loadruh_io_MASK) == SL2_loadruh_io_BITS) 1246 op = Hexagon::SL2_loadruh_io; 1247 else if ((inst & SL2_return_MASK) == SL2_return_BITS) 1248 op = Hexagon::SL2_return; 1249 else if ((inst & SL2_return_f_MASK) == SL2_return_f_BITS) 1250 op = Hexagon::SL2_return_f; 1251 else if ((inst & SL2_return_fnew_MASK) == SL2_return_fnew_BITS) 1252 op = Hexagon::SL2_return_fnew; 1253 else if ((inst & SL2_return_t_MASK) == SL2_return_t_BITS) 1254 op = Hexagon::SL2_return_t; 1255 else if ((inst & SL2_return_tnew_MASK) == SL2_return_tnew_BITS) 1256 op = Hexagon::SL2_return_tnew; 1257 else { 1258 os << "<unknown subinstruction>"; 1259 return MCDisassembler::Fail; 1260 } 1261 break; 1262 case HexagonII::HSIG_A: 1263 if ((inst & SA1_addi_MASK) == SA1_addi_BITS) 1264 op = Hexagon::SA1_addi; 1265 else if ((inst & SA1_addrx_MASK) == SA1_addrx_BITS) 1266 op = Hexagon::SA1_addrx; 1267 else if ((inst & SA1_addsp_MASK) == SA1_addsp_BITS) 1268 op = Hexagon::SA1_addsp; 1269 else if ((inst & SA1_and1_MASK) == SA1_and1_BITS) 1270 op = Hexagon::SA1_and1; 1271 else if ((inst & SA1_clrf_MASK) == SA1_clrf_BITS) 1272 op = Hexagon::SA1_clrf; 1273 else if ((inst & SA1_clrfnew_MASK) == SA1_clrfnew_BITS) 1274 op = Hexagon::SA1_clrfnew; 1275 else if ((inst & SA1_clrt_MASK) == SA1_clrt_BITS) 1276 op = Hexagon::SA1_clrt; 1277 else if ((inst & SA1_clrtnew_MASK) == SA1_clrtnew_BITS) 1278 op = Hexagon::SA1_clrtnew; 1279 else if ((inst & SA1_cmpeqi_MASK) == SA1_cmpeqi_BITS) 1280 op = Hexagon::SA1_cmpeqi; 1281 else if ((inst & SA1_combine0i_MASK) == SA1_combine0i_BITS) 1282 op = Hexagon::SA1_combine0i; 1283 else if ((inst & SA1_combine1i_MASK) == SA1_combine1i_BITS) 1284 op = Hexagon::SA1_combine1i; 1285 else if ((inst & SA1_combine2i_MASK) == SA1_combine2i_BITS) 1286 op = Hexagon::SA1_combine2i; 1287 else if ((inst & SA1_combine3i_MASK) == SA1_combine3i_BITS) 1288 op = Hexagon::SA1_combine3i; 1289 else if ((inst & SA1_combinerz_MASK) == SA1_combinerz_BITS) 1290 op = Hexagon::SA1_combinerz; 1291 else if ((inst & SA1_combinezr_MASK) == SA1_combinezr_BITS) 1292 op = Hexagon::SA1_combinezr; 1293 else if ((inst & SA1_dec_MASK) == SA1_dec_BITS) 1294 op = Hexagon::SA1_dec; 1295 else if ((inst & SA1_inc_MASK) == SA1_inc_BITS) 1296 op = Hexagon::SA1_inc; 1297 else if ((inst & SA1_seti_MASK) == SA1_seti_BITS) 1298 op = Hexagon::SA1_seti; 1299 else if ((inst & SA1_setin1_MASK) == SA1_setin1_BITS) 1300 op = Hexagon::SA1_setin1; 1301 else if ((inst & SA1_sxtb_MASK) == SA1_sxtb_BITS) 1302 op = Hexagon::SA1_sxtb; 1303 else if ((inst & SA1_sxth_MASK) == SA1_sxth_BITS) 1304 op = Hexagon::SA1_sxth; 1305 else if ((inst & SA1_tfr_MASK) == SA1_tfr_BITS) 1306 op = Hexagon::SA1_tfr; 1307 else if ((inst & SA1_zxtb_MASK) == SA1_zxtb_BITS) 1308 op = Hexagon::SA1_zxtb; 1309 else if ((inst & SA1_zxth_MASK) == SA1_zxth_BITS) 1310 op = Hexagon::SA1_zxth; 1311 else { 1312 os << "<unknown subinstruction>"; 1313 return MCDisassembler::Fail; 1314 } 1315 break; 1316 case HexagonII::HSIG_S1: 1317 if ((inst & SS1_storeb_io_MASK) == SS1_storeb_io_BITS) 1318 op = Hexagon::SS1_storeb_io; 1319 else if ((inst & SS1_storew_io_MASK) == SS1_storew_io_BITS) 1320 op = Hexagon::SS1_storew_io; 1321 else { 1322 os << "<unknown subinstruction>"; 1323 return MCDisassembler::Fail; 1324 } 1325 break; 1326 case HexagonII::HSIG_S2: 1327 if ((inst & SS2_allocframe_MASK) == SS2_allocframe_BITS) 1328 op = Hexagon::SS2_allocframe; 1329 else if ((inst & SS2_storebi0_MASK) == SS2_storebi0_BITS) 1330 op = Hexagon::SS2_storebi0; 1331 else if ((inst & SS2_storebi1_MASK) == SS2_storebi1_BITS) 1332 op = Hexagon::SS2_storebi1; 1333 else if ((inst & SS2_stored_sp_MASK) == SS2_stored_sp_BITS) 1334 op = Hexagon::SS2_stored_sp; 1335 else if ((inst & SS2_storeh_io_MASK) == SS2_storeh_io_BITS) 1336 op = Hexagon::SS2_storeh_io; 1337 else if ((inst & SS2_storew_sp_MASK) == SS2_storew_sp_BITS) 1338 op = Hexagon::SS2_storew_sp; 1339 else if ((inst & SS2_storewi0_MASK) == SS2_storewi0_BITS) 1340 op = Hexagon::SS2_storewi0; 1341 else if ((inst & SS2_storewi1_MASK) == SS2_storewi1_BITS) 1342 op = Hexagon::SS2_storewi1; 1343 else { 1344 os << "<unknown subinstruction>"; 1345 return MCDisassembler::Fail; 1346 } 1347 break; 1348 default: 1349 os << "<unknown>"; 1350 return MCDisassembler::Fail; 1351 } 1352 return MCDisassembler::Success; 1353 } 1354 1355 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) { 1356 if (encoded_reg < 8) 1357 return Hexagon::R0 + encoded_reg; 1358 else if (encoded_reg < 16) 1359 return Hexagon::R0 + encoded_reg + 8; 1360 1361 // patently false value 1362 return Hexagon::NoRegister; 1363 } 1364 1365 static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) { 1366 if (encoded_dreg < 4) 1367 return Hexagon::D0 + encoded_dreg; 1368 else if (encoded_dreg < 8) 1369 return Hexagon::D0 + encoded_dreg + 4; 1370 1371 // patently false value 1372 return Hexagon::NoRegister; 1373 } 1374 1375 void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode, 1376 unsigned inst) const { 1377 int64_t operand; 1378 MCOperand Op; 1379 switch (opcode) { 1380 case Hexagon::SL2_deallocframe: 1381 case Hexagon::SL2_jumpr31: 1382 case Hexagon::SL2_jumpr31_f: 1383 case Hexagon::SL2_jumpr31_fnew: 1384 case Hexagon::SL2_jumpr31_t: 1385 case Hexagon::SL2_jumpr31_tnew: 1386 case Hexagon::SL2_return: 1387 case Hexagon::SL2_return_f: 1388 case Hexagon::SL2_return_fnew: 1389 case Hexagon::SL2_return_t: 1390 case Hexagon::SL2_return_tnew: 1391 // no operands for these instructions 1392 break; 1393 case Hexagon::SS2_allocframe: 1394 // u 8-4{5_3} 1395 operand = ((inst & 0x1f0) >> 4) << 3; 1396 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1397 break; 1398 case Hexagon::SL1_loadri_io: 1399 // Rd 3-0, Rs 7-4, u 11-8{4_2} 1400 operand = getRegFromSubinstEncoding(inst & 0xf); 1401 Op = MCOperand::createReg(operand); 1402 MI->addOperand(Op); 1403 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1404 Op = MCOperand::createReg(operand); 1405 MI->addOperand(Op); 1406 operand = (inst & 0xf00) >> 6; 1407 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1408 break; 1409 case Hexagon::SL1_loadrub_io: 1410 // Rd 3-0, Rs 7-4, u 11-8 1411 operand = getRegFromSubinstEncoding(inst & 0xf); 1412 Op = MCOperand::createReg(operand); 1413 MI->addOperand(Op); 1414 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1415 Op = MCOperand::createReg(operand); 1416 MI->addOperand(Op); 1417 operand = (inst & 0xf00) >> 8; 1418 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1419 break; 1420 case Hexagon::SL2_loadrb_io: 1421 // Rd 3-0, Rs 7-4, u 10-8 1422 operand = getRegFromSubinstEncoding(inst & 0xf); 1423 Op = MCOperand::createReg(operand); 1424 MI->addOperand(Op); 1425 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1426 Op = MCOperand::createReg(operand); 1427 MI->addOperand(Op); 1428 operand = (inst & 0x700) >> 8; 1429 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1430 break; 1431 case Hexagon::SL2_loadrh_io: 1432 case Hexagon::SL2_loadruh_io: 1433 // Rd 3-0, Rs 7-4, u 10-8{3_1} 1434 operand = getRegFromSubinstEncoding(inst & 0xf); 1435 Op = MCOperand::createReg(operand); 1436 MI->addOperand(Op); 1437 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1438 Op = MCOperand::createReg(operand); 1439 MI->addOperand(Op); 1440 operand = ((inst & 0x700) >> 8) << 1; 1441 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1442 break; 1443 case Hexagon::SL2_loadrd_sp: 1444 // Rdd 2-0, u 7-3{5_3} 1445 operand = getDRegFromSubinstEncoding(inst & 0x7); 1446 Op = MCOperand::createReg(operand); 1447 MI->addOperand(Op); 1448 operand = ((inst & 0x0f8) >> 3) << 3; 1449 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1450 break; 1451 case Hexagon::SL2_loadri_sp: 1452 // Rd 3-0, u 8-4{5_2} 1453 operand = getRegFromSubinstEncoding(inst & 0xf); 1454 Op = MCOperand::createReg(operand); 1455 MI->addOperand(Op); 1456 operand = ((inst & 0x1f0) >> 4) << 2; 1457 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1458 break; 1459 case Hexagon::SA1_addi: 1460 // Rx 3-0 (x2), s7 10-4 1461 operand = getRegFromSubinstEncoding(inst & 0xf); 1462 Op = MCOperand::createReg(operand); 1463 MI->addOperand(Op); 1464 MI->addOperand(Op); 1465 operand = SignExtend64<7>((inst & 0x7f0) >> 4); 1466 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1467 break; 1468 case Hexagon::SA1_addrx: 1469 // Rx 3-0 (x2), Rs 7-4 1470 operand = getRegFromSubinstEncoding(inst & 0xf); 1471 Op = MCOperand::createReg(operand); 1472 MI->addOperand(Op); 1473 MI->addOperand(Op); 1474 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1475 Op = MCOperand::createReg(operand); 1476 MI->addOperand(Op); 1477 break; 1478 case Hexagon::SA1_and1: 1479 case Hexagon::SA1_dec: 1480 case Hexagon::SA1_inc: 1481 case Hexagon::SA1_sxtb: 1482 case Hexagon::SA1_sxth: 1483 case Hexagon::SA1_tfr: 1484 case Hexagon::SA1_zxtb: 1485 case Hexagon::SA1_zxth: 1486 // Rd 3-0, Rs 7-4 1487 operand = getRegFromSubinstEncoding(inst & 0xf); 1488 Op = MCOperand::createReg(operand); 1489 MI->addOperand(Op); 1490 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1491 Op = MCOperand::createReg(operand); 1492 MI->addOperand(Op); 1493 break; 1494 case Hexagon::SA1_addsp: 1495 // Rd 3-0, u 9-4{6_2} 1496 operand = getRegFromSubinstEncoding(inst & 0xf); 1497 Op = MCOperand::createReg(operand); 1498 MI->addOperand(Op); 1499 operand = ((inst & 0x3f0) >> 4) << 2; 1500 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1501 break; 1502 case Hexagon::SA1_seti: 1503 // Rd 3-0, u 9-4 1504 operand = getRegFromSubinstEncoding(inst & 0xf); 1505 Op = MCOperand::createReg(operand); 1506 MI->addOperand(Op); 1507 operand = (inst & 0x3f0) >> 4; 1508 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1509 break; 1510 case Hexagon::SA1_clrf: 1511 case Hexagon::SA1_clrfnew: 1512 case Hexagon::SA1_clrt: 1513 case Hexagon::SA1_clrtnew: 1514 case Hexagon::SA1_setin1: 1515 // Rd 3-0 1516 operand = getRegFromSubinstEncoding(inst & 0xf); 1517 Op = MCOperand::createReg(operand); 1518 MI->addOperand(Op); 1519 if (opcode == Hexagon::SA1_setin1) 1520 break; 1521 MI->addOperand(MCOperand::createReg(Hexagon::P0)); 1522 break; 1523 case Hexagon::SA1_cmpeqi: 1524 // Rs 7-4, u 1-0 1525 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1526 Op = MCOperand::createReg(operand); 1527 MI->addOperand(Op); 1528 operand = inst & 0x3; 1529 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1530 break; 1531 case Hexagon::SA1_combine0i: 1532 case Hexagon::SA1_combine1i: 1533 case Hexagon::SA1_combine2i: 1534 case Hexagon::SA1_combine3i: 1535 // Rdd 2-0, u 6-5 1536 operand = getDRegFromSubinstEncoding(inst & 0x7); 1537 Op = MCOperand::createReg(operand); 1538 MI->addOperand(Op); 1539 operand = (inst & 0x060) >> 5; 1540 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1541 break; 1542 case Hexagon::SA1_combinerz: 1543 case Hexagon::SA1_combinezr: 1544 // Rdd 2-0, Rs 7-4 1545 operand = getDRegFromSubinstEncoding(inst & 0x7); 1546 Op = MCOperand::createReg(operand); 1547 MI->addOperand(Op); 1548 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1549 Op = MCOperand::createReg(operand); 1550 MI->addOperand(Op); 1551 break; 1552 case Hexagon::SS1_storeb_io: 1553 // Rs 7-4, u 11-8, Rt 3-0 1554 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1555 Op = MCOperand::createReg(operand); 1556 MI->addOperand(Op); 1557 operand = (inst & 0xf00) >> 8; 1558 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1559 operand = getRegFromSubinstEncoding(inst & 0xf); 1560 Op = MCOperand::createReg(operand); 1561 MI->addOperand(Op); 1562 break; 1563 case Hexagon::SS1_storew_io: 1564 // Rs 7-4, u 11-8{4_2}, Rt 3-0 1565 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1566 Op = MCOperand::createReg(operand); 1567 MI->addOperand(Op); 1568 operand = ((inst & 0xf00) >> 8) << 2; 1569 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1570 operand = getRegFromSubinstEncoding(inst & 0xf); 1571 Op = MCOperand::createReg(operand); 1572 MI->addOperand(Op); 1573 break; 1574 case Hexagon::SS2_storebi0: 1575 case Hexagon::SS2_storebi1: 1576 // Rs 7-4, u 3-0 1577 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1578 Op = MCOperand::createReg(operand); 1579 MI->addOperand(Op); 1580 operand = inst & 0xf; 1581 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1582 break; 1583 case Hexagon::SS2_storewi0: 1584 case Hexagon::SS2_storewi1: 1585 // Rs 7-4, u 3-0{4_2} 1586 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1587 Op = MCOperand::createReg(operand); 1588 MI->addOperand(Op); 1589 operand = (inst & 0xf) << 2; 1590 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1591 break; 1592 case Hexagon::SS2_stored_sp: 1593 // s 8-3{6_3}, Rtt 2-0 1594 operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3); 1595 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1596 operand = getDRegFromSubinstEncoding(inst & 0x7); 1597 Op = MCOperand::createReg(operand); 1598 MI->addOperand(Op); 1599 break; 1600 case Hexagon::SS2_storeh_io: 1601 // Rs 7-4, u 10-8{3_1}, Rt 3-0 1602 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1603 Op = MCOperand::createReg(operand); 1604 MI->addOperand(Op); 1605 operand = ((inst & 0x700) >> 8) << 1; 1606 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1607 operand = getRegFromSubinstEncoding(inst & 0xf); 1608 Op = MCOperand::createReg(operand); 1609 MI->addOperand(Op); 1610 break; 1611 case Hexagon::SS2_storew_sp: 1612 // u 8-4{5_2}, Rd 3-0 1613 operand = ((inst & 0x1f0) >> 4) << 2; 1614 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1615 operand = getRegFromSubinstEncoding(inst & 0xf); 1616 Op = MCOperand::createReg(operand); 1617 MI->addOperand(Op); 1618 break; 1619 default: 1620 // don't crash with an invalid subinstruction 1621 // llvm_unreachable("Invalid subinstruction in duplex instruction"); 1622 break; 1623 } 1624 } 1625