1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCTargetDesc.h" 16 #include "MCTargetDesc/HexagonMCInstrInfo.h" 17 #include "MCTargetDesc/HexagonInstPrinter.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrDesc.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/LEB128.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/Support/TargetRegistry.h" 32 33 using namespace llvm; 34 using namespace Hexagon; 35 36 typedef MCDisassembler::DecodeStatus DecodeStatus; 37 38 namespace { 39 /// \brief Hexagon disassembler for all Hexagon platforms. 40 class HexagonDisassembler : public MCDisassembler { 41 public: 42 std::unique_ptr<MCInstrInfo const> const MCII; 43 std::unique_ptr<MCInst *> CurrentBundle; 44 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 45 MCInstrInfo const *MCII) 46 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} 47 48 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 49 ArrayRef<uint8_t> Bytes, uint64_t Address, 50 raw_ostream &VStream, raw_ostream &CStream, 51 bool &Complete) const; 52 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 53 ArrayRef<uint8_t> Bytes, uint64_t Address, 54 raw_ostream &VStream, 55 raw_ostream &CStream) const override; 56 57 void adjustExtendedInstructions(MCInst &MCI, MCInst const &MCB) const; 58 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; 59 }; 60 } 61 62 // Forward declare these because the auto-generated code will reference them. 63 // Definitions are further down. 64 65 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 66 uint64_t Address, 67 const void *Decoder); 68 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 69 uint64_t Address, 70 const void *Decoder); 71 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 72 uint64_t Address, 73 const void *Decoder); 74 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 75 uint64_t Address, 76 const void *Decoder); 77 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 78 uint64_t Address, 79 const void *Decoder); 80 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 81 uint64_t Address, 82 const void *Decoder); 83 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 84 uint64_t Address, 85 const void *Decoder); 86 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 87 uint64_t Address, 88 const void *Decoder); 89 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn); 97 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, 98 void const *Decoder); 99 100 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 101 raw_ostream &os); 102 103 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg); 104 105 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 106 uint64_t Address, const void *Decoder); 107 static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 112 const void *Decoder); 113 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 116 const void *Decoder); 117 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 118 const void *Decoder); 119 static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 122 const void *Decoder); 123 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 128 const void *Decoder); 129 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 134 const void *Decoder); 135 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 136 const void *Decoder); 137 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 138 const void *Decoder); 139 140 #include "HexagonGenDisassemblerTables.inc" 141 142 static MCDisassembler *createHexagonDisassembler(const Target &T, 143 const MCSubtargetInfo &STI, 144 MCContext &Ctx) { 145 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 146 } 147 148 extern "C" void LLVMInitializeHexagonDisassembler() { 149 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 150 createHexagonDisassembler); 151 } 152 153 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 154 ArrayRef<uint8_t> Bytes, 155 uint64_t Address, 156 raw_ostream &os, 157 raw_ostream &cs) const { 158 DecodeStatus Result = DecodeStatus::Success; 159 bool Complete = false; 160 Size = 0; 161 162 *CurrentBundle = &MI; 163 MI = HexagonMCInstrInfo::createBundle(); 164 while (Result == Success && Complete == false) { 165 if (Bytes.size() < HEXAGON_INSTR_SIZE) 166 return MCDisassembler::Fail; 167 MCInst *Inst = new (getContext()) MCInst; 168 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 169 MI.addOperand(MCOperand::createInst(Inst)); 170 Size += HEXAGON_INSTR_SIZE; 171 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 172 } 173 if(Result == MCDisassembler::Fail) 174 return Result; 175 HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo()); 176 if(!Checker.check()) 177 return MCDisassembler::Fail; 178 return MCDisassembler::Success; 179 } 180 181 namespace { 182 HexagonDisassembler const &disassembler(void const *Decoder) { 183 return *static_cast<HexagonDisassembler const *>(Decoder); 184 } 185 MCContext &contextFromDecoder(void const *Decoder) { 186 return disassembler(Decoder).getContext(); 187 } 188 } 189 190 DecodeStatus HexagonDisassembler::getSingleInstruction( 191 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 192 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 193 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 194 195 uint32_t Instruction = 196 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 197 198 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 199 if ((Instruction & HexagonII::INST_PARSE_MASK) == 200 HexagonII::INST_PARSE_LOOP_END) { 201 if (BundleSize == 0) 202 HexagonMCInstrInfo::setInnerLoop(MCB); 203 else if (BundleSize == 1) 204 HexagonMCInstrInfo::setOuterLoop(MCB); 205 else 206 return DecodeStatus::Fail; 207 } 208 209 DecodeStatus Result = DecodeStatus::Success; 210 if ((Instruction & HexagonII::INST_PARSE_MASK) == 211 HexagonII::INST_PARSE_DUPLEX) { 212 // Determine the instruction class of each instruction in the duplex. 213 unsigned duplexIClass, IClassLow, IClassHigh; 214 215 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 216 switch (duplexIClass) { 217 default: 218 return MCDisassembler::Fail; 219 case 0: 220 IClassLow = HexagonII::HSIG_L1; 221 IClassHigh = HexagonII::HSIG_L1; 222 break; 223 case 1: 224 IClassLow = HexagonII::HSIG_L2; 225 IClassHigh = HexagonII::HSIG_L1; 226 break; 227 case 2: 228 IClassLow = HexagonII::HSIG_L2; 229 IClassHigh = HexagonII::HSIG_L2; 230 break; 231 case 3: 232 IClassLow = HexagonII::HSIG_A; 233 IClassHigh = HexagonII::HSIG_A; 234 break; 235 case 4: 236 IClassLow = HexagonII::HSIG_L1; 237 IClassHigh = HexagonII::HSIG_A; 238 break; 239 case 5: 240 IClassLow = HexagonII::HSIG_L2; 241 IClassHigh = HexagonII::HSIG_A; 242 break; 243 case 6: 244 IClassLow = HexagonII::HSIG_S1; 245 IClassHigh = HexagonII::HSIG_A; 246 break; 247 case 7: 248 IClassLow = HexagonII::HSIG_S2; 249 IClassHigh = HexagonII::HSIG_A; 250 break; 251 case 8: 252 IClassLow = HexagonII::HSIG_S1; 253 IClassHigh = HexagonII::HSIG_L1; 254 break; 255 case 9: 256 IClassLow = HexagonII::HSIG_S1; 257 IClassHigh = HexagonII::HSIG_L2; 258 break; 259 case 10: 260 IClassLow = HexagonII::HSIG_S1; 261 IClassHigh = HexagonII::HSIG_S1; 262 break; 263 case 11: 264 IClassLow = HexagonII::HSIG_S2; 265 IClassHigh = HexagonII::HSIG_S1; 266 break; 267 case 12: 268 IClassLow = HexagonII::HSIG_S2; 269 IClassHigh = HexagonII::HSIG_L1; 270 break; 271 case 13: 272 IClassLow = HexagonII::HSIG_S2; 273 IClassHigh = HexagonII::HSIG_L2; 274 break; 275 case 14: 276 IClassLow = HexagonII::HSIG_S2; 277 IClassHigh = HexagonII::HSIG_S2; 278 break; 279 } 280 281 // Set the MCInst to be a duplex instruction. Which one doesn't matter. 282 MI.setOpcode(Hexagon::DuplexIClass0); 283 284 // Decode each instruction in the duplex. 285 // Create an MCInst for each instruction. 286 unsigned instLow = Instruction & 0x1fff; 287 unsigned instHigh = (Instruction >> 16) & 0x1fff; 288 unsigned opLow; 289 if (GetSubinstOpcode(IClassLow, instLow, opLow, os) != 290 MCDisassembler::Success) 291 return MCDisassembler::Fail; 292 unsigned opHigh; 293 if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) != 294 MCDisassembler::Success) 295 return MCDisassembler::Fail; 296 MCInst *MILow = new (getContext()) MCInst; 297 MILow->setOpcode(opLow); 298 MCInst *MIHigh = new (getContext()) MCInst; 299 MIHigh->setOpcode(opHigh); 300 addSubinstOperands(MILow, opLow, instLow); 301 addSubinstOperands(MIHigh, opHigh, instHigh); 302 // see ConvertToSubInst() in 303 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 304 305 // Add the duplex instruction MCInsts as operands to the passed in MCInst. 306 MCOperand OPLow = MCOperand::createInst(MILow); 307 MCOperand OPHigh = MCOperand::createInst(MIHigh); 308 MI.addOperand(OPLow); 309 MI.addOperand(OPHigh); 310 Complete = true; 311 } else { 312 if ((Instruction & HexagonII::INST_PARSE_MASK) == 313 HexagonII::INST_PARSE_PACKET_END) 314 Complete = true; 315 // Calling the auto-generated decoder function. 316 Result = 317 decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); 318 319 // If a, "standard" insn isn't found check special cases. 320 if (MCDisassembler::Success != Result || 321 MI.getOpcode() == Hexagon::A4_ext) { 322 Result = decodeImmext(MI, Instruction, this); 323 if (MCDisassembler::Success != Result) { 324 Result = decodeSpecial(MI, Instruction); 325 } 326 } else { 327 // If the instruction is a compound instruction, register values will 328 // follow the duplex model, so the register values in the MCInst are 329 // incorrect. If the instruction is a compound, loop through the 330 // operands and change registers appropriately. 331 if (llvm::HexagonMCInstrInfo::getType(*MCII, MI) == 332 HexagonII::TypeCOMPOUND) { 333 for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) { 334 if (i->isReg()) { 335 unsigned reg = i->getReg() - Hexagon::R0; 336 i->setReg(getRegFromSubinstEncoding(reg)); 337 } 338 } 339 } 340 } 341 } 342 343 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 344 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 345 MCOperand &MCO = MI.getOperand(OpIndex); 346 assert(MCO.isReg() && "New value consumers must be registers"); 347 unsigned Register = 348 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 349 if ((Register & 0x6) == 0) 350 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 351 return MCDisassembler::Fail; 352 unsigned Lookback = (Register & 0x6) >> 1; 353 unsigned Offset = 1; 354 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 355 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 356 auto i = Instructions.end() - 1; 357 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 358 if (i == n) 359 // Couldn't find producer 360 return MCDisassembler::Fail; 361 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) 362 // Skip scalars when calculating distances for vectors 363 ++Lookback; 364 if (HexagonMCInstrInfo::isImmext(*i->getInst())) 365 ++Lookback; 366 if (Offset == Lookback) 367 break; 368 } 369 auto const &Inst = *i->getInst(); 370 bool SubregBit = (Register & 0x1) != 0; 371 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 372 // If subreg bit is set we're selecting the second produced newvalue 373 unsigned Producer = 374 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 375 assert(Producer != Hexagon::NoRegister); 376 MCO.setReg(Producer); 377 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 378 unsigned Producer = 379 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 380 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 381 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 382 else if (SubregBit) 383 // Hexagon PRM 10.11 New-value operands 384 // Nt[0] is reserved and should always be encoded as zero. 385 return MCDisassembler::Fail; 386 assert(Producer != Hexagon::NoRegister); 387 MCO.setReg(Producer); 388 } else 389 return MCDisassembler::Fail; 390 } 391 392 adjustExtendedInstructions(MI, MCB); 393 MCInst const *Extender = 394 HexagonMCInstrInfo::extenderForIndex(MCB, 395 HexagonMCInstrInfo::bundleSize(MCB)); 396 if(Extender != nullptr) { 397 MCInst const & Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ? 398 *MI.getOperand(1).getInst() : MI; 399 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 400 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 401 return MCDisassembler::Fail; 402 } 403 return Result; 404 } 405 406 void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI, 407 MCInst const &MCB) const { 408 if (!HexagonMCInstrInfo::hasExtenderForIndex( 409 MCB, HexagonMCInstrInfo::bundleSize(MCB))) { 410 unsigned opcode; 411 // This code is used by the disassembler to disambiguate between GP 412 // relative and absolute addressing instructions since they both have 413 // same encoding bits. However, an absolute addressing instruction must 414 // follow an immediate extender. Disassembler alwaus select absolute 415 // addressing instructions first and uses this code to change them into 416 // GP relative instruction in the absence of the corresponding immediate 417 // extender. 418 switch (MCI.getOpcode()) { 419 case Hexagon::PS_storerbabs: 420 opcode = Hexagon::S2_storerbgp; 421 break; 422 case Hexagon::PS_storerhabs: 423 opcode = Hexagon::S2_storerhgp; 424 break; 425 case Hexagon::PS_storerfabs: 426 opcode = Hexagon::S2_storerfgp; 427 break; 428 case Hexagon::PS_storeriabs: 429 opcode = Hexagon::S2_storerigp; 430 break; 431 case Hexagon::PS_storerbnewabs: 432 opcode = Hexagon::S2_storerbnewgp; 433 break; 434 case Hexagon::PS_storerhnewabs: 435 opcode = Hexagon::S2_storerhnewgp; 436 break; 437 case Hexagon::PS_storerinewabs: 438 opcode = Hexagon::S2_storerinewgp; 439 break; 440 case Hexagon::PS_storerdabs: 441 opcode = Hexagon::S2_storerdgp; 442 break; 443 case Hexagon::PS_loadrbabs: 444 opcode = Hexagon::L2_loadrbgp; 445 break; 446 case Hexagon::PS_loadrubabs: 447 opcode = Hexagon::L2_loadrubgp; 448 break; 449 case Hexagon::PS_loadrhabs: 450 opcode = Hexagon::L2_loadrhgp; 451 break; 452 case Hexagon::PS_loadruhabs: 453 opcode = Hexagon::L2_loadruhgp; 454 break; 455 case Hexagon::PS_loadriabs: 456 opcode = Hexagon::L2_loadrigp; 457 break; 458 case Hexagon::PS_loadrdabs: 459 opcode = Hexagon::L2_loadrdgp; 460 break; 461 default: 462 opcode = MCI.getOpcode(); 463 } 464 MCI.setOpcode(opcode); 465 } 466 } 467 468 namespace llvm { 469 extern const MCInstrDesc HexagonInsts[]; 470 } 471 472 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 473 ArrayRef<MCPhysReg> Table) { 474 if (RegNo < Table.size()) { 475 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 476 return MCDisassembler::Success; 477 } 478 479 return MCDisassembler::Fail; 480 } 481 482 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 483 uint64_t Address, 484 const void *Decoder) { 485 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 486 } 487 488 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 489 uint64_t Address, 490 const void *Decoder) { 491 static const MCPhysReg IntRegDecoderTable[] = { 492 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 493 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 494 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 495 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 496 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 497 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 498 Hexagon::R30, Hexagon::R31}; 499 500 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 501 } 502 503 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 504 uint64_t /*Address*/, 505 const void *Decoder) { 506 static const MCPhysReg VecRegDecoderTable[] = { 507 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 508 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 509 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 510 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 511 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 512 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 513 Hexagon::V30, Hexagon::V31}; 514 515 return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable); 516 } 517 518 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 519 uint64_t /*Address*/, 520 const void *Decoder) { 521 static const MCPhysReg DoubleRegDecoderTable[] = { 522 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 523 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 524 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 525 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 526 527 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 528 } 529 530 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 531 uint64_t /*Address*/, 532 const void *Decoder) { 533 static const MCPhysReg VecDblRegDecoderTable[] = { 534 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 535 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 536 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 537 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 538 539 return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable)); 540 } 541 542 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 543 uint64_t /*Address*/, 544 const void *Decoder) { 545 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 546 Hexagon::P2, Hexagon::P3}; 547 548 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 549 } 550 551 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 552 uint64_t /*Address*/, 553 const void *Decoder) { 554 static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 555 Hexagon::Q2, Hexagon::Q3}; 556 557 return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable); 558 } 559 560 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 561 uint64_t /*Address*/, 562 const void *Decoder) { 563 static const MCPhysReg CtrlRegDecoderTable[] = { 564 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, 565 Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7, 566 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, 567 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC 568 }; 569 570 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 571 return MCDisassembler::Fail; 572 573 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister) 574 return MCDisassembler::Fail; 575 576 unsigned Register = CtrlRegDecoderTable[RegNo]; 577 Inst.addOperand(MCOperand::createReg(Register)); 578 return MCDisassembler::Success; 579 } 580 581 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 582 uint64_t /*Address*/, 583 const void *Decoder) { 584 static const MCPhysReg CtrlReg64DecoderTable[] = { 585 Hexagon::C1_0, Hexagon::NoRegister, 586 Hexagon::C3_2, Hexagon::NoRegister, 587 Hexagon::C7_6, Hexagon::NoRegister, 588 Hexagon::C9_8, Hexagon::NoRegister, 589 Hexagon::C11_10, Hexagon::NoRegister, 590 Hexagon::CS, Hexagon::NoRegister, 591 Hexagon::UPC, Hexagon::NoRegister 592 }; 593 594 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 595 return MCDisassembler::Fail; 596 597 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister) 598 return MCDisassembler::Fail; 599 600 unsigned Register = CtrlReg64DecoderTable[RegNo]; 601 Inst.addOperand(MCOperand::createReg(Register)); 602 return MCDisassembler::Success; 603 } 604 605 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 606 uint64_t /*Address*/, 607 const void *Decoder) { 608 unsigned Register = 0; 609 switch (RegNo) { 610 case 0: 611 Register = Hexagon::M0; 612 break; 613 case 1: 614 Register = Hexagon::M1; 615 break; 616 default: 617 return MCDisassembler::Fail; 618 } 619 Inst.addOperand(MCOperand::createReg(Register)); 620 return MCDisassembler::Success; 621 } 622 623 namespace { 624 uint32_t fullValue(MCInstrInfo const &MCII, 625 MCInst &MCB, 626 MCInst &MI, 627 int64_t Value) { 628 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 629 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 630 if(!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 631 return Value; 632 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 633 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 634 int64_t Bits; 635 bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); 636 assert(Success);(void)Success; 637 uint32_t Upper26 = static_cast<uint32_t>(Bits); 638 uint32_t Operand = Upper26 | Lower6; 639 return Operand; 640 } 641 template <size_t T> 642 void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 643 HexagonDisassembler const &Disassembler = disassembler(Decoder); 644 int64_t FullValue = fullValue(*Disassembler.MCII, 645 **Disassembler.CurrentBundle, 646 MI, SignExtend64<T>(tmp)); 647 int64_t Extended = SignExtend64<32>(FullValue); 648 HexagonMCInstrInfo::addConstant(MI, Extended, 649 Disassembler.getContext()); 650 } 651 } 652 653 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 654 uint64_t /*Address*/, 655 const void *Decoder) { 656 HexagonDisassembler const &Disassembler = disassembler(Decoder); 657 int64_t FullValue = fullValue(*Disassembler.MCII, 658 **Disassembler.CurrentBundle, 659 MI, tmp); 660 assert(FullValue >= 0 && "Negative in unsigned decoder"); 661 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 662 return MCDisassembler::Success; 663 } 664 665 static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, 666 uint64_t /*Address*/, const void *Decoder) { 667 signedDecoder<16>(MI, tmp, Decoder); 668 return MCDisassembler::Success; 669 } 670 671 static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, 672 uint64_t /*Address*/, const void *Decoder) { 673 signedDecoder<12>(MI, tmp, Decoder); 674 return MCDisassembler::Success; 675 } 676 677 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, 678 uint64_t /*Address*/, const void *Decoder) { 679 signedDecoder<11>(MI, tmp, Decoder); 680 return MCDisassembler::Success; 681 } 682 683 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, 684 uint64_t /*Address*/, const void *Decoder) { 685 HexagonMCInstrInfo::addConstant(MI, SignExtend64<12>(tmp), contextFromDecoder(Decoder)); 686 return MCDisassembler::Success; 687 } 688 689 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, 690 uint64_t /*Address*/, const void *Decoder) { 691 signedDecoder<13>(MI, tmp, Decoder); 692 return MCDisassembler::Success; 693 } 694 695 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, 696 uint64_t /*Address*/, const void *Decoder) { 697 signedDecoder<14>(MI, tmp, Decoder); 698 return MCDisassembler::Success; 699 } 700 701 static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, 702 uint64_t /*Address*/, const void *Decoder) { 703 signedDecoder<10>(MI, tmp, Decoder); 704 return MCDisassembler::Success; 705 } 706 707 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, 708 const void *Decoder) { 709 signedDecoder<8>(MI, tmp, Decoder); 710 return MCDisassembler::Success; 711 } 712 713 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, 714 uint64_t /*Address*/, const void *Decoder) { 715 signedDecoder<6>(MI, tmp, Decoder); 716 return MCDisassembler::Success; 717 } 718 719 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, 720 uint64_t /*Address*/, const void *Decoder) { 721 signedDecoder<4>(MI, tmp, Decoder); 722 return MCDisassembler::Success; 723 } 724 725 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, 726 uint64_t /*Address*/, const void *Decoder) { 727 signedDecoder<5>(MI, tmp, Decoder); 728 return MCDisassembler::Success; 729 } 730 731 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, 732 uint64_t /*Address*/, const void *Decoder) { 733 signedDecoder<6>(MI, tmp, Decoder); 734 return MCDisassembler::Success; 735 } 736 737 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, 738 uint64_t /*Address*/, const void *Decoder) { 739 signedDecoder<7>(MI, tmp, Decoder); 740 return MCDisassembler::Success; 741 } 742 743 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, 744 uint64_t /*Address*/, const void *Decoder) { 745 signedDecoder<10>(MI, tmp, Decoder); 746 return MCDisassembler::Success; 747 } 748 749 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, 750 uint64_t /*Address*/, const void *Decoder) { 751 signedDecoder<19>(MI, tmp, Decoder); 752 return MCDisassembler::Success; 753 } 754 755 // custom decoder for various jump/call immediates 756 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 757 const void *Decoder) { 758 HexagonDisassembler const &Disassembler = disassembler(Decoder); 759 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 760 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 761 if (Bits == 0) 762 Bits = 15; 763 uint32_t FullValue = fullValue(*Disassembler.MCII, 764 **Disassembler.CurrentBundle, 765 MI, SignExtend64(tmp, Bits)); 766 int64_t Extended = SignExtend64<32>(FullValue) + Address; 767 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 768 0, 4)) 769 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 770 return MCDisassembler::Success; 771 } 772 773 // Addressing mode dependent load store opcode map. 774 // - If an insn is preceded by an extender the address is absolute. 775 // - memw(##symbol) = r0 776 // - If an insn is not preceded by an extender the address is GP relative. 777 // - memw(gp + #symbol) = r0 778 // Please note that the instructions must be ordered in the descending order 779 // of their opcode. 780 // HexagonII::INST_ICLASS_ST 781 static const unsigned int StoreConditionalOpcodeData[][2] = { 782 {S4_pstorerdfnew_abs, 0xafc02084}, 783 {S4_pstorerdtnew_abs, 0xafc02080}, 784 {S4_pstorerdf_abs, 0xafc00084}, 785 {S4_pstorerdt_abs, 0xafc00080}, 786 {S4_pstorerinewfnew_abs, 0xafa03084}, 787 {S4_pstorerinewtnew_abs, 0xafa03080}, 788 {S4_pstorerhnewfnew_abs, 0xafa02884}, 789 {S4_pstorerhnewtnew_abs, 0xafa02880}, 790 {S4_pstorerbnewfnew_abs, 0xafa02084}, 791 {S4_pstorerbnewtnew_abs, 0xafa02080}, 792 {S4_pstorerinewf_abs, 0xafa01084}, 793 {S4_pstorerinewt_abs, 0xafa01080}, 794 {S4_pstorerhnewf_abs, 0xafa00884}, 795 {S4_pstorerhnewt_abs, 0xafa00880}, 796 {S4_pstorerbnewf_abs, 0xafa00084}, 797 {S4_pstorerbnewt_abs, 0xafa00080}, 798 {S4_pstorerifnew_abs, 0xaf802084}, 799 {S4_pstoreritnew_abs, 0xaf802080}, 800 {S4_pstorerif_abs, 0xaf800084}, 801 {S4_pstorerit_abs, 0xaf800080}, 802 {S4_pstorerhfnew_abs, 0xaf402084}, 803 {S4_pstorerhtnew_abs, 0xaf402080}, 804 {S4_pstorerhf_abs, 0xaf400084}, 805 {S4_pstorerht_abs, 0xaf400080}, 806 {S4_pstorerbfnew_abs, 0xaf002084}, 807 {S4_pstorerbtnew_abs, 0xaf002080}, 808 {S4_pstorerbf_abs, 0xaf000084}, 809 {S4_pstorerbt_abs, 0xaf000080}}; 810 // HexagonII::INST_ICLASS_LD 811 812 // HexagonII::INST_ICLASS_LD_ST_2 813 static unsigned int LoadStoreOpcodeData[][2] = {{PS_loadrdabs, 0x49c00000}, 814 {PS_loadriabs, 0x49800000}, 815 {PS_loadruhabs, 0x49600000}, 816 {PS_loadrhabs, 0x49400000}, 817 {PS_loadrubabs, 0x49200000}, 818 {PS_loadrbabs, 0x49000000}, 819 {PS_storerdabs, 0x48c00000}, 820 {PS_storerinewabs, 0x48a01000}, 821 {PS_storerhnewabs, 0x48a00800}, 822 {PS_storerbnewabs, 0x48a00000}, 823 {PS_storeriabs, 0x48800000}, 824 {PS_storerfabs, 0x48600000}, 825 {PS_storerhabs, 0x48400000}, 826 {PS_storerbabs, 0x48000000}}; 827 static const size_t NumCondS = array_lengthof(StoreConditionalOpcodeData); 828 static const size_t NumLS = array_lengthof(LoadStoreOpcodeData); 829 830 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) { 831 832 unsigned MachineOpcode = 0; 833 unsigned LLVMOpcode = 0; 834 835 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_ST) { 836 for (size_t i = 0; i < NumCondS; ++i) { 837 if ((insn & StoreConditionalOpcodeData[i][1]) == 838 StoreConditionalOpcodeData[i][1]) { 839 MachineOpcode = StoreConditionalOpcodeData[i][1]; 840 LLVMOpcode = StoreConditionalOpcodeData[i][0]; 841 break; 842 } 843 } 844 } 845 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_LD_ST_2) { 846 for (size_t i = 0; i < NumLS; ++i) { 847 if ((insn & LoadStoreOpcodeData[i][1]) == LoadStoreOpcodeData[i][1]) { 848 MachineOpcode = LoadStoreOpcodeData[i][1]; 849 LLVMOpcode = LoadStoreOpcodeData[i][0]; 850 break; 851 } 852 } 853 } 854 855 if (MachineOpcode) { 856 unsigned Value = 0; 857 unsigned shift = 0; 858 MI.setOpcode(LLVMOpcode); 859 // Remove the parse bits from the insn. 860 insn &= ~HexagonII::INST_PARSE_MASK; 861 862 switch (LLVMOpcode) { 863 default: 864 return MCDisassembler::Fail; 865 break; 866 867 case Hexagon::S4_pstorerdf_abs: 868 case Hexagon::S4_pstorerdt_abs: 869 case Hexagon::S4_pstorerdfnew_abs: 870 case Hexagon::S4_pstorerdtnew_abs: { 871 // op: Pv 872 Value = insn & UINT64_C(3); 873 DecodePredRegsRegisterClass(MI, Value, 0, 0); 874 // op: u6 875 Value = (insn >> 12) & UINT64_C(48); 876 Value |= (insn >> 3) & UINT64_C(15); 877 MI.addOperand(MCOperand::createImm(Value)); 878 // op: Rtt 879 Value = (insn >> 8) & UINT64_C(31); 880 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 881 break; 882 } 883 884 case Hexagon::S4_pstorerbnewf_abs: 885 case Hexagon::S4_pstorerbnewt_abs: 886 case Hexagon::S4_pstorerbnewfnew_abs: 887 case Hexagon::S4_pstorerbnewtnew_abs: 888 case Hexagon::S4_pstorerhnewf_abs: 889 case Hexagon::S4_pstorerhnewt_abs: 890 case Hexagon::S4_pstorerhnewfnew_abs: 891 case Hexagon::S4_pstorerhnewtnew_abs: 892 case Hexagon::S4_pstorerinewf_abs: 893 case Hexagon::S4_pstorerinewt_abs: 894 case Hexagon::S4_pstorerinewfnew_abs: 895 case Hexagon::S4_pstorerinewtnew_abs: { 896 // op: Pv 897 Value = insn & UINT64_C(3); 898 DecodePredRegsRegisterClass(MI, Value, 0, 0); 899 // op: u6 900 Value = (insn >> 12) & UINT64_C(48); 901 Value |= (insn >> 3) & UINT64_C(15); 902 MI.addOperand(MCOperand::createImm(Value)); 903 // op: Nt 904 Value = (insn >> 8) & UINT64_C(7); 905 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 906 break; 907 } 908 909 case Hexagon::S4_pstorerbf_abs: 910 case Hexagon::S4_pstorerbt_abs: 911 case Hexagon::S4_pstorerbfnew_abs: 912 case Hexagon::S4_pstorerbtnew_abs: 913 case Hexagon::S4_pstorerhf_abs: 914 case Hexagon::S4_pstorerht_abs: 915 case Hexagon::S4_pstorerhfnew_abs: 916 case Hexagon::S4_pstorerhtnew_abs: 917 case Hexagon::S4_pstorerif_abs: 918 case Hexagon::S4_pstorerit_abs: 919 case Hexagon::S4_pstorerifnew_abs: 920 case Hexagon::S4_pstoreritnew_abs: { 921 // op: Pv 922 Value = insn & UINT64_C(3); 923 DecodePredRegsRegisterClass(MI, Value, 0, 0); 924 // op: u6 925 Value = (insn >> 12) & UINT64_C(48); 926 Value |= (insn >> 3) & UINT64_C(15); 927 MI.addOperand(MCOperand::createImm(Value)); 928 // op: Rt 929 Value = (insn >> 8) & UINT64_C(31); 930 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 931 break; 932 } 933 934 case Hexagon::L4_ploadrdf_abs: 935 case Hexagon::L4_ploadrdt_abs: 936 case Hexagon::L4_ploadrdfnew_abs: 937 case Hexagon::L4_ploadrdtnew_abs: { 938 // op: Rdd 939 Value = insn & UINT64_C(31); 940 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 941 // op: Pt 942 Value = ((insn >> 9) & UINT64_C(3)); 943 DecodePredRegsRegisterClass(MI, Value, 0, 0); 944 // op: u6 945 Value = ((insn >> 15) & UINT64_C(62)); 946 Value |= ((insn >> 8) & UINT64_C(1)); 947 MI.addOperand(MCOperand::createImm(Value)); 948 break; 949 } 950 951 case Hexagon::L4_ploadrbf_abs: 952 case Hexagon::L4_ploadrbt_abs: 953 case Hexagon::L4_ploadrbfnew_abs: 954 case Hexagon::L4_ploadrbtnew_abs: 955 case Hexagon::L4_ploadrhf_abs: 956 case Hexagon::L4_ploadrht_abs: 957 case Hexagon::L4_ploadrhfnew_abs: 958 case Hexagon::L4_ploadrhtnew_abs: 959 case Hexagon::L4_ploadrubf_abs: 960 case Hexagon::L4_ploadrubt_abs: 961 case Hexagon::L4_ploadrubfnew_abs: 962 case Hexagon::L4_ploadrubtnew_abs: 963 case Hexagon::L4_ploadruhf_abs: 964 case Hexagon::L4_ploadruht_abs: 965 case Hexagon::L4_ploadruhfnew_abs: 966 case Hexagon::L4_ploadruhtnew_abs: 967 case Hexagon::L4_ploadrif_abs: 968 case Hexagon::L4_ploadrit_abs: 969 case Hexagon::L4_ploadrifnew_abs: 970 case Hexagon::L4_ploadritnew_abs: 971 // op: Rd 972 Value = insn & UINT64_C(31); 973 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 974 // op: Pt 975 Value = (insn >> 9) & UINT64_C(3); 976 DecodePredRegsRegisterClass(MI, Value, 0, 0); 977 // op: u6 978 Value = (insn >> 15) & UINT64_C(62); 979 Value |= (insn >> 8) & UINT64_C(1); 980 MI.addOperand(MCOperand::createImm(Value)); 981 break; 982 983 // op: g16_2 984 case (Hexagon::PS_loadriabs): 985 ++shift; 986 // op: g16_1 987 case Hexagon::PS_loadrhabs: 988 case Hexagon::PS_loadruhabs: 989 ++shift; 990 // op: g16_0 991 case Hexagon::PS_loadrbabs: 992 case Hexagon::PS_loadrubabs: { 993 // op: Rd 994 Value |= insn & UINT64_C(31); 995 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 996 Value = (insn >> 11) & UINT64_C(49152); 997 Value |= (insn >> 7) & UINT64_C(15872); 998 Value |= (insn >> 5) & UINT64_C(511); 999 MI.addOperand(MCOperand::createImm(Value << shift)); 1000 break; 1001 } 1002 1003 case Hexagon::PS_loadrdabs: { 1004 Value = insn & UINT64_C(31); 1005 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 1006 Value = (insn >> 11) & UINT64_C(49152); 1007 Value |= (insn >> 7) & UINT64_C(15872); 1008 Value |= (insn >> 5) & UINT64_C(511); 1009 MI.addOperand(MCOperand::createImm(Value << 3)); 1010 break; 1011 } 1012 1013 case Hexagon::PS_storerdabs: { 1014 // op: g16_3 1015 Value = (insn >> 11) & UINT64_C(49152); 1016 Value |= (insn >> 7) & UINT64_C(15872); 1017 Value |= (insn >> 5) & UINT64_C(256); 1018 Value |= insn & UINT64_C(255); 1019 MI.addOperand(MCOperand::createImm(Value << 3)); 1020 // op: Rtt 1021 Value = (insn >> 8) & UINT64_C(31); 1022 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 1023 break; 1024 } 1025 1026 // op: g16_2 1027 case Hexagon::PS_storerinewabs: 1028 ++shift; 1029 // op: g16_1 1030 case Hexagon::PS_storerhnewabs: 1031 ++shift; 1032 // op: g16_0 1033 case Hexagon::PS_storerbnewabs: { 1034 Value = (insn >> 11) & UINT64_C(49152); 1035 Value |= (insn >> 7) & UINT64_C(15872); 1036 Value |= (insn >> 5) & UINT64_C(256); 1037 Value |= insn & UINT64_C(255); 1038 MI.addOperand(MCOperand::createImm(Value << shift)); 1039 // op: Nt 1040 Value = (insn >> 8) & UINT64_C(7); 1041 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1042 break; 1043 } 1044 1045 // op: g16_2 1046 case Hexagon::PS_storeriabs: 1047 ++shift; 1048 // op: g16_1 1049 case Hexagon::PS_storerhabs: 1050 case Hexagon::PS_storerfabs: 1051 ++shift; 1052 // op: g16_0 1053 case Hexagon::PS_storerbabs: { 1054 Value = (insn >> 11) & UINT64_C(49152); 1055 Value |= (insn >> 7) & UINT64_C(15872); 1056 Value |= (insn >> 5) & UINT64_C(256); 1057 Value |= insn & UINT64_C(255); 1058 MI.addOperand(MCOperand::createImm(Value << shift)); 1059 // op: Rt 1060 Value = (insn >> 8) & UINT64_C(31); 1061 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1062 break; 1063 } 1064 } 1065 return MCDisassembler::Success; 1066 } 1067 return MCDisassembler::Fail; 1068 } 1069 1070 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, 1071 void const *Decoder) { 1072 1073 // Instruction Class for a constant a extender: bits 31:28 = 0x0000 1074 if ((~insn & 0xf0000000) == 0xf0000000) { 1075 unsigned Value; 1076 // 27:16 High 12 bits of 26-bit extender. 1077 Value = (insn & 0x0fff0000) << 4; 1078 // 13:0 Low 14 bits of 26-bit extender. 1079 Value |= ((insn & 0x3fff) << 6); 1080 MI.setOpcode(Hexagon::A4_ext); 1081 HexagonMCInstrInfo::addConstant(MI, Value, contextFromDecoder(Decoder)); 1082 return MCDisassembler::Success; 1083 } 1084 return MCDisassembler::Fail; 1085 } 1086 1087 // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td 1088 enum subInstBinaryValues { 1089 SA1_addi_BITS = 0x0000, 1090 SA1_addi_MASK = 0x1800, 1091 SA1_addrx_BITS = 0x1800, 1092 SA1_addrx_MASK = 0x1f00, 1093 SA1_addsp_BITS = 0x0c00, 1094 SA1_addsp_MASK = 0x1c00, 1095 SA1_and1_BITS = 0x1200, 1096 SA1_and1_MASK = 0x1f00, 1097 SA1_clrf_BITS = 0x1a70, 1098 SA1_clrf_MASK = 0x1e70, 1099 SA1_clrfnew_BITS = 0x1a50, 1100 SA1_clrfnew_MASK = 0x1e70, 1101 SA1_clrt_BITS = 0x1a60, 1102 SA1_clrt_MASK = 0x1e70, 1103 SA1_clrtnew_BITS = 0x1a40, 1104 SA1_clrtnew_MASK = 0x1e70, 1105 SA1_cmpeqi_BITS = 0x1900, 1106 SA1_cmpeqi_MASK = 0x1f00, 1107 SA1_combine0i_BITS = 0x1c00, 1108 SA1_combine0i_MASK = 0x1d18, 1109 SA1_combine1i_BITS = 0x1c08, 1110 SA1_combine1i_MASK = 0x1d18, 1111 SA1_combine2i_BITS = 0x1c10, 1112 SA1_combine2i_MASK = 0x1d18, 1113 SA1_combine3i_BITS = 0x1c18, 1114 SA1_combine3i_MASK = 0x1d18, 1115 SA1_combinerz_BITS = 0x1d08, 1116 SA1_combinerz_MASK = 0x1d08, 1117 SA1_combinezr_BITS = 0x1d00, 1118 SA1_combinezr_MASK = 0x1d08, 1119 SA1_dec_BITS = 0x1300, 1120 SA1_dec_MASK = 0x1f00, 1121 SA1_inc_BITS = 0x1100, 1122 SA1_inc_MASK = 0x1f00, 1123 SA1_seti_BITS = 0x0800, 1124 SA1_seti_MASK = 0x1c00, 1125 SA1_setin1_BITS = 0x1a00, 1126 SA1_setin1_MASK = 0x1e40, 1127 SA1_sxtb_BITS = 0x1500, 1128 SA1_sxtb_MASK = 0x1f00, 1129 SA1_sxth_BITS = 0x1400, 1130 SA1_sxth_MASK = 0x1f00, 1131 SA1_tfr_BITS = 0x1000, 1132 SA1_tfr_MASK = 0x1f00, 1133 SA1_zxtb_BITS = 0x1700, 1134 SA1_zxtb_MASK = 0x1f00, 1135 SA1_zxth_BITS = 0x1600, 1136 SA1_zxth_MASK = 0x1f00, 1137 SL1_loadri_io_BITS = 0x0000, 1138 SL1_loadri_io_MASK = 0x1000, 1139 SL1_loadrub_io_BITS = 0x1000, 1140 SL1_loadrub_io_MASK = 0x1000, 1141 SL2_deallocframe_BITS = 0x1f00, 1142 SL2_deallocframe_MASK = 0x1fc0, 1143 SL2_jumpr31_BITS = 0x1fc0, 1144 SL2_jumpr31_MASK = 0x1fc4, 1145 SL2_jumpr31_f_BITS = 0x1fc5, 1146 SL2_jumpr31_f_MASK = 0x1fc7, 1147 SL2_jumpr31_fnew_BITS = 0x1fc7, 1148 SL2_jumpr31_fnew_MASK = 0x1fc7, 1149 SL2_jumpr31_t_BITS = 0x1fc4, 1150 SL2_jumpr31_t_MASK = 0x1fc7, 1151 SL2_jumpr31_tnew_BITS = 0x1fc6, 1152 SL2_jumpr31_tnew_MASK = 0x1fc7, 1153 SL2_loadrb_io_BITS = 0x1000, 1154 SL2_loadrb_io_MASK = 0x1800, 1155 SL2_loadrd_sp_BITS = 0x1e00, 1156 SL2_loadrd_sp_MASK = 0x1f00, 1157 SL2_loadrh_io_BITS = 0x0000, 1158 SL2_loadrh_io_MASK = 0x1800, 1159 SL2_loadri_sp_BITS = 0x1c00, 1160 SL2_loadri_sp_MASK = 0x1e00, 1161 SL2_loadruh_io_BITS = 0x0800, 1162 SL2_loadruh_io_MASK = 0x1800, 1163 SL2_return_BITS = 0x1f40, 1164 SL2_return_MASK = 0x1fc4, 1165 SL2_return_f_BITS = 0x1f45, 1166 SL2_return_f_MASK = 0x1fc7, 1167 SL2_return_fnew_BITS = 0x1f47, 1168 SL2_return_fnew_MASK = 0x1fc7, 1169 SL2_return_t_BITS = 0x1f44, 1170 SL2_return_t_MASK = 0x1fc7, 1171 SL2_return_tnew_BITS = 0x1f46, 1172 SL2_return_tnew_MASK = 0x1fc7, 1173 SS1_storeb_io_BITS = 0x1000, 1174 SS1_storeb_io_MASK = 0x1000, 1175 SS1_storew_io_BITS = 0x0000, 1176 SS1_storew_io_MASK = 0x1000, 1177 SS2_allocframe_BITS = 0x1c00, 1178 SS2_allocframe_MASK = 0x1e00, 1179 SS2_storebi0_BITS = 0x1200, 1180 SS2_storebi0_MASK = 0x1f00, 1181 SS2_storebi1_BITS = 0x1300, 1182 SS2_storebi1_MASK = 0x1f00, 1183 SS2_stored_sp_BITS = 0x0a00, 1184 SS2_stored_sp_MASK = 0x1e00, 1185 SS2_storeh_io_BITS = 0x0000, 1186 SS2_storeh_io_MASK = 0x1800, 1187 SS2_storew_sp_BITS = 0x0800, 1188 SS2_storew_sp_MASK = 0x1e00, 1189 SS2_storewi0_BITS = 0x1000, 1190 SS2_storewi0_MASK = 0x1f00, 1191 SS2_storewi1_BITS = 0x1100, 1192 SS2_storewi1_MASK = 0x1f00 1193 }; 1194 1195 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 1196 raw_ostream &os) { 1197 switch (IClass) { 1198 case HexagonII::HSIG_L1: 1199 if ((inst & SL1_loadri_io_MASK) == SL1_loadri_io_BITS) 1200 op = Hexagon::SL1_loadri_io; 1201 else if ((inst & SL1_loadrub_io_MASK) == SL1_loadrub_io_BITS) 1202 op = Hexagon::SL1_loadrub_io; 1203 else { 1204 os << "<unknown subinstruction>"; 1205 return MCDisassembler::Fail; 1206 } 1207 break; 1208 case HexagonII::HSIG_L2: 1209 if ((inst & SL2_deallocframe_MASK) == SL2_deallocframe_BITS) 1210 op = Hexagon::SL2_deallocframe; 1211 else if ((inst & SL2_jumpr31_MASK) == SL2_jumpr31_BITS) 1212 op = Hexagon::SL2_jumpr31; 1213 else if ((inst & SL2_jumpr31_f_MASK) == SL2_jumpr31_f_BITS) 1214 op = Hexagon::SL2_jumpr31_f; 1215 else if ((inst & SL2_jumpr31_fnew_MASK) == SL2_jumpr31_fnew_BITS) 1216 op = Hexagon::SL2_jumpr31_fnew; 1217 else if ((inst & SL2_jumpr31_t_MASK) == SL2_jumpr31_t_BITS) 1218 op = Hexagon::SL2_jumpr31_t; 1219 else if ((inst & SL2_jumpr31_tnew_MASK) == SL2_jumpr31_tnew_BITS) 1220 op = Hexagon::SL2_jumpr31_tnew; 1221 else if ((inst & SL2_loadrb_io_MASK) == SL2_loadrb_io_BITS) 1222 op = Hexagon::SL2_loadrb_io; 1223 else if ((inst & SL2_loadrd_sp_MASK) == SL2_loadrd_sp_BITS) 1224 op = Hexagon::SL2_loadrd_sp; 1225 else if ((inst & SL2_loadrh_io_MASK) == SL2_loadrh_io_BITS) 1226 op = Hexagon::SL2_loadrh_io; 1227 else if ((inst & SL2_loadri_sp_MASK) == SL2_loadri_sp_BITS) 1228 op = Hexagon::SL2_loadri_sp; 1229 else if ((inst & SL2_loadruh_io_MASK) == SL2_loadruh_io_BITS) 1230 op = Hexagon::SL2_loadruh_io; 1231 else if ((inst & SL2_return_MASK) == SL2_return_BITS) 1232 op = Hexagon::SL2_return; 1233 else if ((inst & SL2_return_f_MASK) == SL2_return_f_BITS) 1234 op = Hexagon::SL2_return_f; 1235 else if ((inst & SL2_return_fnew_MASK) == SL2_return_fnew_BITS) 1236 op = Hexagon::SL2_return_fnew; 1237 else if ((inst & SL2_return_t_MASK) == SL2_return_t_BITS) 1238 op = Hexagon::SL2_return_t; 1239 else if ((inst & SL2_return_tnew_MASK) == SL2_return_tnew_BITS) 1240 op = Hexagon::SL2_return_tnew; 1241 else { 1242 os << "<unknown subinstruction>"; 1243 return MCDisassembler::Fail; 1244 } 1245 break; 1246 case HexagonII::HSIG_A: 1247 if ((inst & SA1_addi_MASK) == SA1_addi_BITS) 1248 op = Hexagon::SA1_addi; 1249 else if ((inst & SA1_addrx_MASK) == SA1_addrx_BITS) 1250 op = Hexagon::SA1_addrx; 1251 else if ((inst & SA1_addsp_MASK) == SA1_addsp_BITS) 1252 op = Hexagon::SA1_addsp; 1253 else if ((inst & SA1_and1_MASK) == SA1_and1_BITS) 1254 op = Hexagon::SA1_and1; 1255 else if ((inst & SA1_clrf_MASK) == SA1_clrf_BITS) 1256 op = Hexagon::SA1_clrf; 1257 else if ((inst & SA1_clrfnew_MASK) == SA1_clrfnew_BITS) 1258 op = Hexagon::SA1_clrfnew; 1259 else if ((inst & SA1_clrt_MASK) == SA1_clrt_BITS) 1260 op = Hexagon::SA1_clrt; 1261 else if ((inst & SA1_clrtnew_MASK) == SA1_clrtnew_BITS) 1262 op = Hexagon::SA1_clrtnew; 1263 else if ((inst & SA1_cmpeqi_MASK) == SA1_cmpeqi_BITS) 1264 op = Hexagon::SA1_cmpeqi; 1265 else if ((inst & SA1_combine0i_MASK) == SA1_combine0i_BITS) 1266 op = Hexagon::SA1_combine0i; 1267 else if ((inst & SA1_combine1i_MASK) == SA1_combine1i_BITS) 1268 op = Hexagon::SA1_combine1i; 1269 else if ((inst & SA1_combine2i_MASK) == SA1_combine2i_BITS) 1270 op = Hexagon::SA1_combine2i; 1271 else if ((inst & SA1_combine3i_MASK) == SA1_combine3i_BITS) 1272 op = Hexagon::SA1_combine3i; 1273 else if ((inst & SA1_combinerz_MASK) == SA1_combinerz_BITS) 1274 op = Hexagon::SA1_combinerz; 1275 else if ((inst & SA1_combinezr_MASK) == SA1_combinezr_BITS) 1276 op = Hexagon::SA1_combinezr; 1277 else if ((inst & SA1_dec_MASK) == SA1_dec_BITS) 1278 op = Hexagon::SA1_dec; 1279 else if ((inst & SA1_inc_MASK) == SA1_inc_BITS) 1280 op = Hexagon::SA1_inc; 1281 else if ((inst & SA1_seti_MASK) == SA1_seti_BITS) 1282 op = Hexagon::SA1_seti; 1283 else if ((inst & SA1_setin1_MASK) == SA1_setin1_BITS) 1284 op = Hexagon::SA1_setin1; 1285 else if ((inst & SA1_sxtb_MASK) == SA1_sxtb_BITS) 1286 op = Hexagon::SA1_sxtb; 1287 else if ((inst & SA1_sxth_MASK) == SA1_sxth_BITS) 1288 op = Hexagon::SA1_sxth; 1289 else if ((inst & SA1_tfr_MASK) == SA1_tfr_BITS) 1290 op = Hexagon::SA1_tfr; 1291 else if ((inst & SA1_zxtb_MASK) == SA1_zxtb_BITS) 1292 op = Hexagon::SA1_zxtb; 1293 else if ((inst & SA1_zxth_MASK) == SA1_zxth_BITS) 1294 op = Hexagon::SA1_zxth; 1295 else { 1296 os << "<unknown subinstruction>"; 1297 return MCDisassembler::Fail; 1298 } 1299 break; 1300 case HexagonII::HSIG_S1: 1301 if ((inst & SS1_storeb_io_MASK) == SS1_storeb_io_BITS) 1302 op = Hexagon::SS1_storeb_io; 1303 else if ((inst & SS1_storew_io_MASK) == SS1_storew_io_BITS) 1304 op = Hexagon::SS1_storew_io; 1305 else { 1306 os << "<unknown subinstruction>"; 1307 return MCDisassembler::Fail; 1308 } 1309 break; 1310 case HexagonII::HSIG_S2: 1311 if ((inst & SS2_allocframe_MASK) == SS2_allocframe_BITS) 1312 op = Hexagon::SS2_allocframe; 1313 else if ((inst & SS2_storebi0_MASK) == SS2_storebi0_BITS) 1314 op = Hexagon::SS2_storebi0; 1315 else if ((inst & SS2_storebi1_MASK) == SS2_storebi1_BITS) 1316 op = Hexagon::SS2_storebi1; 1317 else if ((inst & SS2_stored_sp_MASK) == SS2_stored_sp_BITS) 1318 op = Hexagon::SS2_stored_sp; 1319 else if ((inst & SS2_storeh_io_MASK) == SS2_storeh_io_BITS) 1320 op = Hexagon::SS2_storeh_io; 1321 else if ((inst & SS2_storew_sp_MASK) == SS2_storew_sp_BITS) 1322 op = Hexagon::SS2_storew_sp; 1323 else if ((inst & SS2_storewi0_MASK) == SS2_storewi0_BITS) 1324 op = Hexagon::SS2_storewi0; 1325 else if ((inst & SS2_storewi1_MASK) == SS2_storewi1_BITS) 1326 op = Hexagon::SS2_storewi1; 1327 else { 1328 os << "<unknown subinstruction>"; 1329 return MCDisassembler::Fail; 1330 } 1331 break; 1332 default: 1333 os << "<unknown>"; 1334 return MCDisassembler::Fail; 1335 } 1336 return MCDisassembler::Success; 1337 } 1338 1339 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) { 1340 if (encoded_reg < 8) 1341 return Hexagon::R0 + encoded_reg; 1342 else if (encoded_reg < 16) 1343 return Hexagon::R0 + encoded_reg + 8; 1344 1345 // patently false value 1346 return Hexagon::NoRegister; 1347 } 1348 1349 static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) { 1350 if (encoded_dreg < 4) 1351 return Hexagon::D0 + encoded_dreg; 1352 else if (encoded_dreg < 8) 1353 return Hexagon::D0 + encoded_dreg + 4; 1354 1355 // patently false value 1356 return Hexagon::NoRegister; 1357 } 1358 1359 void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode, 1360 unsigned inst) const { 1361 int64_t operand; 1362 MCOperand Op; 1363 switch (opcode) { 1364 case Hexagon::SL2_deallocframe: 1365 case Hexagon::SL2_jumpr31: 1366 case Hexagon::SL2_jumpr31_f: 1367 case Hexagon::SL2_jumpr31_fnew: 1368 case Hexagon::SL2_jumpr31_t: 1369 case Hexagon::SL2_jumpr31_tnew: 1370 case Hexagon::SL2_return: 1371 case Hexagon::SL2_return_f: 1372 case Hexagon::SL2_return_fnew: 1373 case Hexagon::SL2_return_t: 1374 case Hexagon::SL2_return_tnew: 1375 // no operands for these instructions 1376 break; 1377 case Hexagon::SS2_allocframe: 1378 // u 8-4{5_3} 1379 operand = ((inst & 0x1f0) >> 4) << 3; 1380 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1381 break; 1382 case Hexagon::SL1_loadri_io: 1383 // Rd 3-0, Rs 7-4, u 11-8{4_2} 1384 operand = getRegFromSubinstEncoding(inst & 0xf); 1385 Op = MCOperand::createReg(operand); 1386 MI->addOperand(Op); 1387 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1388 Op = MCOperand::createReg(operand); 1389 MI->addOperand(Op); 1390 operand = (inst & 0xf00) >> 6; 1391 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1392 break; 1393 case Hexagon::SL1_loadrub_io: 1394 // Rd 3-0, Rs 7-4, u 11-8 1395 operand = getRegFromSubinstEncoding(inst & 0xf); 1396 Op = MCOperand::createReg(operand); 1397 MI->addOperand(Op); 1398 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1399 Op = MCOperand::createReg(operand); 1400 MI->addOperand(Op); 1401 operand = (inst & 0xf00) >> 8; 1402 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1403 break; 1404 case Hexagon::SL2_loadrb_io: 1405 // Rd 3-0, Rs 7-4, u 10-8 1406 operand = getRegFromSubinstEncoding(inst & 0xf); 1407 Op = MCOperand::createReg(operand); 1408 MI->addOperand(Op); 1409 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1410 Op = MCOperand::createReg(operand); 1411 MI->addOperand(Op); 1412 operand = (inst & 0x700) >> 8; 1413 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1414 break; 1415 case Hexagon::SL2_loadrh_io: 1416 case Hexagon::SL2_loadruh_io: 1417 // Rd 3-0, Rs 7-4, u 10-8{3_1} 1418 operand = getRegFromSubinstEncoding(inst & 0xf); 1419 Op = MCOperand::createReg(operand); 1420 MI->addOperand(Op); 1421 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1422 Op = MCOperand::createReg(operand); 1423 MI->addOperand(Op); 1424 operand = ((inst & 0x700) >> 8) << 1; 1425 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1426 break; 1427 case Hexagon::SL2_loadrd_sp: 1428 // Rdd 2-0, u 7-3{5_3} 1429 operand = getDRegFromSubinstEncoding(inst & 0x7); 1430 Op = MCOperand::createReg(operand); 1431 MI->addOperand(Op); 1432 operand = ((inst & 0x0f8) >> 3) << 3; 1433 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1434 break; 1435 case Hexagon::SL2_loadri_sp: 1436 // Rd 3-0, u 8-4{5_2} 1437 operand = getRegFromSubinstEncoding(inst & 0xf); 1438 Op = MCOperand::createReg(operand); 1439 MI->addOperand(Op); 1440 operand = ((inst & 0x1f0) >> 4) << 2; 1441 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1442 break; 1443 case Hexagon::SA1_addi: 1444 // Rx 3-0 (x2), s7 10-4 1445 operand = getRegFromSubinstEncoding(inst & 0xf); 1446 Op = MCOperand::createReg(operand); 1447 MI->addOperand(Op); 1448 MI->addOperand(Op); 1449 operand = SignExtend64<7>((inst & 0x7f0) >> 4); 1450 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1451 break; 1452 case Hexagon::SA1_addrx: 1453 // Rx 3-0 (x2), Rs 7-4 1454 operand = getRegFromSubinstEncoding(inst & 0xf); 1455 Op = MCOperand::createReg(operand); 1456 MI->addOperand(Op); 1457 MI->addOperand(Op); 1458 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1459 Op = MCOperand::createReg(operand); 1460 MI->addOperand(Op); 1461 break; 1462 case Hexagon::SA1_and1: 1463 case Hexagon::SA1_dec: 1464 case Hexagon::SA1_inc: 1465 case Hexagon::SA1_sxtb: 1466 case Hexagon::SA1_sxth: 1467 case Hexagon::SA1_tfr: 1468 case Hexagon::SA1_zxtb: 1469 case Hexagon::SA1_zxth: 1470 // Rd 3-0, Rs 7-4 1471 operand = getRegFromSubinstEncoding(inst & 0xf); 1472 Op = MCOperand::createReg(operand); 1473 MI->addOperand(Op); 1474 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1475 Op = MCOperand::createReg(operand); 1476 MI->addOperand(Op); 1477 break; 1478 case Hexagon::SA1_addsp: 1479 // Rd 3-0, u 9-4{6_2} 1480 operand = getRegFromSubinstEncoding(inst & 0xf); 1481 Op = MCOperand::createReg(operand); 1482 MI->addOperand(Op); 1483 operand = ((inst & 0x3f0) >> 4) << 2; 1484 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1485 break; 1486 case Hexagon::SA1_seti: 1487 // Rd 3-0, u 9-4 1488 operand = getRegFromSubinstEncoding(inst & 0xf); 1489 Op = MCOperand::createReg(operand); 1490 MI->addOperand(Op); 1491 operand = (inst & 0x3f0) >> 4; 1492 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1493 break; 1494 case Hexagon::SA1_clrf: 1495 case Hexagon::SA1_clrfnew: 1496 case Hexagon::SA1_clrt: 1497 case Hexagon::SA1_clrtnew: 1498 case Hexagon::SA1_setin1: 1499 // Rd 3-0 1500 operand = getRegFromSubinstEncoding(inst & 0xf); 1501 Op = MCOperand::createReg(operand); 1502 MI->addOperand(Op); 1503 if (opcode == Hexagon::SA1_setin1) 1504 break; 1505 MI->addOperand(MCOperand::createReg(Hexagon::P0)); 1506 break; 1507 case Hexagon::SA1_cmpeqi: 1508 // Rs 7-4, u 1-0 1509 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1510 Op = MCOperand::createReg(operand); 1511 MI->addOperand(Op); 1512 operand = inst & 0x3; 1513 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1514 break; 1515 case Hexagon::SA1_combine0i: 1516 case Hexagon::SA1_combine1i: 1517 case Hexagon::SA1_combine2i: 1518 case Hexagon::SA1_combine3i: 1519 // Rdd 2-0, u 6-5 1520 operand = getDRegFromSubinstEncoding(inst & 0x7); 1521 Op = MCOperand::createReg(operand); 1522 MI->addOperand(Op); 1523 operand = (inst & 0x060) >> 5; 1524 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1525 break; 1526 case Hexagon::SA1_combinerz: 1527 case Hexagon::SA1_combinezr: 1528 // Rdd 2-0, Rs 7-4 1529 operand = getDRegFromSubinstEncoding(inst & 0x7); 1530 Op = MCOperand::createReg(operand); 1531 MI->addOperand(Op); 1532 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1533 Op = MCOperand::createReg(operand); 1534 MI->addOperand(Op); 1535 break; 1536 case Hexagon::SS1_storeb_io: 1537 // Rs 7-4, u 11-8, Rt 3-0 1538 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1539 Op = MCOperand::createReg(operand); 1540 MI->addOperand(Op); 1541 operand = (inst & 0xf00) >> 8; 1542 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1543 operand = getRegFromSubinstEncoding(inst & 0xf); 1544 Op = MCOperand::createReg(operand); 1545 MI->addOperand(Op); 1546 break; 1547 case Hexagon::SS1_storew_io: 1548 // Rs 7-4, u 11-8{4_2}, Rt 3-0 1549 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1550 Op = MCOperand::createReg(operand); 1551 MI->addOperand(Op); 1552 operand = ((inst & 0xf00) >> 8) << 2; 1553 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1554 operand = getRegFromSubinstEncoding(inst & 0xf); 1555 Op = MCOperand::createReg(operand); 1556 MI->addOperand(Op); 1557 break; 1558 case Hexagon::SS2_storebi0: 1559 case Hexagon::SS2_storebi1: 1560 // Rs 7-4, u 3-0 1561 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1562 Op = MCOperand::createReg(operand); 1563 MI->addOperand(Op); 1564 operand = inst & 0xf; 1565 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1566 break; 1567 case Hexagon::SS2_storewi0: 1568 case Hexagon::SS2_storewi1: 1569 // Rs 7-4, u 3-0{4_2} 1570 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1571 Op = MCOperand::createReg(operand); 1572 MI->addOperand(Op); 1573 operand = (inst & 0xf) << 2; 1574 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1575 break; 1576 case Hexagon::SS2_stored_sp: 1577 // s 8-3{6_3}, Rtt 2-0 1578 operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3); 1579 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1580 operand = getDRegFromSubinstEncoding(inst & 0x7); 1581 Op = MCOperand::createReg(operand); 1582 MI->addOperand(Op); 1583 break; 1584 case Hexagon::SS2_storeh_io: 1585 // Rs 7-4, u 10-8{3_1}, Rt 3-0 1586 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1587 Op = MCOperand::createReg(operand); 1588 MI->addOperand(Op); 1589 operand = ((inst & 0x700) >> 8) << 1; 1590 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1591 operand = getRegFromSubinstEncoding(inst & 0xf); 1592 Op = MCOperand::createReg(operand); 1593 MI->addOperand(Op); 1594 break; 1595 case Hexagon::SS2_storew_sp: 1596 // u 8-4{5_2}, Rd 3-0 1597 operand = ((inst & 0x1f0) >> 4) << 2; 1598 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1599 operand = getRegFromSubinstEncoding(inst & 0xf); 1600 Op = MCOperand::createReg(operand); 1601 MI->addOperand(Op); 1602 break; 1603 default: 1604 // don't crash with an invalid subinstruction 1605 // llvm_unreachable("Invalid subinstruction in duplex instruction"); 1606 break; 1607 } 1608 } 1609