1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCInstrInfo.h" 16 #include "MCTargetDesc/HexagonMCTargetDesc.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/Endian.h" 28 #include "llvm/Support/MathExtras.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include <cassert> 32 #include <cstddef> 33 #include <cstdint> 34 #include <memory> 35 36 using namespace llvm; 37 using namespace Hexagon; 38 39 using DecodeStatus = MCDisassembler::DecodeStatus; 40 41 namespace { 42 43 /// \brief Hexagon disassembler for all Hexagon platforms. 44 class HexagonDisassembler : public MCDisassembler { 45 public: 46 std::unique_ptr<MCInstrInfo const> const MCII; 47 std::unique_ptr<MCInst *> CurrentBundle; 48 mutable MCInst const *CurrentExtender; 49 50 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 51 MCInstrInfo const *MCII) 52 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), 53 CurrentExtender(nullptr) {} 54 55 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 56 ArrayRef<uint8_t> Bytes, uint64_t Address, 57 raw_ostream &VStream, raw_ostream &CStream, 58 bool &Complete) const; 59 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 60 ArrayRef<uint8_t> Bytes, uint64_t Address, 61 raw_ostream &VStream, 62 raw_ostream &CStream) const override; 63 void remapInstruction(MCInst &Instr) const; 64 }; 65 66 static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI, 67 int64_t Value) { 68 MCInstrInfo MCII = *Disassembler.MCII; 69 if (!Disassembler.CurrentExtender || 70 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 71 return Value; 72 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 73 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 74 int64_t Bits; 75 bool Success = 76 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute( 77 Bits); 78 assert(Success); 79 (void)Success; 80 uint64_t Upper26 = static_cast<uint64_t>(Bits); 81 uint64_t Operand = Upper26 | Lower6; 82 return Operand; 83 } 84 static HexagonDisassembler const &disassembler(void const *Decoder) { 85 return *static_cast<HexagonDisassembler const *>(Decoder); 86 } 87 template <size_t T> 88 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 89 HexagonDisassembler const &Disassembler = disassembler(Decoder); 90 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp)); 91 int64_t Extended = SignExtend64<32>(FullValue); 92 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 93 } 94 } 95 96 // Forward declare these because the auto-generated code will reference them. 97 // Definitions are further down. 98 99 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus 116 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 140 uint64_t /*Address*/, const void *Decoder); 141 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 142 const void *Decoder); 143 144 #include "HexagonDepDecoders.h" 145 #include "HexagonGenDisassemblerTables.inc" 146 147 static MCDisassembler *createHexagonDisassembler(const Target &T, 148 const MCSubtargetInfo &STI, 149 MCContext &Ctx) { 150 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 151 } 152 153 extern "C" void LLVMInitializeHexagonDisassembler() { 154 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 155 createHexagonDisassembler); 156 } 157 158 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 159 ArrayRef<uint8_t> Bytes, 160 uint64_t Address, 161 raw_ostream &os, 162 raw_ostream &cs) const { 163 (void)&s10_0ImmDecoder; 164 (void)&s10_6ImmDecoder; 165 DecodeStatus Result = DecodeStatus::Success; 166 bool Complete = false; 167 Size = 0; 168 169 *CurrentBundle = &MI; 170 MI.setOpcode(Hexagon::BUNDLE); 171 MI.addOperand(MCOperand::createImm(0)); 172 while (Result == Success && !Complete) { 173 if (Bytes.size() < HEXAGON_INSTR_SIZE) 174 return MCDisassembler::Fail; 175 MCInst *Inst = new (getContext()) MCInst; 176 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 177 MI.addOperand(MCOperand::createInst(Inst)); 178 Size += HEXAGON_INSTR_SIZE; 179 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 180 } 181 if (Result == MCDisassembler::Fail) 182 return Result; 183 if (Size > HEXAGON_MAX_PACKET_SIZE) 184 return MCDisassembler::Fail; 185 HexagonMCChecker Checker(getContext(), *MCII, STI, MI, 186 *getContext().getRegisterInfo(), false); 187 if (!Checker.check()) 188 return MCDisassembler::Fail; 189 remapInstruction(MI); 190 return MCDisassembler::Success; 191 } 192 193 void HexagonDisassembler::remapInstruction(MCInst &Instr) const { 194 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) { 195 auto &MI = const_cast<MCInst &>(*I.getInst()); 196 switch (MI.getOpcode()) { 197 case Hexagon::S2_allocframe: 198 if (MI.getOperand(0).getReg() == Hexagon::R29) { 199 MI.setOpcode(Hexagon::S6_allocframe_to_raw); 200 MI.erase(MI.begin () + 1); 201 MI.erase(MI.begin ()); 202 } 203 break; 204 case Hexagon::L2_deallocframe: 205 if (MI.getOperand(0).getReg() == Hexagon::D15 && 206 MI.getOperand(1).getReg() == Hexagon::R30) { 207 MI.setOpcode(L6_deallocframe_map_to_raw); 208 MI.erase(MI.begin () + 1); 209 MI.erase(MI.begin ()); 210 } 211 break; 212 case Hexagon::L4_return: 213 if (MI.getOperand(0).getReg() == Hexagon::D15 && 214 MI.getOperand(1).getReg() == Hexagon::R30) { 215 MI.setOpcode(L6_return_map_to_raw); 216 MI.erase(MI.begin () + 1); 217 MI.erase(MI.begin ()); 218 } 219 break; 220 case Hexagon::L4_return_t: 221 if (MI.getOperand(0).getReg() == Hexagon::D15 && 222 MI.getOperand(2).getReg() == Hexagon::R30) { 223 MI.setOpcode(L4_return_map_to_raw_t); 224 MI.erase(MI.begin () + 2); 225 MI.erase(MI.begin ()); 226 } 227 break; 228 case Hexagon::L4_return_f: 229 if (MI.getOperand(0).getReg() == Hexagon::D15 && 230 MI.getOperand(2).getReg() == Hexagon::R30) { 231 MI.setOpcode(L4_return_map_to_raw_f); 232 MI.erase(MI.begin () + 2); 233 MI.erase(MI.begin ()); 234 } 235 break; 236 case Hexagon::L4_return_tnew_pt: 237 if (MI.getOperand(0).getReg() == Hexagon::D15 && 238 MI.getOperand(2).getReg() == Hexagon::R30) { 239 MI.setOpcode(L4_return_map_to_raw_tnew_pt); 240 MI.erase(MI.begin () + 2); 241 MI.erase(MI.begin ()); 242 } 243 break; 244 case Hexagon::L4_return_fnew_pt: 245 if (MI.getOperand(0).getReg() == Hexagon::D15 && 246 MI.getOperand(2).getReg() == Hexagon::R30) { 247 MI.setOpcode(L4_return_map_to_raw_fnew_pt); 248 MI.erase(MI.begin () + 2); 249 MI.erase(MI.begin ()); 250 } 251 break; 252 case Hexagon::L4_return_tnew_pnt: 253 if (MI.getOperand(0).getReg() == Hexagon::D15 && 254 MI.getOperand(2).getReg() == Hexagon::R30) { 255 MI.setOpcode(L4_return_map_to_raw_tnew_pnt); 256 MI.erase(MI.begin () + 2); 257 MI.erase(MI.begin ()); 258 } 259 break; 260 case Hexagon::L4_return_fnew_pnt: 261 if (MI.getOperand(0).getReg() == Hexagon::D15 && 262 MI.getOperand(2).getReg() == Hexagon::R30) { 263 MI.setOpcode(L4_return_map_to_raw_fnew_pnt); 264 MI.erase(MI.begin () + 2); 265 MI.erase(MI.begin ()); 266 } 267 break; 268 } 269 } 270 } 271 272 static void adjustDuplex(MCInst &MI, MCContext &Context) { 273 switch (MI.getOpcode()) { 274 case Hexagon::SA1_setin1: 275 MI.insert(MI.begin() + 1, 276 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 277 break; 278 case Hexagon::SA1_dec: 279 MI.insert(MI.begin() + 2, 280 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 281 break; 282 default: 283 break; 284 } 285 } 286 287 DecodeStatus HexagonDisassembler::getSingleInstruction( 288 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 289 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 290 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 291 292 uint32_t Instruction = support::endian::read32le(Bytes.data()); 293 294 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 295 if ((Instruction & HexagonII::INST_PARSE_MASK) == 296 HexagonII::INST_PARSE_LOOP_END) { 297 if (BundleSize == 0) 298 HexagonMCInstrInfo::setInnerLoop(MCB); 299 else if (BundleSize == 1) 300 HexagonMCInstrInfo::setOuterLoop(MCB); 301 else 302 return DecodeStatus::Fail; 303 } 304 305 CurrentExtender = HexagonMCInstrInfo::extenderForIndex( 306 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 307 308 DecodeStatus Result = DecodeStatus::Fail; 309 if ((Instruction & HexagonII::INST_PARSE_MASK) == 310 HexagonII::INST_PARSE_DUPLEX) { 311 unsigned duplexIClass; 312 uint8_t const *DecodeLow, *DecodeHigh; 313 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 314 switch (duplexIClass) { 315 default: 316 return MCDisassembler::Fail; 317 case 0: 318 DecodeLow = DecoderTableSUBINSN_L132; 319 DecodeHigh = DecoderTableSUBINSN_L132; 320 break; 321 case 1: 322 DecodeLow = DecoderTableSUBINSN_L232; 323 DecodeHigh = DecoderTableSUBINSN_L132; 324 break; 325 case 2: 326 DecodeLow = DecoderTableSUBINSN_L232; 327 DecodeHigh = DecoderTableSUBINSN_L232; 328 break; 329 case 3: 330 DecodeLow = DecoderTableSUBINSN_A32; 331 DecodeHigh = DecoderTableSUBINSN_A32; 332 break; 333 case 4: 334 DecodeLow = DecoderTableSUBINSN_L132; 335 DecodeHigh = DecoderTableSUBINSN_A32; 336 break; 337 case 5: 338 DecodeLow = DecoderTableSUBINSN_L232; 339 DecodeHigh = DecoderTableSUBINSN_A32; 340 break; 341 case 6: 342 DecodeLow = DecoderTableSUBINSN_S132; 343 DecodeHigh = DecoderTableSUBINSN_A32; 344 break; 345 case 7: 346 DecodeLow = DecoderTableSUBINSN_S232; 347 DecodeHigh = DecoderTableSUBINSN_A32; 348 break; 349 case 8: 350 DecodeLow = DecoderTableSUBINSN_S132; 351 DecodeHigh = DecoderTableSUBINSN_L132; 352 break; 353 case 9: 354 DecodeLow = DecoderTableSUBINSN_S132; 355 DecodeHigh = DecoderTableSUBINSN_L232; 356 break; 357 case 10: 358 DecodeLow = DecoderTableSUBINSN_S132; 359 DecodeHigh = DecoderTableSUBINSN_S132; 360 break; 361 case 11: 362 DecodeLow = DecoderTableSUBINSN_S232; 363 DecodeHigh = DecoderTableSUBINSN_S132; 364 break; 365 case 12: 366 DecodeLow = DecoderTableSUBINSN_S232; 367 DecodeHigh = DecoderTableSUBINSN_L132; 368 break; 369 case 13: 370 DecodeLow = DecoderTableSUBINSN_S232; 371 DecodeHigh = DecoderTableSUBINSN_L232; 372 break; 373 case 14: 374 DecodeLow = DecoderTableSUBINSN_S232; 375 DecodeHigh = DecoderTableSUBINSN_S232; 376 break; 377 } 378 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); 379 MCInst *MILow = new (getContext()) MCInst; 380 MCInst *MIHigh = new (getContext()) MCInst; 381 auto TmpExtender = CurrentExtender; 382 CurrentExtender = 383 nullptr; // constant extenders in duplex must always be in slot 1 384 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, 385 this, STI); 386 CurrentExtender = TmpExtender; 387 if (Result != DecodeStatus::Success) 388 return DecodeStatus::Fail; 389 adjustDuplex(*MILow, getContext()); 390 Result = decodeInstruction( 391 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); 392 if (Result != DecodeStatus::Success) 393 return DecodeStatus::Fail; 394 adjustDuplex(*MIHigh, getContext()); 395 MCOperand OPLow = MCOperand::createInst(MILow); 396 MCOperand OPHigh = MCOperand::createInst(MIHigh); 397 MI.addOperand(OPLow); 398 MI.addOperand(OPHigh); 399 Complete = true; 400 } else { 401 if ((Instruction & HexagonII::INST_PARSE_MASK) == 402 HexagonII::INST_PARSE_PACKET_END) 403 Complete = true; 404 405 if (CurrentExtender != nullptr) 406 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, 407 Address, this, STI); 408 409 if (Result != MCDisassembler::Success) 410 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, 411 STI); 412 413 if (Result != MCDisassembler::Success && 414 STI.getFeatureBits()[Hexagon::ExtensionHVX]) 415 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, 416 Address, this, STI); 417 418 } 419 420 switch (MI.getOpcode()) { 421 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 422 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 423 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 424 case Hexagon::J4_cmpeqn1_fp0_jump_t: 425 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 426 case Hexagon::J4_cmpeqn1_fp1_jump_t: 427 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 428 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 429 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 430 case Hexagon::J4_cmpeqn1_tp0_jump_t: 431 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 432 case Hexagon::J4_cmpeqn1_tp1_jump_t: 433 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 434 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 435 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 436 case Hexagon::J4_cmpgtn1_fp0_jump_t: 437 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 438 case Hexagon::J4_cmpgtn1_fp1_jump_t: 439 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 440 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 441 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 442 case Hexagon::J4_cmpgtn1_tp0_jump_t: 443 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 444 case Hexagon::J4_cmpgtn1_tp1_jump_t: 445 MI.insert(MI.begin() + 1, 446 MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 447 break; 448 default: 449 break; 450 } 451 452 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 453 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 454 MCOperand &MCO = MI.getOperand(OpIndex); 455 assert(MCO.isReg() && "New value consumers must be registers"); 456 unsigned Register = 457 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 458 if ((Register & 0x6) == 0) 459 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 460 return MCDisassembler::Fail; 461 unsigned Lookback = (Register & 0x6) >> 1; 462 unsigned Offset = 1; 463 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 464 bool PrevVector = false; 465 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 466 auto i = Instructions.end() - 1; 467 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 468 if (i == n) 469 // Couldn't find producer 470 return MCDisassembler::Fail; 471 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst()); 472 if (Vector && !CurrentVector) 473 // Skip scalars when calculating distances for vectors 474 ++Lookback; 475 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector)) 476 ++Lookback; 477 PrevVector = CurrentVector; 478 if (Offset == Lookback) 479 break; 480 } 481 auto const &Inst = *i->getInst(); 482 bool SubregBit = (Register & 0x1) != 0; 483 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 484 // If subreg bit is set we're selecting the second produced newvalue 485 unsigned Producer = SubregBit ? 486 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() : 487 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 488 assert(Producer != Hexagon::NoRegister); 489 MCO.setReg(Producer); 490 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 491 unsigned Producer = 492 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 493 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 494 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 495 else if (SubregBit) 496 // Hexagon PRM 10.11 New-value operands 497 // Nt[0] is reserved and should always be encoded as zero. 498 return MCDisassembler::Fail; 499 assert(Producer != Hexagon::NoRegister); 500 MCO.setReg(Producer); 501 } else 502 return MCDisassembler::Fail; 503 } 504 505 if (CurrentExtender != nullptr) { 506 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) 507 ? *MI.getOperand(1).getInst() 508 : MI; 509 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 510 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 511 return MCDisassembler::Fail; 512 } 513 return Result; 514 } 515 516 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 517 ArrayRef<MCPhysReg> Table) { 518 if (RegNo < Table.size()) { 519 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 520 return MCDisassembler::Success; 521 } 522 523 return MCDisassembler::Fail; 524 } 525 526 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 527 uint64_t Address, 528 const void *Decoder) { 529 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 530 } 531 532 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 533 uint64_t Address, 534 const void *Decoder) { 535 static const MCPhysReg IntRegDecoderTable[] = { 536 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 537 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 538 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 539 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 540 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 541 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 542 Hexagon::R30, Hexagon::R31}; 543 544 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 545 } 546 547 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 548 unsigned RegNo, 549 uint64_t Address, 550 const void *Decoder) { 551 static const MCPhysReg GeneralSubRegDecoderTable[] = { 552 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 553 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, 554 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 555 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 556 }; 557 558 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); 559 } 560 561 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 562 uint64_t /*Address*/, 563 const void *Decoder) { 564 static const MCPhysReg HvxVRDecoderTable[] = { 565 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 566 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 567 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 568 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 569 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 570 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 571 Hexagon::V30, Hexagon::V31}; 572 573 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); 574 } 575 576 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 577 uint64_t /*Address*/, 578 const void *Decoder) { 579 static const MCPhysReg DoubleRegDecoderTable[] = { 580 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 581 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 582 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 583 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 584 585 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 586 } 587 588 static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( 589 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { 590 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { 591 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 592 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; 593 594 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); 595 } 596 597 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 598 uint64_t /*Address*/, 599 const void *Decoder) { 600 static const MCPhysReg HvxWRDecoderTable[] = { 601 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 602 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 603 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 604 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 605 606 return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable)); 607 } 608 609 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 610 uint64_t /*Address*/, 611 const void *Decoder) { 612 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 613 Hexagon::P2, Hexagon::P3}; 614 615 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 616 } 617 618 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 619 uint64_t /*Address*/, 620 const void *Decoder) { 621 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 622 Hexagon::Q2, Hexagon::Q3}; 623 624 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); 625 } 626 627 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 628 uint64_t /*Address*/, 629 const void *Decoder) { 630 using namespace Hexagon; 631 632 static const MCPhysReg CtrlRegDecoderTable[] = { 633 /* 0 */ SA0, LC0, SA1, LC1, 634 /* 4 */ P3_0, C5, M0, M1, 635 /* 8 */ USR, PC, UGP, GP, 636 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, 637 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, 638 /* 20 */ 0, 0, 0, 0, 639 /* 24 */ 0, 0, 0, 0, 640 /* 28 */ 0, 0, UTIMERLO, UTIMERHI 641 }; 642 643 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 644 return MCDisassembler::Fail; 645 646 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 647 if (CtrlRegDecoderTable[RegNo] == NoRegister) 648 return MCDisassembler::Fail; 649 650 unsigned Register = CtrlRegDecoderTable[RegNo]; 651 Inst.addOperand(MCOperand::createReg(Register)); 652 return MCDisassembler::Success; 653 } 654 655 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 656 uint64_t /*Address*/, 657 const void *Decoder) { 658 using namespace Hexagon; 659 660 static const MCPhysReg CtrlReg64DecoderTable[] = { 661 /* 0 */ C1_0, 0, C3_2, 0, 662 /* 4 */ C5_4, 0, C7_6, 0, 663 /* 8 */ C9_8, 0, C11_10, 0, 664 /* 12 */ CS, 0, UPCYCLE, 0, 665 /* 16 */ C17_16, 0, PKTCOUNT, 0, 666 /* 20 */ 0, 0, 0, 0, 667 /* 24 */ 0, 0, 0, 0, 668 /* 28 */ 0, 0, UTIMER, 0 669 }; 670 671 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 672 return MCDisassembler::Fail; 673 674 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 675 if (CtrlReg64DecoderTable[RegNo] == NoRegister) 676 return MCDisassembler::Fail; 677 678 unsigned Register = CtrlReg64DecoderTable[RegNo]; 679 Inst.addOperand(MCOperand::createReg(Register)); 680 return MCDisassembler::Success; 681 } 682 683 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 684 uint64_t /*Address*/, 685 const void *Decoder) { 686 unsigned Register = 0; 687 switch (RegNo) { 688 case 0: 689 Register = Hexagon::M0; 690 break; 691 case 1: 692 Register = Hexagon::M1; 693 break; 694 default: 695 return MCDisassembler::Fail; 696 } 697 Inst.addOperand(MCOperand::createReg(Register)); 698 return MCDisassembler::Success; 699 } 700 701 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 702 uint64_t /*Address*/, 703 const void *Decoder) { 704 HexagonDisassembler const &Disassembler = disassembler(Decoder); 705 int64_t FullValue = fullValue(Disassembler, MI, tmp); 706 assert(FullValue >= 0 && "Negative in unsigned decoder"); 707 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 708 return MCDisassembler::Success; 709 } 710 711 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 712 uint64_t /*Address*/, const void *Decoder) { 713 HexagonDisassembler const &Disassembler = disassembler(Decoder); 714 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 715 tmp = SignExtend64(tmp, Bits); 716 signedDecoder<32>(MI, tmp, Decoder); 717 return MCDisassembler::Success; 718 } 719 720 // custom decoder for various jump/call immediates 721 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 722 const void *Decoder) { 723 HexagonDisassembler const &Disassembler = disassembler(Decoder); 724 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 725 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 726 if (Bits == 0) 727 Bits = 15; 728 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits)); 729 uint32_t Extended = FullValue + Address; 730 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) 731 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 732 return MCDisassembler::Success; 733 } 734