1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "Hexagon.h" 11 #include "MCTargetDesc/HexagonBaseInfo.h" 12 #include "MCTargetDesc/HexagonMCInstrInfo.h" 13 #include "MCTargetDesc/HexagonMCTargetDesc.h" 14 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/Endian.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/LEB128.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <array> 29 #include <vector> 30 31 using namespace llvm; 32 using namespace Hexagon; 33 34 #define DEBUG_TYPE "hexagon-disassembler" 35 36 // Pull DecodeStatus and its enum values into the global namespace. 37 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 38 39 namespace { 40 /// \brief Hexagon disassembler for all Hexagon platforms. 41 class HexagonDisassembler : public MCDisassembler { 42 public: 43 std::unique_ptr<MCInst *> CurrentBundle; 44 HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx) 45 : MCDisassembler(STI, Ctx), CurrentBundle(new MCInst *) {} 46 47 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 48 ArrayRef<uint8_t> Bytes, uint64_t Address, 49 raw_ostream &VStream, raw_ostream &CStream, 50 bool &Complete) const; 51 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 52 ArrayRef<uint8_t> Bytes, uint64_t Address, 53 raw_ostream &VStream, 54 raw_ostream &CStream) const override; 55 }; 56 } 57 58 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 59 uint64_t Address, 60 const void *Decoder); 61 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 62 uint64_t Address, 63 const void *Decoder); 64 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 65 uint64_t Address, 66 const void *Decoder); 67 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 68 uint64_t Address, 69 const void *Decoder); 70 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 71 uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 void const *Decoder); 79 80 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 81 raw_ostream &os); 82 static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst); 83 84 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 85 const void *Decoder); 86 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 89 const void *Decoder); 90 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 91 const void *Decoder); 92 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 95 const void *Decoder); 96 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 97 const void *Decoder); 98 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 101 const void *Decoder); 102 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 103 const void *Decoder); 104 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 113 const void *Decoder); 114 115 static const uint16_t IntRegDecoderTable[] = { 116 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 117 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 118 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 119 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 120 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 121 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 122 Hexagon::R30, Hexagon::R31}; 123 124 static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 125 Hexagon::P2, Hexagon::P3}; 126 127 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 128 const uint16_t Table[], size_t Size) { 129 if (RegNo < Size) { 130 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 131 return MCDisassembler::Success; 132 } else 133 return MCDisassembler::Fail; 134 } 135 136 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 137 uint64_t /*Address*/, 138 void const *Decoder) { 139 if (RegNo > 31) 140 return MCDisassembler::Fail; 141 142 unsigned Register = IntRegDecoderTable[RegNo]; 143 Inst.addOperand(MCOperand::createReg(Register)); 144 return MCDisassembler::Success; 145 } 146 147 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 148 uint64_t /*Address*/, 149 const void *Decoder) { 150 static const uint16_t CtrlRegDecoderTable[] = { 151 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, 152 Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7, 153 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, 154 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH}; 155 156 if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0])) 157 return MCDisassembler::Fail; 158 159 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister) 160 return MCDisassembler::Fail; 161 162 unsigned Register = CtrlRegDecoderTable[RegNo]; 163 Inst.addOperand(MCOperand::createReg(Register)); 164 return MCDisassembler::Success; 165 } 166 167 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t /*Address*/, 169 void const *Decoder) { 170 static const uint16_t CtrlReg64DecoderTable[] = { 171 Hexagon::C1_0, Hexagon::NoRegister, Hexagon::C3_2, 172 Hexagon::NoRegister, Hexagon::NoRegister, Hexagon::NoRegister, 173 Hexagon::C7_6, Hexagon::NoRegister, Hexagon::C9_8, 174 Hexagon::NoRegister, Hexagon::C11_10, Hexagon::NoRegister, 175 Hexagon::CS, Hexagon::NoRegister, Hexagon::UPC, 176 Hexagon::NoRegister}; 177 178 if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0])) 179 return MCDisassembler::Fail; 180 181 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister) 182 return MCDisassembler::Fail; 183 184 unsigned Register = CtrlReg64DecoderTable[RegNo]; 185 Inst.addOperand(MCOperand::createReg(Register)); 186 return MCDisassembler::Success; 187 } 188 189 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 190 uint64_t /*Address*/, 191 const void *Decoder) { 192 unsigned Register = 0; 193 switch (RegNo) { 194 case 0: 195 Register = Hexagon::M0; 196 break; 197 case 1: 198 Register = Hexagon::M1; 199 break; 200 default: 201 return MCDisassembler::Fail; 202 } 203 Inst.addOperand(MCOperand::createReg(Register)); 204 return MCDisassembler::Success; 205 } 206 207 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t /*Address*/, 209 const void *Decoder) { 210 static const uint16_t DoubleRegDecoderTable[] = { 211 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 212 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 213 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 214 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 215 216 return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable, 217 sizeof(DoubleRegDecoderTable))); 218 } 219 220 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 221 uint64_t /*Address*/, 222 void const *Decoder) { 223 if (RegNo > 3) 224 return MCDisassembler::Fail; 225 226 unsigned Register = PredRegDecoderTable[RegNo]; 227 Inst.addOperand(MCOperand::createReg(Register)); 228 return MCDisassembler::Success; 229 } 230 231 #include "HexagonGenDisassemblerTables.inc" 232 233 static MCDisassembler *createHexagonDisassembler(Target const &T, 234 MCSubtargetInfo const &STI, 235 MCContext &Ctx) { 236 return new HexagonDisassembler(STI, Ctx); 237 } 238 239 extern "C" void LLVMInitializeHexagonDisassembler() { 240 TargetRegistry::RegisterMCDisassembler(TheHexagonTarget, 241 createHexagonDisassembler); 242 } 243 244 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 245 ArrayRef<uint8_t> Bytes, 246 uint64_t Address, 247 raw_ostream &os, 248 raw_ostream &cs) const { 249 DecodeStatus Result = DecodeStatus::Success; 250 bool Complete = false; 251 Size = 0; 252 253 *CurrentBundle = &MI; 254 MI.clear(); 255 MI.setOpcode(Hexagon::BUNDLE); 256 MI.addOperand(MCOperand::createImm(0)); 257 while (Result == Success && Complete == false) { 258 if (Bytes.size() < HEXAGON_INSTR_SIZE) 259 return MCDisassembler::Fail; 260 MCInst *Inst = new (getContext()) MCInst; 261 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 262 MI.addOperand(MCOperand::createInst(Inst)); 263 Size += HEXAGON_INSTR_SIZE; 264 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 265 } 266 return Result; 267 } 268 269 DecodeStatus HexagonDisassembler::getSingleInstruction( 270 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 271 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 272 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 273 274 uint32_t Instruction = 275 llvm::support::endian::read<uint32_t, llvm::support::little, 276 llvm::support::unaligned>(Bytes.data()); 277 278 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 279 if ((Instruction & HexagonII::INST_PARSE_MASK) == 280 HexagonII::INST_PARSE_LOOP_END) { 281 if (BundleSize == 0) 282 HexagonMCInstrInfo::setInnerLoop(MCB); 283 else if (BundleSize == 1) 284 HexagonMCInstrInfo::setOuterLoop(MCB); 285 else 286 return DecodeStatus::Fail; 287 } 288 289 DecodeStatus Result = DecodeStatus::Success; 290 if ((Instruction & HexagonII::INST_PARSE_MASK) == 291 HexagonII::INST_PARSE_DUPLEX) { 292 // Determine the instruction class of each instruction in the duplex. 293 unsigned duplexIClass, IClassLow, IClassHigh; 294 295 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 296 switch (duplexIClass) { 297 default: 298 return MCDisassembler::Fail; 299 case 0: 300 IClassLow = HexagonII::HSIG_L1; 301 IClassHigh = HexagonII::HSIG_L1; 302 break; 303 case 1: 304 IClassLow = HexagonII::HSIG_L2; 305 IClassHigh = HexagonII::HSIG_L1; 306 break; 307 case 2: 308 IClassLow = HexagonII::HSIG_L2; 309 IClassHigh = HexagonII::HSIG_L2; 310 break; 311 case 3: 312 IClassLow = HexagonII::HSIG_A; 313 IClassHigh = HexagonII::HSIG_A; 314 break; 315 case 4: 316 IClassLow = HexagonII::HSIG_L1; 317 IClassHigh = HexagonII::HSIG_A; 318 break; 319 case 5: 320 IClassLow = HexagonII::HSIG_L2; 321 IClassHigh = HexagonII::HSIG_A; 322 break; 323 case 6: 324 IClassLow = HexagonII::HSIG_S1; 325 IClassHigh = HexagonII::HSIG_A; 326 break; 327 case 7: 328 IClassLow = HexagonII::HSIG_S2; 329 IClassHigh = HexagonII::HSIG_A; 330 break; 331 case 8: 332 IClassLow = HexagonII::HSIG_S1; 333 IClassHigh = HexagonII::HSIG_L1; 334 break; 335 case 9: 336 IClassLow = HexagonII::HSIG_S1; 337 IClassHigh = HexagonII::HSIG_L2; 338 break; 339 case 10: 340 IClassLow = HexagonII::HSIG_S1; 341 IClassHigh = HexagonII::HSIG_S1; 342 break; 343 case 11: 344 IClassLow = HexagonII::HSIG_S2; 345 IClassHigh = HexagonII::HSIG_S1; 346 break; 347 case 12: 348 IClassLow = HexagonII::HSIG_S2; 349 IClassHigh = HexagonII::HSIG_L1; 350 break; 351 case 13: 352 IClassLow = HexagonII::HSIG_S2; 353 IClassHigh = HexagonII::HSIG_L2; 354 break; 355 case 14: 356 IClassLow = HexagonII::HSIG_S2; 357 IClassHigh = HexagonII::HSIG_S2; 358 break; 359 } 360 361 // Set the MCInst to be a duplex instruction. Which one doesn't matter. 362 MI.setOpcode(Hexagon::DuplexIClass0); 363 364 // Decode each instruction in the duplex. 365 // Create an MCInst for each instruction. 366 unsigned instLow = Instruction & 0x1fff; 367 unsigned instHigh = (Instruction >> 16) & 0x1fff; 368 unsigned opLow; 369 if (GetSubinstOpcode(IClassLow, instLow, opLow, os) != 370 MCDisassembler::Success) 371 return MCDisassembler::Fail; 372 unsigned opHigh; 373 if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) != 374 MCDisassembler::Success) 375 return MCDisassembler::Fail; 376 MCInst *MILow = new (getContext()) MCInst; 377 MILow->setOpcode(opLow); 378 MCInst *MIHigh = new (getContext()) MCInst; 379 MIHigh->setOpcode(opHigh); 380 AddSubinstOperands(MILow, opLow, instLow); 381 AddSubinstOperands(MIHigh, opHigh, instHigh); 382 // see ConvertToSubInst() in 383 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 384 385 // Add the duplex instruction MCInsts as operands to the passed in MCInst. 386 MCOperand OPLow = MCOperand::createInst(MILow); 387 MCOperand OPHigh = MCOperand::createInst(MIHigh); 388 MI.addOperand(OPLow); 389 MI.addOperand(OPHigh); 390 Complete = true; 391 } else { 392 if ((Instruction & HexagonII::INST_PARSE_MASK) == 393 HexagonII::INST_PARSE_PACKET_END) 394 Complete = true; 395 // Calling the auto-generated decoder function. 396 Result = 397 decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); 398 } 399 400 return Result; 401 } 402 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 403 uint64_t Address, 404 const void *Decoder) { 405 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 406 } 407 408 409 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 410 uint64_t /*Address*/, 411 const void *Decoder) { 412 static const uint16_t VecRegDecoderTable[] = { 413 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 414 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 415 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 416 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 417 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 418 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 419 Hexagon::V30, Hexagon::V31}; 420 421 return (DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable, 422 sizeof(VecRegDecoderTable))); 423 } 424 425 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 426 uint64_t /*Address*/, 427 const void *Decoder) { 428 static const uint16_t VecDblRegDecoderTable[] = { 429 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 430 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 431 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 432 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 433 434 return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable, 435 sizeof(VecDblRegDecoderTable))); 436 } 437 438 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 439 uint64_t /*Address*/, 440 const void *Decoder) { 441 static const uint16_t VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 442 Hexagon::Q2, Hexagon::Q3}; 443 444 return (DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable, 445 sizeof(VecPredRegDecoderTable))); 446 } 447 448 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, 449 uint64_t /*Address*/, const void *Decoder) { 450 uint64_t imm = SignExtend64<16>(tmp); 451 MI.addOperand(MCOperand::createImm(imm)); 452 return MCDisassembler::Success; 453 } 454 455 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, 456 uint64_t /*Address*/, const void *Decoder) { 457 uint64_t imm = SignExtend64<12>(tmp); 458 MI.addOperand(MCOperand::createImm(imm)); 459 return MCDisassembler::Success; 460 } 461 462 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, 463 uint64_t /*Address*/, const void *Decoder) { 464 uint64_t imm = SignExtend64<11>(tmp); 465 MI.addOperand(MCOperand::createImm(imm)); 466 return MCDisassembler::Success; 467 } 468 469 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, 470 uint64_t /*Address*/, const void *Decoder) { 471 uint64_t imm = SignExtend64<12>(tmp); 472 MI.addOperand(MCOperand::createImm(imm)); 473 return MCDisassembler::Success; 474 } 475 476 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, 477 uint64_t /*Address*/, const void *Decoder) { 478 uint64_t imm = SignExtend64<13>(tmp); 479 MI.addOperand(MCOperand::createImm(imm)); 480 return MCDisassembler::Success; 481 } 482 483 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, 484 uint64_t /*Address*/, const void *Decoder) { 485 uint64_t imm = SignExtend64<14>(tmp); 486 MI.addOperand(MCOperand::createImm(imm)); 487 return MCDisassembler::Success; 488 } 489 490 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, 491 uint64_t /*Address*/, const void *Decoder) { 492 uint64_t imm = SignExtend64<10>(tmp); 493 MI.addOperand(MCOperand::createImm(imm)); 494 return MCDisassembler::Success; 495 } 496 497 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, 498 const void *Decoder) { 499 uint64_t imm = SignExtend64<8>(tmp); 500 MI.addOperand(MCOperand::createImm(imm)); 501 return MCDisassembler::Success; 502 } 503 504 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, 505 uint64_t /*Address*/, const void *Decoder) { 506 uint64_t imm = SignExtend64<6>(tmp); 507 MI.addOperand(MCOperand::createImm(imm)); 508 return MCDisassembler::Success; 509 } 510 511 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, 512 uint64_t /*Address*/, const void *Decoder) { 513 uint64_t imm = SignExtend64<4>(tmp); 514 MI.addOperand(MCOperand::createImm(imm)); 515 return MCDisassembler::Success; 516 } 517 518 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, 519 uint64_t /*Address*/, const void *Decoder) { 520 uint64_t imm = SignExtend64<5>(tmp); 521 MI.addOperand(MCOperand::createImm(imm)); 522 return MCDisassembler::Success; 523 } 524 525 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, 526 uint64_t /*Address*/, const void *Decoder) { 527 uint64_t imm = SignExtend64<6>(tmp); 528 MI.addOperand(MCOperand::createImm(imm)); 529 return MCDisassembler::Success; 530 } 531 532 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, 533 uint64_t /*Address*/, const void *Decoder) { 534 uint64_t imm = SignExtend64<7>(tmp); 535 MI.addOperand(MCOperand::createImm(imm)); 536 return MCDisassembler::Success; 537 } 538 539 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, 540 uint64_t /*Address*/, const void *Decoder) { 541 uint64_t imm = SignExtend64<10>(tmp); 542 MI.addOperand(MCOperand::createImm(imm)); 543 return MCDisassembler::Success; 544 } 545 546 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, 547 uint64_t /*Address*/, const void *Decoder) { 548 uint64_t imm = SignExtend64<9>(tmp); 549 MI.addOperand(MCOperand::createImm(imm)); 550 return MCDisassembler::Success; 551 } 552 553 // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td 554 enum subInstBinaryValues { 555 V4_SA1_addi_BITS = 0x0000, 556 V4_SA1_addi_MASK = 0x1800, 557 V4_SA1_addrx_BITS = 0x1800, 558 V4_SA1_addrx_MASK = 0x1f00, 559 V4_SA1_addsp_BITS = 0x0c00, 560 V4_SA1_addsp_MASK = 0x1c00, 561 V4_SA1_and1_BITS = 0x1200, 562 V4_SA1_and1_MASK = 0x1f00, 563 V4_SA1_clrf_BITS = 0x1a70, 564 V4_SA1_clrf_MASK = 0x1e70, 565 V4_SA1_clrfnew_BITS = 0x1a50, 566 V4_SA1_clrfnew_MASK = 0x1e70, 567 V4_SA1_clrt_BITS = 0x1a60, 568 V4_SA1_clrt_MASK = 0x1e70, 569 V4_SA1_clrtnew_BITS = 0x1a40, 570 V4_SA1_clrtnew_MASK = 0x1e70, 571 V4_SA1_cmpeqi_BITS = 0x1900, 572 V4_SA1_cmpeqi_MASK = 0x1f00, 573 V4_SA1_combine0i_BITS = 0x1c00, 574 V4_SA1_combine0i_MASK = 0x1d18, 575 V4_SA1_combine1i_BITS = 0x1c08, 576 V4_SA1_combine1i_MASK = 0x1d18, 577 V4_SA1_combine2i_BITS = 0x1c10, 578 V4_SA1_combine2i_MASK = 0x1d18, 579 V4_SA1_combine3i_BITS = 0x1c18, 580 V4_SA1_combine3i_MASK = 0x1d18, 581 V4_SA1_combinerz_BITS = 0x1d08, 582 V4_SA1_combinerz_MASK = 0x1d08, 583 V4_SA1_combinezr_BITS = 0x1d00, 584 V4_SA1_combinezr_MASK = 0x1d08, 585 V4_SA1_dec_BITS = 0x1300, 586 V4_SA1_dec_MASK = 0x1f00, 587 V4_SA1_inc_BITS = 0x1100, 588 V4_SA1_inc_MASK = 0x1f00, 589 V4_SA1_seti_BITS = 0x0800, 590 V4_SA1_seti_MASK = 0x1c00, 591 V4_SA1_setin1_BITS = 0x1a00, 592 V4_SA1_setin1_MASK = 0x1e40, 593 V4_SA1_sxtb_BITS = 0x1500, 594 V4_SA1_sxtb_MASK = 0x1f00, 595 V4_SA1_sxth_BITS = 0x1400, 596 V4_SA1_sxth_MASK = 0x1f00, 597 V4_SA1_tfr_BITS = 0x1000, 598 V4_SA1_tfr_MASK = 0x1f00, 599 V4_SA1_zxtb_BITS = 0x1700, 600 V4_SA1_zxtb_MASK = 0x1f00, 601 V4_SA1_zxth_BITS = 0x1600, 602 V4_SA1_zxth_MASK = 0x1f00, 603 V4_SL1_loadri_io_BITS = 0x0000, 604 V4_SL1_loadri_io_MASK = 0x1000, 605 V4_SL1_loadrub_io_BITS = 0x1000, 606 V4_SL1_loadrub_io_MASK = 0x1000, 607 V4_SL2_deallocframe_BITS = 0x1f00, 608 V4_SL2_deallocframe_MASK = 0x1fc0, 609 V4_SL2_jumpr31_BITS = 0x1fc0, 610 V4_SL2_jumpr31_MASK = 0x1fc4, 611 V4_SL2_jumpr31_f_BITS = 0x1fc5, 612 V4_SL2_jumpr31_f_MASK = 0x1fc7, 613 V4_SL2_jumpr31_fnew_BITS = 0x1fc7, 614 V4_SL2_jumpr31_fnew_MASK = 0x1fc7, 615 V4_SL2_jumpr31_t_BITS = 0x1fc4, 616 V4_SL2_jumpr31_t_MASK = 0x1fc7, 617 V4_SL2_jumpr31_tnew_BITS = 0x1fc6, 618 V4_SL2_jumpr31_tnew_MASK = 0x1fc7, 619 V4_SL2_loadrb_io_BITS = 0x1000, 620 V4_SL2_loadrb_io_MASK = 0x1800, 621 V4_SL2_loadrd_sp_BITS = 0x1e00, 622 V4_SL2_loadrd_sp_MASK = 0x1f00, 623 V4_SL2_loadrh_io_BITS = 0x0000, 624 V4_SL2_loadrh_io_MASK = 0x1800, 625 V4_SL2_loadri_sp_BITS = 0x1c00, 626 V4_SL2_loadri_sp_MASK = 0x1e00, 627 V4_SL2_loadruh_io_BITS = 0x0800, 628 V4_SL2_loadruh_io_MASK = 0x1800, 629 V4_SL2_return_BITS = 0x1f40, 630 V4_SL2_return_MASK = 0x1fc4, 631 V4_SL2_return_f_BITS = 0x1f45, 632 V4_SL2_return_f_MASK = 0x1fc7, 633 V4_SL2_return_fnew_BITS = 0x1f47, 634 V4_SL2_return_fnew_MASK = 0x1fc7, 635 V4_SL2_return_t_BITS = 0x1f44, 636 V4_SL2_return_t_MASK = 0x1fc7, 637 V4_SL2_return_tnew_BITS = 0x1f46, 638 V4_SL2_return_tnew_MASK = 0x1fc7, 639 V4_SS1_storeb_io_BITS = 0x1000, 640 V4_SS1_storeb_io_MASK = 0x1000, 641 V4_SS1_storew_io_BITS = 0x0000, 642 V4_SS1_storew_io_MASK = 0x1000, 643 V4_SS2_allocframe_BITS = 0x1c00, 644 V4_SS2_allocframe_MASK = 0x1e00, 645 V4_SS2_storebi0_BITS = 0x1200, 646 V4_SS2_storebi0_MASK = 0x1f00, 647 V4_SS2_storebi1_BITS = 0x1300, 648 V4_SS2_storebi1_MASK = 0x1f00, 649 V4_SS2_stored_sp_BITS = 0x0a00, 650 V4_SS2_stored_sp_MASK = 0x1e00, 651 V4_SS2_storeh_io_BITS = 0x0000, 652 V4_SS2_storeh_io_MASK = 0x1800, 653 V4_SS2_storew_sp_BITS = 0x0800, 654 V4_SS2_storew_sp_MASK = 0x1e00, 655 V4_SS2_storewi0_BITS = 0x1000, 656 V4_SS2_storewi0_MASK = 0x1f00, 657 V4_SS2_storewi1_BITS = 0x1100, 658 V4_SS2_storewi1_MASK = 0x1f00 659 }; 660 661 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 662 raw_ostream &os) { 663 switch (IClass) { 664 case HexagonII::HSIG_L1: 665 if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS) 666 op = Hexagon::V4_SL1_loadri_io; 667 else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS) 668 op = Hexagon::V4_SL1_loadrub_io; 669 else { 670 os << "<unknown subinstruction>"; 671 return MCDisassembler::Fail; 672 } 673 break; 674 case HexagonII::HSIG_L2: 675 if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS) 676 op = Hexagon::V4_SL2_deallocframe; 677 else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS) 678 op = Hexagon::V4_SL2_jumpr31; 679 else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS) 680 op = Hexagon::V4_SL2_jumpr31_f; 681 else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS) 682 op = Hexagon::V4_SL2_jumpr31_fnew; 683 else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS) 684 op = Hexagon::V4_SL2_jumpr31_t; 685 else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS) 686 op = Hexagon::V4_SL2_jumpr31_tnew; 687 else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS) 688 op = Hexagon::V4_SL2_loadrb_io; 689 else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS) 690 op = Hexagon::V4_SL2_loadrd_sp; 691 else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS) 692 op = Hexagon::V4_SL2_loadrh_io; 693 else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS) 694 op = Hexagon::V4_SL2_loadri_sp; 695 else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS) 696 op = Hexagon::V4_SL2_loadruh_io; 697 else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS) 698 op = Hexagon::V4_SL2_return; 699 else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS) 700 op = Hexagon::V4_SL2_return_f; 701 else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS) 702 op = Hexagon::V4_SL2_return_fnew; 703 else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS) 704 op = Hexagon::V4_SL2_return_t; 705 else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS) 706 op = Hexagon::V4_SL2_return_tnew; 707 else { 708 os << "<unknown subinstruction>"; 709 return MCDisassembler::Fail; 710 } 711 break; 712 case HexagonII::HSIG_A: 713 if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS) 714 op = Hexagon::V4_SA1_addi; 715 else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS) 716 op = Hexagon::V4_SA1_addrx; 717 else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS) 718 op = Hexagon::V4_SA1_addsp; 719 else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS) 720 op = Hexagon::V4_SA1_and1; 721 else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS) 722 op = Hexagon::V4_SA1_clrf; 723 else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS) 724 op = Hexagon::V4_SA1_clrfnew; 725 else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS) 726 op = Hexagon::V4_SA1_clrt; 727 else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS) 728 op = Hexagon::V4_SA1_clrtnew; 729 else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS) 730 op = Hexagon::V4_SA1_cmpeqi; 731 else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS) 732 op = Hexagon::V4_SA1_combine0i; 733 else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS) 734 op = Hexagon::V4_SA1_combine1i; 735 else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS) 736 op = Hexagon::V4_SA1_combine2i; 737 else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS) 738 op = Hexagon::V4_SA1_combine3i; 739 else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS) 740 op = Hexagon::V4_SA1_combinerz; 741 else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS) 742 op = Hexagon::V4_SA1_combinezr; 743 else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS) 744 op = Hexagon::V4_SA1_dec; 745 else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS) 746 op = Hexagon::V4_SA1_inc; 747 else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS) 748 op = Hexagon::V4_SA1_seti; 749 else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS) 750 op = Hexagon::V4_SA1_setin1; 751 else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS) 752 op = Hexagon::V4_SA1_sxtb; 753 else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS) 754 op = Hexagon::V4_SA1_sxth; 755 else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS) 756 op = Hexagon::V4_SA1_tfr; 757 else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS) 758 op = Hexagon::V4_SA1_zxtb; 759 else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS) 760 op = Hexagon::V4_SA1_zxth; 761 else { 762 os << "<unknown subinstruction>"; 763 return MCDisassembler::Fail; 764 } 765 break; 766 case HexagonII::HSIG_S1: 767 if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS) 768 op = Hexagon::V4_SS1_storeb_io; 769 else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS) 770 op = Hexagon::V4_SS1_storew_io; 771 else { 772 os << "<unknown subinstruction>"; 773 return MCDisassembler::Fail; 774 } 775 break; 776 case HexagonII::HSIG_S2: 777 if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS) 778 op = Hexagon::V4_SS2_allocframe; 779 else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS) 780 op = Hexagon::V4_SS2_storebi0; 781 else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS) 782 op = Hexagon::V4_SS2_storebi1; 783 else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS) 784 op = Hexagon::V4_SS2_stored_sp; 785 else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS) 786 op = Hexagon::V4_SS2_storeh_io; 787 else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS) 788 op = Hexagon::V4_SS2_storew_sp; 789 else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS) 790 op = Hexagon::V4_SS2_storewi0; 791 else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS) 792 op = Hexagon::V4_SS2_storewi1; 793 else { 794 os << "<unknown subinstruction>"; 795 return MCDisassembler::Fail; 796 } 797 break; 798 default: 799 os << "<unknown>"; 800 return MCDisassembler::Fail; 801 } 802 return MCDisassembler::Success; 803 } 804 805 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) { 806 if (encoded_reg < 8) 807 return Hexagon::R0 + encoded_reg; 808 else if (encoded_reg < 16) 809 return Hexagon::R0 + encoded_reg + 8; 810 return Hexagon::NoRegister; 811 } 812 813 static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) { 814 if (encoded_dreg < 4) 815 return Hexagon::D0 + encoded_dreg; 816 else if (encoded_dreg < 8) 817 return Hexagon::D0 + encoded_dreg + 4; 818 return Hexagon::NoRegister; 819 } 820 821 static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) { 822 int64_t operand; 823 MCOperand Op; 824 switch (opcode) { 825 case Hexagon::V4_SL2_deallocframe: 826 case Hexagon::V4_SL2_jumpr31: 827 case Hexagon::V4_SL2_jumpr31_f: 828 case Hexagon::V4_SL2_jumpr31_fnew: 829 case Hexagon::V4_SL2_jumpr31_t: 830 case Hexagon::V4_SL2_jumpr31_tnew: 831 case Hexagon::V4_SL2_return: 832 case Hexagon::V4_SL2_return_f: 833 case Hexagon::V4_SL2_return_fnew: 834 case Hexagon::V4_SL2_return_t: 835 case Hexagon::V4_SL2_return_tnew: 836 // no operands for these instructions 837 break; 838 case Hexagon::V4_SS2_allocframe: 839 // u 8-4{5_3} 840 operand = ((inst & 0x1f0) >> 4) << 3; 841 Op = MCOperand::createImm(operand); 842 MI->addOperand(Op); 843 break; 844 case Hexagon::V4_SL1_loadri_io: 845 // Rd 3-0, Rs 7-4, u 11-8{4_2} 846 operand = getRegFromSubinstEncoding(inst & 0xf); 847 Op = MCOperand::createReg(operand); 848 MI->addOperand(Op); 849 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 850 Op = MCOperand::createReg(operand); 851 MI->addOperand(Op); 852 operand = (inst & 0xf00) >> 6; 853 Op = MCOperand::createImm(operand); 854 MI->addOperand(Op); 855 break; 856 case Hexagon::V4_SL1_loadrub_io: 857 // Rd 3-0, Rs 7-4, u 11-8 858 operand = getRegFromSubinstEncoding(inst & 0xf); 859 Op = MCOperand::createReg(operand); 860 MI->addOperand(Op); 861 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 862 Op = MCOperand::createReg(operand); 863 MI->addOperand(Op); 864 operand = (inst & 0xf00) >> 8; 865 Op = MCOperand::createImm(operand); 866 MI->addOperand(Op); 867 break; 868 case Hexagon::V4_SL2_loadrb_io: 869 // Rd 3-0, Rs 7-4, u 10-8 870 operand = getRegFromSubinstEncoding(inst & 0xf); 871 Op = MCOperand::createReg(operand); 872 MI->addOperand(Op); 873 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 874 Op = MCOperand::createReg(operand); 875 MI->addOperand(Op); 876 operand = (inst & 0x700) >> 8; 877 Op = MCOperand::createImm(operand); 878 MI->addOperand(Op); 879 break; 880 case Hexagon::V4_SL2_loadrh_io: 881 case Hexagon::V4_SL2_loadruh_io: 882 // Rd 3-0, Rs 7-4, u 10-8{3_1} 883 operand = getRegFromSubinstEncoding(inst & 0xf); 884 Op = MCOperand::createReg(operand); 885 MI->addOperand(Op); 886 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 887 Op = MCOperand::createReg(operand); 888 MI->addOperand(Op); 889 operand = ((inst & 0x700) >> 8) << 1; 890 Op = MCOperand::createImm(operand); 891 MI->addOperand(Op); 892 break; 893 case Hexagon::V4_SL2_loadrd_sp: 894 // Rdd 2-0, u 7-3{5_3} 895 operand = getDRegFromSubinstEncoding(inst & 0x7); 896 Op = MCOperand::createReg(operand); 897 MI->addOperand(Op); 898 operand = ((inst & 0x0f8) >> 3) << 3; 899 Op = MCOperand::createImm(operand); 900 MI->addOperand(Op); 901 break; 902 case Hexagon::V4_SL2_loadri_sp: 903 // Rd 3-0, u 8-4{5_2} 904 operand = getRegFromSubinstEncoding(inst & 0xf); 905 Op = MCOperand::createReg(operand); 906 MI->addOperand(Op); 907 operand = ((inst & 0x1f0) >> 4) << 2; 908 Op = MCOperand::createImm(operand); 909 MI->addOperand(Op); 910 break; 911 case Hexagon::V4_SA1_addi: 912 // Rx 3-0 (x2), s7 10-4 913 operand = getRegFromSubinstEncoding(inst & 0xf); 914 Op = MCOperand::createReg(operand); 915 MI->addOperand(Op); 916 MI->addOperand(Op); 917 operand = SignExtend64<7>((inst & 0x7f0) >> 4); 918 Op = MCOperand::createImm(operand); 919 MI->addOperand(Op); 920 break; 921 case Hexagon::V4_SA1_addrx: 922 // Rx 3-0 (x2), Rs 7-4 923 operand = getRegFromSubinstEncoding(inst & 0xf); 924 Op = MCOperand::createReg(operand); 925 MI->addOperand(Op); 926 MI->addOperand(Op); 927 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 928 Op = MCOperand::createReg(operand); 929 MI->addOperand(Op); 930 case Hexagon::V4_SA1_and1: 931 case Hexagon::V4_SA1_dec: 932 case Hexagon::V4_SA1_inc: 933 case Hexagon::V4_SA1_sxtb: 934 case Hexagon::V4_SA1_sxth: 935 case Hexagon::V4_SA1_tfr: 936 case Hexagon::V4_SA1_zxtb: 937 case Hexagon::V4_SA1_zxth: 938 // Rd 3-0, Rs 7-4 939 operand = getRegFromSubinstEncoding(inst & 0xf); 940 Op = MCOperand::createReg(operand); 941 MI->addOperand(Op); 942 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 943 Op = MCOperand::createReg(operand); 944 MI->addOperand(Op); 945 break; 946 case Hexagon::V4_SA1_addsp: 947 // Rd 3-0, u 9-4{6_2} 948 operand = getRegFromSubinstEncoding(inst & 0xf); 949 Op = MCOperand::createReg(operand); 950 MI->addOperand(Op); 951 operand = ((inst & 0x3f0) >> 4) << 2; 952 Op = MCOperand::createImm(operand); 953 MI->addOperand(Op); 954 break; 955 case Hexagon::V4_SA1_seti: 956 // Rd 3-0, u 9-4 957 operand = getRegFromSubinstEncoding(inst & 0xf); 958 Op = MCOperand::createReg(operand); 959 MI->addOperand(Op); 960 operand = (inst & 0x3f0) >> 4; 961 Op = MCOperand::createImm(operand); 962 MI->addOperand(Op); 963 break; 964 case Hexagon::V4_SA1_clrf: 965 case Hexagon::V4_SA1_clrfnew: 966 case Hexagon::V4_SA1_clrt: 967 case Hexagon::V4_SA1_clrtnew: 968 case Hexagon::V4_SA1_setin1: 969 // Rd 3-0 970 operand = getRegFromSubinstEncoding(inst & 0xf); 971 Op = MCOperand::createReg(operand); 972 MI->addOperand(Op); 973 break; 974 case Hexagon::V4_SA1_cmpeqi: 975 // Rs 7-4, u 1-0 976 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 977 Op = MCOperand::createReg(operand); 978 MI->addOperand(Op); 979 operand = inst & 0x3; 980 Op = MCOperand::createImm(operand); 981 MI->addOperand(Op); 982 break; 983 case Hexagon::V4_SA1_combine0i: 984 case Hexagon::V4_SA1_combine1i: 985 case Hexagon::V4_SA1_combine2i: 986 case Hexagon::V4_SA1_combine3i: 987 // Rdd 2-0, u 6-5 988 operand = getDRegFromSubinstEncoding(inst & 0x7); 989 Op = MCOperand::createReg(operand); 990 MI->addOperand(Op); 991 operand = (inst & 0x060) >> 5; 992 Op = MCOperand::createImm(operand); 993 MI->addOperand(Op); 994 break; 995 case Hexagon::V4_SA1_combinerz: 996 case Hexagon::V4_SA1_combinezr: 997 // Rdd 2-0, Rs 7-4 998 operand = getDRegFromSubinstEncoding(inst & 0x7); 999 Op = MCOperand::createReg(operand); 1000 MI->addOperand(Op); 1001 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1002 Op = MCOperand::createReg(operand); 1003 MI->addOperand(Op); 1004 break; 1005 case Hexagon::V4_SS1_storeb_io: 1006 // Rs 7-4, u 11-8, Rt 3-0 1007 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1008 Op = MCOperand::createReg(operand); 1009 MI->addOperand(Op); 1010 operand = (inst & 0xf00) >> 8; 1011 Op = MCOperand::createImm(operand); 1012 MI->addOperand(Op); 1013 operand = getRegFromSubinstEncoding(inst & 0xf); 1014 Op = MCOperand::createReg(operand); 1015 MI->addOperand(Op); 1016 break; 1017 case Hexagon::V4_SS1_storew_io: 1018 // Rs 7-4, u 11-8{4_2}, Rt 3-0 1019 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1020 Op = MCOperand::createReg(operand); 1021 MI->addOperand(Op); 1022 operand = ((inst & 0xf00) >> 8) << 2; 1023 Op = MCOperand::createImm(operand); 1024 MI->addOperand(Op); 1025 operand = getRegFromSubinstEncoding(inst & 0xf); 1026 Op = MCOperand::createReg(operand); 1027 MI->addOperand(Op); 1028 break; 1029 case Hexagon::V4_SS2_storebi0: 1030 case Hexagon::V4_SS2_storebi1: 1031 // Rs 7-4, u 3-0 1032 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1033 Op = MCOperand::createReg(operand); 1034 MI->addOperand(Op); 1035 operand = inst & 0xf; 1036 Op = MCOperand::createImm(operand); 1037 MI->addOperand(Op); 1038 break; 1039 case Hexagon::V4_SS2_storewi0: 1040 case Hexagon::V4_SS2_storewi1: 1041 // Rs 7-4, u 3-0{4_2} 1042 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1043 Op = MCOperand::createReg(operand); 1044 MI->addOperand(Op); 1045 operand = (inst & 0xf) << 2; 1046 Op = MCOperand::createImm(operand); 1047 MI->addOperand(Op); 1048 break; 1049 case Hexagon::V4_SS2_stored_sp: 1050 // s 8-3{6_3}, Rtt 2-0 1051 operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3); 1052 Op = MCOperand::createImm(operand); 1053 MI->addOperand(Op); 1054 operand = getDRegFromSubinstEncoding(inst & 0x7); 1055 Op = MCOperand::createReg(operand); 1056 MI->addOperand(Op); 1057 case Hexagon::V4_SS2_storeh_io: 1058 // Rs 7-4, u 10-8{3_1}, Rt 3-0 1059 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1060 Op = MCOperand::createReg(operand); 1061 MI->addOperand(Op); 1062 operand = ((inst & 0x700) >> 8) << 1; 1063 Op = MCOperand::createImm(operand); 1064 MI->addOperand(Op); 1065 operand = getRegFromSubinstEncoding(inst & 0xf); 1066 Op = MCOperand::createReg(operand); 1067 MI->addOperand(Op); 1068 break; 1069 case Hexagon::V4_SS2_storew_sp: 1070 // u 8-4{5_2}, Rd 3-0 1071 operand = ((inst & 0x1f0) >> 4) << 2; 1072 Op = MCOperand::createImm(operand); 1073 MI->addOperand(Op); 1074 operand = getRegFromSubinstEncoding(inst & 0xf); 1075 Op = MCOperand::createReg(operand); 1076 MI->addOperand(Op); 1077 break; 1078 default: 1079 // don't crash with an invalid subinstruction 1080 // llvm_unreachable("Invalid subinstruction in duplex instruction"); 1081 break; 1082 } 1083 } 1084