1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCTargetDesc.h" 16 #include "MCTargetDesc/HexagonMCInstrInfo.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include <cassert> 31 #include <cstddef> 32 #include <cstdint> 33 #include <memory> 34 35 using namespace llvm; 36 using namespace Hexagon; 37 38 typedef MCDisassembler::DecodeStatus DecodeStatus; 39 40 namespace { 41 42 /// \brief Hexagon disassembler for all Hexagon platforms. 43 class HexagonDisassembler : public MCDisassembler { 44 public: 45 std::unique_ptr<MCInstrInfo const> const MCII; 46 std::unique_ptr<MCInst *> CurrentBundle; 47 48 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 49 MCInstrInfo const *MCII) 50 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} 51 52 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 53 ArrayRef<uint8_t> Bytes, uint64_t Address, 54 raw_ostream &VStream, raw_ostream &CStream, 55 bool &Complete) const; 56 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 57 ArrayRef<uint8_t> Bytes, uint64_t Address, 58 raw_ostream &VStream, 59 raw_ostream &CStream) const override; 60 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; 61 }; 62 63 namespace { 64 uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, 65 int64_t Value) { 66 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 67 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 68 if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 69 return Value; 70 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 71 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 72 int64_t Bits; 73 bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); 74 assert(Success); (void)Success; 75 uint32_t Upper26 = static_cast<uint32_t>(Bits); 76 uint32_t Operand = Upper26 | Lower6; 77 return Operand; 78 } 79 HexagonDisassembler const &disassembler(void const *Decoder) { 80 return *static_cast<HexagonDisassembler const *>(Decoder); 81 } 82 template <size_t T> 83 void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 84 HexagonDisassembler const &Disassembler = disassembler(Decoder); 85 int64_t FullValue = 86 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, 87 SignExtend64<T>(tmp)); 88 int64_t Extended = SignExtend64<32>(FullValue); 89 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 90 } 91 } 92 } // end anonymous namespace 93 94 // Forward declare these because the auto-generated code will reference them. 95 // Definitions are further down. 96 97 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 101 unsigned RegNo, 102 uint64_t Address, 103 const void *Decoder); 104 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t Address, 112 const void *Decoder); 113 static DecodeStatus 114 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 117 uint64_t Address, 118 const void *Decoder); 119 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 132 uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 138 uint64_t /*Address*/, const void *Decoder); 139 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 140 const void *Decoder); 141 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 142 const void *Decoder); 143 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 144 const void *Decoder); 145 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 146 const void *Decoder); 147 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 152 const void *Decoder); 153 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 156 const void *Decoder); 157 158 #include "HexagonDepDecoders.h" 159 #include "HexagonGenDisassemblerTables.inc" 160 161 static MCDisassembler *createHexagonDisassembler(const Target &T, 162 const MCSubtargetInfo &STI, 163 MCContext &Ctx) { 164 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 165 } 166 167 extern "C" void LLVMInitializeHexagonDisassembler() { 168 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 169 createHexagonDisassembler); 170 } 171 172 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 173 ArrayRef<uint8_t> Bytes, 174 uint64_t Address, 175 raw_ostream &os, 176 raw_ostream &cs) const { 177 DecodeStatus Result = DecodeStatus::Success; 178 bool Complete = false; 179 Size = 0; 180 181 *CurrentBundle = &MI; 182 MI = HexagonMCInstrInfo::createBundle(); 183 while (Result == Success && !Complete) { 184 if (Bytes.size() < HEXAGON_INSTR_SIZE) 185 return MCDisassembler::Fail; 186 MCInst *Inst = new (getContext()) MCInst; 187 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 188 MI.addOperand(MCOperand::createInst(Inst)); 189 Size += HEXAGON_INSTR_SIZE; 190 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 191 } 192 if (Result == MCDisassembler::Fail) 193 return Result; 194 if (Size > HEXAGON_MAX_PACKET_SIZE) 195 return MCDisassembler::Fail; 196 HexagonMCChecker Checker(*MCII, STI, MI, MI, *getContext().getRegisterInfo()); 197 if (!Checker.check()) 198 return MCDisassembler::Fail; 199 return MCDisassembler::Success; 200 } 201 202 namespace { 203 void adjustDuplex(MCInst &MI, MCContext &Context) { 204 switch (MI.getOpcode()) { 205 case Hexagon::SA1_setin1: 206 MI.insert(MI.begin() + 1, 207 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 208 break; 209 case Hexagon::SA1_dec: 210 MI.insert(MI.begin() + 2, 211 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 212 break; 213 default: 214 break; 215 } 216 } 217 } 218 219 DecodeStatus HexagonDisassembler::getSingleInstruction( 220 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 221 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 222 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 223 224 uint32_t Instruction = support::endian::read32le(Bytes.data()); 225 226 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 227 if ((Instruction & HexagonII::INST_PARSE_MASK) == 228 HexagonII::INST_PARSE_LOOP_END) { 229 if (BundleSize == 0) 230 HexagonMCInstrInfo::setInnerLoop(MCB); 231 else if (BundleSize == 1) 232 HexagonMCInstrInfo::setOuterLoop(MCB); 233 else 234 return DecodeStatus::Fail; 235 } 236 237 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 238 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 239 240 DecodeStatus Result = DecodeStatus::Fail; 241 if ((Instruction & HexagonII::INST_PARSE_MASK) == 242 HexagonII::INST_PARSE_DUPLEX) { 243 unsigned duplexIClass; 244 uint8_t const *DecodeLow, *DecodeHigh; 245 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 246 switch (duplexIClass) { 247 default: 248 return MCDisassembler::Fail; 249 case 0: 250 DecodeLow = DecoderTableSUBINSN_L132; 251 DecodeHigh = DecoderTableSUBINSN_L132; 252 break; 253 case 1: 254 DecodeLow = DecoderTableSUBINSN_L232; 255 DecodeHigh = DecoderTableSUBINSN_L132; 256 break; 257 case 2: 258 DecodeLow = DecoderTableSUBINSN_L232; 259 DecodeHigh = DecoderTableSUBINSN_L232; 260 break; 261 case 3: 262 DecodeLow = DecoderTableSUBINSN_A32; 263 DecodeHigh = DecoderTableSUBINSN_A32; 264 break; 265 case 4: 266 DecodeLow = DecoderTableSUBINSN_L132; 267 DecodeHigh = DecoderTableSUBINSN_A32; 268 break; 269 case 5: 270 DecodeLow = DecoderTableSUBINSN_L232; 271 DecodeHigh = DecoderTableSUBINSN_A32; 272 break; 273 case 6: 274 DecodeLow = DecoderTableSUBINSN_S132; 275 DecodeHigh = DecoderTableSUBINSN_A32; 276 break; 277 case 7: 278 DecodeLow = DecoderTableSUBINSN_S232; 279 DecodeHigh = DecoderTableSUBINSN_A32; 280 break; 281 case 8: 282 DecodeLow = DecoderTableSUBINSN_S132; 283 DecodeHigh = DecoderTableSUBINSN_L132; 284 break; 285 case 9: 286 DecodeLow = DecoderTableSUBINSN_S132; 287 DecodeHigh = DecoderTableSUBINSN_L232; 288 break; 289 case 10: 290 DecodeLow = DecoderTableSUBINSN_S132; 291 DecodeHigh = DecoderTableSUBINSN_S132; 292 break; 293 case 11: 294 DecodeLow = DecoderTableSUBINSN_S232; 295 DecodeHigh = DecoderTableSUBINSN_S132; 296 break; 297 case 12: 298 DecodeLow = DecoderTableSUBINSN_S232; 299 DecodeHigh = DecoderTableSUBINSN_L132; 300 break; 301 case 13: 302 DecodeLow = DecoderTableSUBINSN_S232; 303 DecodeHigh = DecoderTableSUBINSN_L232; 304 break; 305 case 14: 306 DecodeLow = DecoderTableSUBINSN_S232; 307 DecodeHigh = DecoderTableSUBINSN_S232; 308 break; 309 } 310 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); 311 MCInst *MILow = new (getContext()) MCInst; 312 MCInst *MIHigh = new (getContext()) MCInst; 313 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, 314 this, STI); 315 if (Result != DecodeStatus::Success) 316 return DecodeStatus::Fail; 317 adjustDuplex(*MILow, getContext()); 318 Result = decodeInstruction( 319 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); 320 if (Result != DecodeStatus::Success) 321 return DecodeStatus::Fail; 322 adjustDuplex(*MIHigh, getContext()); 323 MCOperand OPLow = MCOperand::createInst(MILow); 324 MCOperand OPHigh = MCOperand::createInst(MIHigh); 325 MI.addOperand(OPLow); 326 MI.addOperand(OPHigh); 327 Complete = true; 328 } else { 329 if ((Instruction & HexagonII::INST_PARSE_MASK) == 330 HexagonII::INST_PARSE_PACKET_END) 331 Complete = true; 332 333 if (Extender != nullptr) 334 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, 335 Address, this, STI); 336 337 if (Result != MCDisassembler::Success) 338 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, 339 STI); 340 341 if (Result != MCDisassembler::Success && 342 STI.getFeatureBits()[Hexagon::ExtensionHVX]) 343 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, 344 Address, this, STI); 345 346 } 347 348 switch (MI.getOpcode()) { 349 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 350 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 351 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 352 case Hexagon::J4_cmpeqn1_fp0_jump_t: 353 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 354 case Hexagon::J4_cmpeqn1_fp1_jump_t: 355 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 356 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 357 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 358 case Hexagon::J4_cmpeqn1_tp0_jump_t: 359 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 360 case Hexagon::J4_cmpeqn1_tp1_jump_t: 361 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 362 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 363 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 364 case Hexagon::J4_cmpgtn1_fp0_jump_t: 365 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 366 case Hexagon::J4_cmpgtn1_fp1_jump_t: 367 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 368 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 369 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 370 case Hexagon::J4_cmpgtn1_tp0_jump_t: 371 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 372 case Hexagon::J4_cmpgtn1_tp1_jump_t: 373 MI.insert(MI.begin() + 1, 374 MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 375 break; 376 default: 377 break; 378 } 379 380 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 381 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 382 MCOperand &MCO = MI.getOperand(OpIndex); 383 assert(MCO.isReg() && "New value consumers must be registers"); 384 unsigned Register = 385 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 386 if ((Register & 0x6) == 0) 387 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 388 return MCDisassembler::Fail; 389 unsigned Lookback = (Register & 0x6) >> 1; 390 unsigned Offset = 1; 391 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 392 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 393 auto i = Instructions.end() - 1; 394 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 395 if (i == n) 396 // Couldn't find producer 397 return MCDisassembler::Fail; 398 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) 399 // Skip scalars when calculating distances for vectors 400 ++Lookback; 401 if (HexagonMCInstrInfo::isImmext(*i->getInst())) 402 ++Lookback; 403 if (Offset == Lookback) 404 break; 405 } 406 auto const &Inst = *i->getInst(); 407 bool SubregBit = (Register & 0x1) != 0; 408 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 409 // If subreg bit is set we're selecting the second produced newvalue 410 unsigned Producer = 411 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 412 assert(Producer != Hexagon::NoRegister); 413 MCO.setReg(Producer); 414 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 415 unsigned Producer = 416 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 417 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 418 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 419 else if (SubregBit) 420 // Hexagon PRM 10.11 New-value operands 421 // Nt[0] is reserved and should always be encoded as zero. 422 return MCDisassembler::Fail; 423 assert(Producer != Hexagon::NoRegister); 424 MCO.setReg(Producer); 425 } else 426 return MCDisassembler::Fail; 427 } 428 429 if (Extender != nullptr) { 430 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) 431 ? *MI.getOperand(1).getInst() 432 : MI; 433 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 434 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 435 return MCDisassembler::Fail; 436 } 437 return Result; 438 } 439 440 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 441 ArrayRef<MCPhysReg> Table) { 442 if (RegNo < Table.size()) { 443 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 444 return MCDisassembler::Success; 445 } 446 447 return MCDisassembler::Fail; 448 } 449 450 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 451 uint64_t Address, 452 const void *Decoder) { 453 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 454 } 455 456 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 457 uint64_t Address, 458 const void *Decoder) { 459 static const MCPhysReg IntRegDecoderTable[] = { 460 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 461 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 462 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 463 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 464 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 465 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 466 Hexagon::R30, Hexagon::R31}; 467 468 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 469 } 470 471 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 472 unsigned RegNo, 473 uint64_t Address, 474 const void *Decoder) { 475 static const MCPhysReg GeneralSubRegDecoderTable[] = { 476 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 477 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, 478 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 479 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 480 }; 481 482 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); 483 } 484 485 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 486 uint64_t /*Address*/, 487 const void *Decoder) { 488 static const MCPhysReg VecRegDecoderTable[] = { 489 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 490 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 491 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 492 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 493 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 494 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 495 Hexagon::V30, Hexagon::V31}; 496 497 return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable); 498 } 499 500 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 501 uint64_t /*Address*/, 502 const void *Decoder) { 503 static const MCPhysReg DoubleRegDecoderTable[] = { 504 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 505 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 506 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 507 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 508 509 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 510 } 511 512 static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( 513 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { 514 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { 515 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 516 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; 517 518 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); 519 } 520 521 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 522 uint64_t /*Address*/, 523 const void *Decoder) { 524 static const MCPhysReg VecDblRegDecoderTable[] = { 525 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 526 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 527 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 528 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 529 530 return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable)); 531 } 532 533 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 534 uint64_t /*Address*/, 535 const void *Decoder) { 536 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 537 Hexagon::P2, Hexagon::P3}; 538 539 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 540 } 541 542 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 543 uint64_t /*Address*/, 544 const void *Decoder) { 545 static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 546 Hexagon::Q2, Hexagon::Q3}; 547 548 return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable); 549 } 550 551 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 552 uint64_t /*Address*/, 553 const void *Decoder) { 554 using namespace Hexagon; 555 static const MCPhysReg CtrlRegDecoderTable[] = { 556 /* 0 */ SA0, LC0, SA1, LC1, 557 /* 4 */ P3_0, C5, C6, C7, 558 /* 8 */ USR, PC, UGP, GP, 559 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, 560 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, 561 /* 20 */ 0, 0, 0, 0, 562 /* 24 */ 0, 0, 0, 0, 563 /* 28 */ 0, 0, UTIMERLO, UTIMERHI 564 }; 565 566 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 567 return MCDisassembler::Fail; 568 569 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 570 if (CtrlRegDecoderTable[RegNo] == NoRegister) 571 return MCDisassembler::Fail; 572 573 unsigned Register = CtrlRegDecoderTable[RegNo]; 574 Inst.addOperand(MCOperand::createReg(Register)); 575 return MCDisassembler::Success; 576 } 577 578 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 579 uint64_t /*Address*/, 580 const void *Decoder) { 581 using namespace Hexagon; 582 static const MCPhysReg CtrlReg64DecoderTable[] = { 583 /* 0 */ C1_0, 0, C3_2, 0, 584 /* 4 */ C5_4, 0, C7_6, 0, 585 /* 8 */ C9_8, 0, C11_10, 0, 586 /* 12 */ CS, 0, UPCYCLE, 0, 587 /* 16 */ C17_16, 0, PKTCOUNT, 0, 588 /* 20 */ 0, 0, 0, 0, 589 /* 24 */ 0, 0, 0, 0, 590 /* 28 */ 0, 0, UTIMER, 0 591 }; 592 593 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 594 return MCDisassembler::Fail; 595 596 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 597 if (CtrlReg64DecoderTable[RegNo] == NoRegister) 598 return MCDisassembler::Fail; 599 600 unsigned Register = CtrlReg64DecoderTable[RegNo]; 601 Inst.addOperand(MCOperand::createReg(Register)); 602 return MCDisassembler::Success; 603 } 604 605 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 606 uint64_t /*Address*/, 607 const void *Decoder) { 608 unsigned Register = 0; 609 switch (RegNo) { 610 case 0: 611 Register = Hexagon::M0; 612 break; 613 case 1: 614 Register = Hexagon::M1; 615 break; 616 default: 617 return MCDisassembler::Fail; 618 } 619 Inst.addOperand(MCOperand::createReg(Register)); 620 return MCDisassembler::Success; 621 } 622 623 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 624 uint64_t /*Address*/, 625 const void *Decoder) { 626 HexagonDisassembler const &Disassembler = disassembler(Decoder); 627 int64_t FullValue = 628 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, tmp); 629 assert(FullValue >= 0 && "Negative in unsigned decoder"); 630 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 631 return MCDisassembler::Success; 632 } 633 634 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, 635 uint64_t /*Address*/, const void *Decoder) { 636 signedDecoder<10>(MI, tmp, Decoder); 637 return MCDisassembler::Success; 638 } 639 640 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, 641 uint64_t /*Address*/, const void *Decoder) { 642 signedDecoder<19>(MI, tmp, Decoder); 643 return MCDisassembler::Success; 644 } 645 646 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 647 uint64_t /*Address*/, const void *Decoder) { 648 HexagonDisassembler const &Disassembler = disassembler(Decoder); 649 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 650 tmp = SignExtend64(tmp, Bits); 651 signedDecoder<32>(MI, tmp, Decoder); 652 return MCDisassembler::Success; 653 } 654 655 // custom decoder for various jump/call immediates 656 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 657 const void *Decoder) { 658 HexagonDisassembler const &Disassembler = disassembler(Decoder); 659 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 660 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 661 if (Bits == 0) 662 Bits = 15; 663 uint32_t FullValue = 664 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, 665 SignExtend64(tmp, Bits)); 666 int64_t Extended = SignExtend64<32>(FullValue) + Address; 667 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) 668 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 669 return MCDisassembler::Success; 670 } 671 672 673