1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "MCTargetDesc/HexagonBaseInfo.h" 13 #include "MCTargetDesc/HexagonMCChecker.h" 14 #include "MCTargetDesc/HexagonMCInstrInfo.h" 15 #include "MCTargetDesc/HexagonMCTargetDesc.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/Endian.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/TargetRegistry.h" 29 #include "llvm/Support/raw_ostream.h" 30 #include <cassert> 31 #include <cstddef> 32 #include <cstdint> 33 #include <memory> 34 35 using namespace llvm; 36 using namespace Hexagon; 37 38 using DecodeStatus = MCDisassembler::DecodeStatus; 39 40 namespace { 41 42 /// Hexagon disassembler for all Hexagon platforms. 43 class HexagonDisassembler : public MCDisassembler { 44 public: 45 std::unique_ptr<MCInstrInfo const> const MCII; 46 std::unique_ptr<MCInst *> CurrentBundle; 47 mutable MCInst const *CurrentExtender; 48 49 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 50 MCInstrInfo const *MCII) 51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), 52 CurrentExtender(nullptr) {} 53 54 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 55 ArrayRef<uint8_t> Bytes, uint64_t Address, 56 raw_ostream &VStream, raw_ostream &CStream, 57 bool &Complete) const; 58 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 59 ArrayRef<uint8_t> Bytes, uint64_t Address, 60 raw_ostream &VStream, 61 raw_ostream &CStream) const override; 62 void remapInstruction(MCInst &Instr) const; 63 }; 64 65 static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI, 66 int64_t Value) { 67 MCInstrInfo MCII = *Disassembler.MCII; 68 if (!Disassembler.CurrentExtender || 69 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 70 return Value; 71 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 72 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 73 int64_t Bits; 74 bool Success = 75 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute( 76 Bits); 77 assert(Success); 78 (void)Success; 79 uint64_t Upper26 = static_cast<uint64_t>(Bits); 80 uint64_t Operand = Upper26 | Lower6; 81 return Operand; 82 } 83 static HexagonDisassembler const &disassembler(void const *Decoder) { 84 return *static_cast<HexagonDisassembler const *>(Decoder); 85 } 86 template <size_t T> 87 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 88 HexagonDisassembler const &Disassembler = disassembler(Decoder); 89 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp)); 90 int64_t Extended = SignExtend64<32>(FullValue); 91 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 92 } 93 } 94 95 // Forward declare these because the auto-generated code will reference them. 96 // Definitions are further down. 97 98 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 99 uint64_t Address, 100 const void *Decoder); 101 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 102 unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, 107 const void *Decoder); 108 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const void *Decoder); 114 static DecodeStatus 115 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 118 uint64_t Address, 119 const void *Decoder); 120 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 121 uint64_t Address, 122 const void *Decoder); 123 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 127 uint64_t Address, 128 const void *Decoder); 129 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, 130 uint64_t Address, 131 const void *Decoder); 132 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 133 uint64_t Address, 134 const void *Decoder); 135 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 136 uint64_t Address, 137 const void *Decoder); 138 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 145 uint64_t /*Address*/, const void *Decoder); 146 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 147 const void *Decoder); 148 #include "HexagonDepDecoders.h" 149 #include "HexagonGenDisassemblerTables.inc" 150 151 static MCDisassembler *createHexagonDisassembler(const Target &T, 152 const MCSubtargetInfo &STI, 153 MCContext &Ctx) { 154 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 155 } 156 157 extern "C" void LLVMInitializeHexagonDisassembler() { 158 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 159 createHexagonDisassembler); 160 } 161 162 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 163 ArrayRef<uint8_t> Bytes, 164 uint64_t Address, 165 raw_ostream &os, 166 raw_ostream &cs) const { 167 DecodeStatus Result = DecodeStatus::Success; 168 bool Complete = false; 169 Size = 0; 170 171 *CurrentBundle = &MI; 172 MI.setOpcode(Hexagon::BUNDLE); 173 MI.addOperand(MCOperand::createImm(0)); 174 while (Result == Success && !Complete) { 175 if (Bytes.size() < HEXAGON_INSTR_SIZE) 176 return MCDisassembler::Fail; 177 MCInst *Inst = new (getContext()) MCInst; 178 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 179 MI.addOperand(MCOperand::createInst(Inst)); 180 Size += HEXAGON_INSTR_SIZE; 181 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 182 } 183 if (Result == MCDisassembler::Fail) 184 return Result; 185 if (Size > HEXAGON_MAX_PACKET_SIZE) 186 return MCDisassembler::Fail; 187 HexagonMCChecker Checker(getContext(), *MCII, STI, MI, 188 *getContext().getRegisterInfo(), false); 189 if (!Checker.check()) 190 return MCDisassembler::Fail; 191 remapInstruction(MI); 192 return MCDisassembler::Success; 193 } 194 195 void HexagonDisassembler::remapInstruction(MCInst &Instr) const { 196 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) { 197 auto &MI = const_cast<MCInst &>(*I.getInst()); 198 switch (MI.getOpcode()) { 199 case Hexagon::S2_allocframe: 200 if (MI.getOperand(0).getReg() == Hexagon::R29) { 201 MI.setOpcode(Hexagon::S6_allocframe_to_raw); 202 MI.erase(MI.begin () + 1); 203 MI.erase(MI.begin ()); 204 } 205 break; 206 case Hexagon::L2_deallocframe: 207 if (MI.getOperand(0).getReg() == Hexagon::D15 && 208 MI.getOperand(1).getReg() == Hexagon::R30) { 209 MI.setOpcode(L6_deallocframe_map_to_raw); 210 MI.erase(MI.begin () + 1); 211 MI.erase(MI.begin ()); 212 } 213 break; 214 case Hexagon::L4_return: 215 if (MI.getOperand(0).getReg() == Hexagon::D15 && 216 MI.getOperand(1).getReg() == Hexagon::R30) { 217 MI.setOpcode(L6_return_map_to_raw); 218 MI.erase(MI.begin () + 1); 219 MI.erase(MI.begin ()); 220 } 221 break; 222 case Hexagon::L4_return_t: 223 if (MI.getOperand(0).getReg() == Hexagon::D15 && 224 MI.getOperand(2).getReg() == Hexagon::R30) { 225 MI.setOpcode(L4_return_map_to_raw_t); 226 MI.erase(MI.begin () + 2); 227 MI.erase(MI.begin ()); 228 } 229 break; 230 case Hexagon::L4_return_f: 231 if (MI.getOperand(0).getReg() == Hexagon::D15 && 232 MI.getOperand(2).getReg() == Hexagon::R30) { 233 MI.setOpcode(L4_return_map_to_raw_f); 234 MI.erase(MI.begin () + 2); 235 MI.erase(MI.begin ()); 236 } 237 break; 238 case Hexagon::L4_return_tnew_pt: 239 if (MI.getOperand(0).getReg() == Hexagon::D15 && 240 MI.getOperand(2).getReg() == Hexagon::R30) { 241 MI.setOpcode(L4_return_map_to_raw_tnew_pt); 242 MI.erase(MI.begin () + 2); 243 MI.erase(MI.begin ()); 244 } 245 break; 246 case Hexagon::L4_return_fnew_pt: 247 if (MI.getOperand(0).getReg() == Hexagon::D15 && 248 MI.getOperand(2).getReg() == Hexagon::R30) { 249 MI.setOpcode(L4_return_map_to_raw_fnew_pt); 250 MI.erase(MI.begin () + 2); 251 MI.erase(MI.begin ()); 252 } 253 break; 254 case Hexagon::L4_return_tnew_pnt: 255 if (MI.getOperand(0).getReg() == Hexagon::D15 && 256 MI.getOperand(2).getReg() == Hexagon::R30) { 257 MI.setOpcode(L4_return_map_to_raw_tnew_pnt); 258 MI.erase(MI.begin () + 2); 259 MI.erase(MI.begin ()); 260 } 261 break; 262 case Hexagon::L4_return_fnew_pnt: 263 if (MI.getOperand(0).getReg() == Hexagon::D15 && 264 MI.getOperand(2).getReg() == Hexagon::R30) { 265 MI.setOpcode(L4_return_map_to_raw_fnew_pnt); 266 MI.erase(MI.begin () + 2); 267 MI.erase(MI.begin ()); 268 } 269 break; 270 } 271 } 272 } 273 274 static void adjustDuplex(MCInst &MI, MCContext &Context) { 275 switch (MI.getOpcode()) { 276 case Hexagon::SA1_setin1: 277 MI.insert(MI.begin() + 1, 278 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 279 break; 280 case Hexagon::SA1_dec: 281 MI.insert(MI.begin() + 2, 282 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 283 break; 284 default: 285 break; 286 } 287 } 288 289 DecodeStatus HexagonDisassembler::getSingleInstruction( 290 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 291 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 292 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 293 294 uint32_t Instruction = support::endian::read32le(Bytes.data()); 295 296 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 297 if ((Instruction & HexagonII::INST_PARSE_MASK) == 298 HexagonII::INST_PARSE_LOOP_END) { 299 if (BundleSize == 0) 300 HexagonMCInstrInfo::setInnerLoop(MCB); 301 else if (BundleSize == 1) 302 HexagonMCInstrInfo::setOuterLoop(MCB); 303 else 304 return DecodeStatus::Fail; 305 } 306 307 CurrentExtender = HexagonMCInstrInfo::extenderForIndex( 308 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 309 310 DecodeStatus Result = DecodeStatus::Fail; 311 if ((Instruction & HexagonII::INST_PARSE_MASK) == 312 HexagonII::INST_PARSE_DUPLEX) { 313 unsigned duplexIClass; 314 uint8_t const *DecodeLow, *DecodeHigh; 315 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 316 switch (duplexIClass) { 317 default: 318 return MCDisassembler::Fail; 319 case 0: 320 DecodeLow = DecoderTableSUBINSN_L132; 321 DecodeHigh = DecoderTableSUBINSN_L132; 322 break; 323 case 1: 324 DecodeLow = DecoderTableSUBINSN_L232; 325 DecodeHigh = DecoderTableSUBINSN_L132; 326 break; 327 case 2: 328 DecodeLow = DecoderTableSUBINSN_L232; 329 DecodeHigh = DecoderTableSUBINSN_L232; 330 break; 331 case 3: 332 DecodeLow = DecoderTableSUBINSN_A32; 333 DecodeHigh = DecoderTableSUBINSN_A32; 334 break; 335 case 4: 336 DecodeLow = DecoderTableSUBINSN_L132; 337 DecodeHigh = DecoderTableSUBINSN_A32; 338 break; 339 case 5: 340 DecodeLow = DecoderTableSUBINSN_L232; 341 DecodeHigh = DecoderTableSUBINSN_A32; 342 break; 343 case 6: 344 DecodeLow = DecoderTableSUBINSN_S132; 345 DecodeHigh = DecoderTableSUBINSN_A32; 346 break; 347 case 7: 348 DecodeLow = DecoderTableSUBINSN_S232; 349 DecodeHigh = DecoderTableSUBINSN_A32; 350 break; 351 case 8: 352 DecodeLow = DecoderTableSUBINSN_S132; 353 DecodeHigh = DecoderTableSUBINSN_L132; 354 break; 355 case 9: 356 DecodeLow = DecoderTableSUBINSN_S132; 357 DecodeHigh = DecoderTableSUBINSN_L232; 358 break; 359 case 10: 360 DecodeLow = DecoderTableSUBINSN_S132; 361 DecodeHigh = DecoderTableSUBINSN_S132; 362 break; 363 case 11: 364 DecodeLow = DecoderTableSUBINSN_S232; 365 DecodeHigh = DecoderTableSUBINSN_S132; 366 break; 367 case 12: 368 DecodeLow = DecoderTableSUBINSN_S232; 369 DecodeHigh = DecoderTableSUBINSN_L132; 370 break; 371 case 13: 372 DecodeLow = DecoderTableSUBINSN_S232; 373 DecodeHigh = DecoderTableSUBINSN_L232; 374 break; 375 case 14: 376 DecodeLow = DecoderTableSUBINSN_S232; 377 DecodeHigh = DecoderTableSUBINSN_S232; 378 break; 379 } 380 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); 381 MCInst *MILow = new (getContext()) MCInst; 382 MCInst *MIHigh = new (getContext()) MCInst; 383 auto TmpExtender = CurrentExtender; 384 CurrentExtender = 385 nullptr; // constant extenders in duplex must always be in slot 1 386 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, 387 this, STI); 388 CurrentExtender = TmpExtender; 389 if (Result != DecodeStatus::Success) 390 return DecodeStatus::Fail; 391 adjustDuplex(*MILow, getContext()); 392 Result = decodeInstruction( 393 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); 394 if (Result != DecodeStatus::Success) 395 return DecodeStatus::Fail; 396 adjustDuplex(*MIHigh, getContext()); 397 MCOperand OPLow = MCOperand::createInst(MILow); 398 MCOperand OPHigh = MCOperand::createInst(MIHigh); 399 MI.addOperand(OPLow); 400 MI.addOperand(OPHigh); 401 Complete = true; 402 } else { 403 if ((Instruction & HexagonII::INST_PARSE_MASK) == 404 HexagonII::INST_PARSE_PACKET_END) 405 Complete = true; 406 407 if (CurrentExtender != nullptr) 408 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, 409 Address, this, STI); 410 411 if (Result != MCDisassembler::Success) 412 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, 413 STI); 414 415 if (Result != MCDisassembler::Success && 416 STI.getFeatureBits()[Hexagon::ExtensionHVX]) 417 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, 418 Address, this, STI); 419 420 } 421 422 switch (MI.getOpcode()) { 423 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 424 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 425 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 426 case Hexagon::J4_cmpeqn1_fp0_jump_t: 427 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 428 case Hexagon::J4_cmpeqn1_fp1_jump_t: 429 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 430 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 431 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 432 case Hexagon::J4_cmpeqn1_tp0_jump_t: 433 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 434 case Hexagon::J4_cmpeqn1_tp1_jump_t: 435 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 436 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 437 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 438 case Hexagon::J4_cmpgtn1_fp0_jump_t: 439 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 440 case Hexagon::J4_cmpgtn1_fp1_jump_t: 441 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 442 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 443 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 444 case Hexagon::J4_cmpgtn1_tp0_jump_t: 445 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 446 case Hexagon::J4_cmpgtn1_tp1_jump_t: 447 MI.insert(MI.begin() + 1, 448 MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 449 break; 450 default: 451 break; 452 } 453 454 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 455 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 456 MCOperand &MCO = MI.getOperand(OpIndex); 457 assert(MCO.isReg() && "New value consumers must be registers"); 458 unsigned Register = 459 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 460 if ((Register & 0x6) == 0) 461 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 462 return MCDisassembler::Fail; 463 unsigned Lookback = (Register & 0x6) >> 1; 464 unsigned Offset = 1; 465 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 466 bool PrevVector = false; 467 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 468 auto i = Instructions.end() - 1; 469 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 470 if (i == n) 471 // Couldn't find producer 472 return MCDisassembler::Fail; 473 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst()); 474 if (Vector && !CurrentVector) 475 // Skip scalars when calculating distances for vectors 476 ++Lookback; 477 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector)) 478 ++Lookback; 479 PrevVector = CurrentVector; 480 if (Offset == Lookback) 481 break; 482 } 483 auto const &Inst = *i->getInst(); 484 bool SubregBit = (Register & 0x1) != 0; 485 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 486 // If subreg bit is set we're selecting the second produced newvalue 487 unsigned Producer = SubregBit ? 488 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() : 489 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 490 assert(Producer != Hexagon::NoRegister); 491 MCO.setReg(Producer); 492 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 493 unsigned Producer = 494 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 495 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 496 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 497 else if (SubregBit) 498 // Hexagon PRM 10.11 New-value operands 499 // Nt[0] is reserved and should always be encoded as zero. 500 return MCDisassembler::Fail; 501 assert(Producer != Hexagon::NoRegister); 502 MCO.setReg(Producer); 503 } else 504 return MCDisassembler::Fail; 505 } 506 507 if (CurrentExtender != nullptr) { 508 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) 509 ? *MI.getOperand(1).getInst() 510 : MI; 511 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 512 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 513 return MCDisassembler::Fail; 514 } 515 return Result; 516 } 517 518 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 519 ArrayRef<MCPhysReg> Table) { 520 if (RegNo < Table.size()) { 521 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 522 return MCDisassembler::Success; 523 } 524 525 return MCDisassembler::Fail; 526 } 527 528 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 529 uint64_t Address, 530 const void *Decoder) { 531 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 532 } 533 534 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 535 uint64_t Address, 536 const void *Decoder) { 537 static const MCPhysReg IntRegDecoderTable[] = { 538 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 539 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 540 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 541 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 542 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 543 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 544 Hexagon::R30, Hexagon::R31}; 545 546 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 547 } 548 549 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 550 unsigned RegNo, 551 uint64_t Address, 552 const void *Decoder) { 553 static const MCPhysReg GeneralSubRegDecoderTable[] = { 554 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 555 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, 556 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 557 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 558 }; 559 560 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); 561 } 562 563 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 564 uint64_t /*Address*/, 565 const void *Decoder) { 566 static const MCPhysReg HvxVRDecoderTable[] = { 567 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 568 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 569 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 570 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 571 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 572 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 573 Hexagon::V30, Hexagon::V31}; 574 575 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); 576 } 577 578 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 579 uint64_t /*Address*/, 580 const void *Decoder) { 581 static const MCPhysReg DoubleRegDecoderTable[] = { 582 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 583 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 584 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 585 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 586 587 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 588 } 589 590 static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( 591 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { 592 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { 593 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 594 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; 595 596 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); 597 } 598 599 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 600 uint64_t /*Address*/, 601 const void *Decoder) { 602 static const MCPhysReg HvxWRDecoderTable[] = { 603 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 604 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 605 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 606 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 607 608 return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable)); 609 } 610 611 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 612 uint64_t /*Address*/, 613 const void *Decoder) { 614 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 615 Hexagon::P2, Hexagon::P3}; 616 617 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 618 } 619 620 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 621 uint64_t /*Address*/, 622 const void *Decoder) { 623 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 624 Hexagon::Q2, Hexagon::Q3}; 625 626 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); 627 } 628 629 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 630 uint64_t /*Address*/, 631 const void *Decoder) { 632 using namespace Hexagon; 633 634 static const MCPhysReg CtrlRegDecoderTable[] = { 635 /* 0 */ SA0, LC0, SA1, LC1, 636 /* 4 */ P3_0, C5, M0, M1, 637 /* 8 */ USR, PC, UGP, GP, 638 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, 639 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, 640 /* 20 */ 0, 0, 0, 0, 641 /* 24 */ 0, 0, 0, 0, 642 /* 28 */ 0, 0, UTIMERLO, UTIMERHI 643 }; 644 645 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 646 return MCDisassembler::Fail; 647 648 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 649 if (CtrlRegDecoderTable[RegNo] == NoRegister) 650 return MCDisassembler::Fail; 651 652 unsigned Register = CtrlRegDecoderTable[RegNo]; 653 Inst.addOperand(MCOperand::createReg(Register)); 654 return MCDisassembler::Success; 655 } 656 657 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 658 uint64_t /*Address*/, 659 const void *Decoder) { 660 using namespace Hexagon; 661 662 static const MCPhysReg CtrlReg64DecoderTable[] = { 663 /* 0 */ C1_0, 0, C3_2, 0, 664 /* 4 */ C5_4, 0, C7_6, 0, 665 /* 8 */ C9_8, 0, C11_10, 0, 666 /* 12 */ CS, 0, UPCYCLE, 0, 667 /* 16 */ C17_16, 0, PKTCOUNT, 0, 668 /* 20 */ 0, 0, 0, 0, 669 /* 24 */ 0, 0, 0, 0, 670 /* 28 */ 0, 0, UTIMER, 0 671 }; 672 673 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 674 return MCDisassembler::Fail; 675 676 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 677 if (CtrlReg64DecoderTable[RegNo] == NoRegister) 678 return MCDisassembler::Fail; 679 680 unsigned Register = CtrlReg64DecoderTable[RegNo]; 681 Inst.addOperand(MCOperand::createReg(Register)); 682 return MCDisassembler::Success; 683 } 684 685 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 686 uint64_t /*Address*/, 687 const void *Decoder) { 688 unsigned Register = 0; 689 switch (RegNo) { 690 case 0: 691 Register = Hexagon::M0; 692 break; 693 case 1: 694 Register = Hexagon::M1; 695 break; 696 default: 697 return MCDisassembler::Fail; 698 } 699 Inst.addOperand(MCOperand::createReg(Register)); 700 return MCDisassembler::Success; 701 } 702 703 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 704 uint64_t /*Address*/, 705 const void *Decoder) { 706 HexagonDisassembler const &Disassembler = disassembler(Decoder); 707 int64_t FullValue = fullValue(Disassembler, MI, tmp); 708 assert(FullValue >= 0 && "Negative in unsigned decoder"); 709 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 710 return MCDisassembler::Success; 711 } 712 713 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 714 uint64_t /*Address*/, const void *Decoder) { 715 HexagonDisassembler const &Disassembler = disassembler(Decoder); 716 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 717 tmp = SignExtend64(tmp, Bits); 718 signedDecoder<32>(MI, tmp, Decoder); 719 return MCDisassembler::Success; 720 } 721 722 // custom decoder for various jump/call immediates 723 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 724 const void *Decoder) { 725 HexagonDisassembler const &Disassembler = disassembler(Decoder); 726 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 727 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 728 if (Bits == 0) 729 Bits = 15; 730 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits)); 731 uint32_t Extended = FullValue + Address; 732 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) 733 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 734 return MCDisassembler::Success; 735 } 736 737 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, 738 uint64_t /*Address*/, 739 const void *Decoder) { 740 using namespace Hexagon; 741 742 static const MCPhysReg GuestRegDecoderTable[] = { 743 /* 0 */ GELR, GSR, GOSP, G3, 744 /* 4 */ G4, G5, G6, G7, 745 /* 8 */ G8, G9, G10, G11, 746 /* 12 */ G12, G13, G14, G15, 747 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7, 748 /* 20 */ G20, G21, G22, G23, 749 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1, 750 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31 751 }; 752 753 if (RegNo >= array_lengthof(GuestRegDecoderTable)) 754 return MCDisassembler::Fail; 755 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister) 756 return MCDisassembler::Fail; 757 758 unsigned Register = GuestRegDecoderTable[RegNo]; 759 Inst.addOperand(MCOperand::createReg(Register)); 760 return MCDisassembler::Success; 761 } 762 763 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 764 uint64_t /*Address*/, 765 const void *Decoder) { 766 using namespace Hexagon; 767 768 static const MCPhysReg GuestReg64DecoderTable[] = { 769 /* 0 */ G1_0, 0, G3_2, 0, 770 /* 4 */ G5_4, 0, G7_6, 0, 771 /* 8 */ G9_8, 0, G11_10, 0, 772 /* 12 */ G13_12, 0, G15_14, 0, 773 /* 16 */ G17_16, 0, G19_18, 0, 774 /* 20 */ G21_20, 0, G23_22, 0, 775 /* 24 */ G25_24, 0, G27_26, 0, 776 /* 28 */ G29_28, 0, G31_30, 0 777 }; 778 779 if (RegNo >= array_lengthof(GuestReg64DecoderTable)) 780 return MCDisassembler::Fail; 781 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister) 782 return MCDisassembler::Fail; 783 784 unsigned Register = GuestReg64DecoderTable[RegNo]; 785 Inst.addOperand(MCOperand::createReg(Register)); 786 return MCDisassembler::Success; 787 } 788