1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCTargetDesc.h" 16 #include "MCTargetDesc/HexagonMCInstrInfo.h" 17 #include "MCTargetDesc/HexagonInstPrinter.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrDesc.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/LEB128.h" 30 #include "llvm/Support/MemoryObject.h" 31 #include "llvm/Support/raw_ostream.h" 32 #include "llvm/Support/TargetRegistry.h" 33 #include <vector> 34 35 using namespace llvm; 36 using namespace Hexagon; 37 38 typedef MCDisassembler::DecodeStatus DecodeStatus; 39 40 namespace { 41 /// \brief Hexagon disassembler for all Hexagon platforms. 42 class HexagonDisassembler : public MCDisassembler { 43 public: 44 std::unique_ptr<MCInstrInfo const> const MCII; 45 std::unique_ptr<MCInst *> CurrentBundle; 46 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 47 MCInstrInfo const *MCII) 48 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} 49 50 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 51 ArrayRef<uint8_t> Bytes, uint64_t Address, 52 raw_ostream &VStream, raw_ostream &CStream, 53 bool &Complete) const; 54 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 55 ArrayRef<uint8_t> Bytes, uint64_t Address, 56 raw_ostream &VStream, 57 raw_ostream &CStream) const override; 58 59 void adjustExtendedInstructions(MCInst &MCI, MCInst const &MCB) const; 60 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; 61 }; 62 } 63 64 // Forward declare these because the auto-generated code will reference them. 65 // Definitions are further down. 66 67 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 68 uint64_t Address, 69 const void *Decoder); 70 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 71 uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decoder); 94 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 98 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn); 99 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, 100 void const *Decoder); 101 102 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 103 raw_ostream &os); 104 105 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg); 106 107 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 108 uint64_t Address, const void *Decoder); 109 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 112 const void *Decoder); 113 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 116 const void *Decoder); 117 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 118 const void *Decoder); 119 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 122 const void *Decoder); 123 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 128 const void *Decoder); 129 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 134 const void *Decoder); 135 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 136 const void *Decoder); 137 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 138 const void *Decoder); 139 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 140 const void *Decoder); 141 142 #include "HexagonGenDisassemblerTables.inc" 143 144 static MCDisassembler *createHexagonDisassembler(const Target &T, 145 const MCSubtargetInfo &STI, 146 MCContext &Ctx) { 147 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 148 } 149 150 extern "C" void LLVMInitializeHexagonDisassembler() { 151 TargetRegistry::RegisterMCDisassembler(TheHexagonTarget, 152 createHexagonDisassembler); 153 } 154 155 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 156 ArrayRef<uint8_t> Bytes, 157 uint64_t Address, 158 raw_ostream &os, 159 raw_ostream &cs) const { 160 DecodeStatus Result = DecodeStatus::Success; 161 bool Complete = false; 162 Size = 0; 163 164 *CurrentBundle = &MI; 165 MI = HexagonMCInstrInfo::createBundle(); 166 while (Result == Success && Complete == false) { 167 if (Bytes.size() < HEXAGON_INSTR_SIZE) 168 return MCDisassembler::Fail; 169 MCInst *Inst = new (getContext()) MCInst; 170 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 171 MI.addOperand(MCOperand::createInst(Inst)); 172 Size += HEXAGON_INSTR_SIZE; 173 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 174 } 175 if(Result == MCDisassembler::Fail) 176 return Result; 177 HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo()); 178 if(!Checker.check()) 179 return MCDisassembler::Fail; 180 return MCDisassembler::Success; 181 } 182 183 namespace { 184 HexagonDisassembler const &disassembler(void const *Decoder) { 185 return *static_cast<HexagonDisassembler const *>(Decoder); 186 } 187 MCContext &contextFromDecoder(void const *Decoder) { 188 return disassembler(Decoder).getContext(); 189 } 190 } 191 192 DecodeStatus HexagonDisassembler::getSingleInstruction( 193 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 194 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 195 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 196 197 uint32_t Instruction = 198 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 199 200 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 201 if ((Instruction & HexagonII::INST_PARSE_MASK) == 202 HexagonII::INST_PARSE_LOOP_END) { 203 if (BundleSize == 0) 204 HexagonMCInstrInfo::setInnerLoop(MCB); 205 else if (BundleSize == 1) 206 HexagonMCInstrInfo::setOuterLoop(MCB); 207 else 208 return DecodeStatus::Fail; 209 } 210 211 DecodeStatus Result = DecodeStatus::Success; 212 if ((Instruction & HexagonII::INST_PARSE_MASK) == 213 HexagonII::INST_PARSE_DUPLEX) { 214 // Determine the instruction class of each instruction in the duplex. 215 unsigned duplexIClass, IClassLow, IClassHigh; 216 217 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 218 switch (duplexIClass) { 219 default: 220 return MCDisassembler::Fail; 221 case 0: 222 IClassLow = HexagonII::HSIG_L1; 223 IClassHigh = HexagonII::HSIG_L1; 224 break; 225 case 1: 226 IClassLow = HexagonII::HSIG_L2; 227 IClassHigh = HexagonII::HSIG_L1; 228 break; 229 case 2: 230 IClassLow = HexagonII::HSIG_L2; 231 IClassHigh = HexagonII::HSIG_L2; 232 break; 233 case 3: 234 IClassLow = HexagonII::HSIG_A; 235 IClassHigh = HexagonII::HSIG_A; 236 break; 237 case 4: 238 IClassLow = HexagonII::HSIG_L1; 239 IClassHigh = HexagonII::HSIG_A; 240 break; 241 case 5: 242 IClassLow = HexagonII::HSIG_L2; 243 IClassHigh = HexagonII::HSIG_A; 244 break; 245 case 6: 246 IClassLow = HexagonII::HSIG_S1; 247 IClassHigh = HexagonII::HSIG_A; 248 break; 249 case 7: 250 IClassLow = HexagonII::HSIG_S2; 251 IClassHigh = HexagonII::HSIG_A; 252 break; 253 case 8: 254 IClassLow = HexagonII::HSIG_S1; 255 IClassHigh = HexagonII::HSIG_L1; 256 break; 257 case 9: 258 IClassLow = HexagonII::HSIG_S1; 259 IClassHigh = HexagonII::HSIG_L2; 260 break; 261 case 10: 262 IClassLow = HexagonII::HSIG_S1; 263 IClassHigh = HexagonII::HSIG_S1; 264 break; 265 case 11: 266 IClassLow = HexagonII::HSIG_S2; 267 IClassHigh = HexagonII::HSIG_S1; 268 break; 269 case 12: 270 IClassLow = HexagonII::HSIG_S2; 271 IClassHigh = HexagonII::HSIG_L1; 272 break; 273 case 13: 274 IClassLow = HexagonII::HSIG_S2; 275 IClassHigh = HexagonII::HSIG_L2; 276 break; 277 case 14: 278 IClassLow = HexagonII::HSIG_S2; 279 IClassHigh = HexagonII::HSIG_S2; 280 break; 281 } 282 283 // Set the MCInst to be a duplex instruction. Which one doesn't matter. 284 MI.setOpcode(Hexagon::DuplexIClass0); 285 286 // Decode each instruction in the duplex. 287 // Create an MCInst for each instruction. 288 unsigned instLow = Instruction & 0x1fff; 289 unsigned instHigh = (Instruction >> 16) & 0x1fff; 290 unsigned opLow; 291 if (GetSubinstOpcode(IClassLow, instLow, opLow, os) != 292 MCDisassembler::Success) 293 return MCDisassembler::Fail; 294 unsigned opHigh; 295 if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) != 296 MCDisassembler::Success) 297 return MCDisassembler::Fail; 298 MCInst *MILow = new (getContext()) MCInst; 299 MILow->setOpcode(opLow); 300 MCInst *MIHigh = new (getContext()) MCInst; 301 MIHigh->setOpcode(opHigh); 302 addSubinstOperands(MILow, opLow, instLow); 303 addSubinstOperands(MIHigh, opHigh, instHigh); 304 // see ConvertToSubInst() in 305 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 306 307 // Add the duplex instruction MCInsts as operands to the passed in MCInst. 308 MCOperand OPLow = MCOperand::createInst(MILow); 309 MCOperand OPHigh = MCOperand::createInst(MIHigh); 310 MI.addOperand(OPLow); 311 MI.addOperand(OPHigh); 312 Complete = true; 313 } else { 314 if ((Instruction & HexagonII::INST_PARSE_MASK) == 315 HexagonII::INST_PARSE_PACKET_END) 316 Complete = true; 317 // Calling the auto-generated decoder function. 318 Result = 319 decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); 320 321 // If a, "standard" insn isn't found check special cases. 322 if (MCDisassembler::Success != Result || 323 MI.getOpcode() == Hexagon::A4_ext) { 324 Result = decodeImmext(MI, Instruction, this); 325 if (MCDisassembler::Success != Result) { 326 Result = decodeSpecial(MI, Instruction); 327 } 328 } else { 329 // If the instruction is a compound instruction, register values will 330 // follow the duplex model, so the register values in the MCInst are 331 // incorrect. If the instruction is a compound, loop through the 332 // operands and change registers appropriately. 333 if (llvm::HexagonMCInstrInfo::getType(*MCII, MI) == 334 HexagonII::TypeCOMPOUND) { 335 for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) { 336 if (i->isReg()) { 337 unsigned reg = i->getReg() - Hexagon::R0; 338 i->setReg(getRegFromSubinstEncoding(reg)); 339 } 340 } 341 } 342 } 343 } 344 345 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 346 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 347 MCOperand &MCO = MI.getOperand(OpIndex); 348 assert(MCO.isReg() && "New value consumers must be registers"); 349 unsigned Register = 350 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 351 if ((Register & 0x6) == 0) 352 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 353 return MCDisassembler::Fail; 354 unsigned Lookback = (Register & 0x6) >> 1; 355 unsigned Offset = 1; 356 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 357 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 358 auto i = Instructions.end() - 1; 359 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 360 if (i == n) 361 // Couldn't find producer 362 return MCDisassembler::Fail; 363 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) 364 // Skip scalars when calculating distances for vectors 365 ++Lookback; 366 if (HexagonMCInstrInfo::isImmext(*i->getInst())) 367 ++Lookback; 368 if (Offset == Lookback) 369 break; 370 } 371 auto const &Inst = *i->getInst(); 372 bool SubregBit = (Register & 0x1) != 0; 373 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 374 // If subreg bit is set we're selecting the second produced newvalue 375 unsigned Producer = 376 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 377 assert(Producer != Hexagon::NoRegister); 378 MCO.setReg(Producer); 379 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 380 unsigned Producer = 381 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 382 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 383 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 384 else if (SubregBit) 385 // Hexagon PRM 10.11 New-value operands 386 // Nt[0] is reserved and should always be encoded as zero. 387 return MCDisassembler::Fail; 388 assert(Producer != Hexagon::NoRegister); 389 MCO.setReg(Producer); 390 } else 391 return MCDisassembler::Fail; 392 } 393 394 adjustExtendedInstructions(MI, MCB); 395 MCInst const *Extender = 396 HexagonMCInstrInfo::extenderForIndex(MCB, 397 HexagonMCInstrInfo::bundleSize(MCB)); 398 if(Extender != nullptr) { 399 MCInst const & Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ? 400 *MI.getOperand(1).getInst() : MI; 401 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 402 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 403 return MCDisassembler::Fail; 404 } 405 return Result; 406 } 407 408 void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI, 409 MCInst const &MCB) const { 410 if (!HexagonMCInstrInfo::hasExtenderForIndex( 411 MCB, HexagonMCInstrInfo::bundleSize(MCB))) { 412 unsigned opcode; 413 // This code is used by the disassembler to disambiguate between GP 414 // relative and absolute addressing instructions since they both have 415 // same encoding bits. However, an absolute addressing instruction must 416 // follow an immediate extender. Disassembler alwaus select absolute 417 // addressing instructions first and uses this code to change them into 418 // GP relative instruction in the absence of the corresponding immediate 419 // extender. 420 switch (MCI.getOpcode()) { 421 case Hexagon::S2_storerbabs: 422 opcode = Hexagon::S2_storerbgp; 423 break; 424 case Hexagon::S2_storerhabs: 425 opcode = Hexagon::S2_storerhgp; 426 break; 427 case Hexagon::S2_storerfabs: 428 opcode = Hexagon::S2_storerfgp; 429 break; 430 case Hexagon::S2_storeriabs: 431 opcode = Hexagon::S2_storerigp; 432 break; 433 case Hexagon::S2_storerbnewabs: 434 opcode = Hexagon::S2_storerbnewgp; 435 break; 436 case Hexagon::S2_storerhnewabs: 437 opcode = Hexagon::S2_storerhnewgp; 438 break; 439 case Hexagon::S2_storerinewabs: 440 opcode = Hexagon::S2_storerinewgp; 441 break; 442 case Hexagon::S2_storerdabs: 443 opcode = Hexagon::S2_storerdgp; 444 break; 445 case Hexagon::L4_loadrb_abs: 446 opcode = Hexagon::L2_loadrbgp; 447 break; 448 case Hexagon::L4_loadrub_abs: 449 opcode = Hexagon::L2_loadrubgp; 450 break; 451 case Hexagon::L4_loadrh_abs: 452 opcode = Hexagon::L2_loadrhgp; 453 break; 454 case Hexagon::L4_loadruh_abs: 455 opcode = Hexagon::L2_loadruhgp; 456 break; 457 case Hexagon::L4_loadri_abs: 458 opcode = Hexagon::L2_loadrigp; 459 break; 460 case Hexagon::L4_loadrd_abs: 461 opcode = Hexagon::L2_loadrdgp; 462 break; 463 default: 464 opcode = MCI.getOpcode(); 465 } 466 MCI.setOpcode(opcode); 467 } 468 } 469 470 namespace llvm { 471 extern const MCInstrDesc HexagonInsts[]; 472 } 473 474 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 475 ArrayRef<MCPhysReg> Table) { 476 if (RegNo < Table.size()) { 477 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 478 return MCDisassembler::Success; 479 } 480 481 return MCDisassembler::Fail; 482 } 483 484 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 485 uint64_t Address, 486 const void *Decoder) { 487 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 488 } 489 490 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 491 uint64_t Address, 492 const void *Decoder) { 493 static const MCPhysReg IntRegDecoderTable[] = { 494 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 495 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 496 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 497 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 498 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 499 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 500 Hexagon::R30, Hexagon::R31}; 501 502 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 503 } 504 505 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 506 uint64_t /*Address*/, 507 const void *Decoder) { 508 static const MCPhysReg VecRegDecoderTable[] = { 509 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 510 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 511 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 512 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 513 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 514 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 515 Hexagon::V30, Hexagon::V31}; 516 517 return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable); 518 } 519 520 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 521 uint64_t /*Address*/, 522 const void *Decoder) { 523 static const MCPhysReg DoubleRegDecoderTable[] = { 524 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 525 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 526 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 527 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 528 529 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 530 } 531 532 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 533 uint64_t /*Address*/, 534 const void *Decoder) { 535 static const MCPhysReg VecDblRegDecoderTable[] = { 536 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 537 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 538 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 539 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 540 541 return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable)); 542 } 543 544 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 545 uint64_t /*Address*/, 546 const void *Decoder) { 547 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 548 Hexagon::P2, Hexagon::P3}; 549 550 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 551 } 552 553 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 554 uint64_t /*Address*/, 555 const void *Decoder) { 556 static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 557 Hexagon::Q2, Hexagon::Q3}; 558 559 return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable); 560 } 561 562 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 563 uint64_t /*Address*/, 564 const void *Decoder) { 565 static const MCPhysReg CtrlRegDecoderTable[] = { 566 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, 567 Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7, 568 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, 569 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC 570 }; 571 572 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 573 return MCDisassembler::Fail; 574 575 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister) 576 return MCDisassembler::Fail; 577 578 unsigned Register = CtrlRegDecoderTable[RegNo]; 579 Inst.addOperand(MCOperand::createReg(Register)); 580 return MCDisassembler::Success; 581 } 582 583 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 584 uint64_t /*Address*/, 585 const void *Decoder) { 586 static const MCPhysReg CtrlReg64DecoderTable[] = { 587 Hexagon::C1_0, Hexagon::NoRegister, 588 Hexagon::C3_2, Hexagon::NoRegister, 589 Hexagon::C7_6, Hexagon::NoRegister, 590 Hexagon::C9_8, Hexagon::NoRegister, 591 Hexagon::C11_10, Hexagon::NoRegister, 592 Hexagon::CS, Hexagon::NoRegister, 593 Hexagon::UPC, Hexagon::NoRegister 594 }; 595 596 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 597 return MCDisassembler::Fail; 598 599 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister) 600 return MCDisassembler::Fail; 601 602 unsigned Register = CtrlReg64DecoderTable[RegNo]; 603 Inst.addOperand(MCOperand::createReg(Register)); 604 return MCDisassembler::Success; 605 } 606 607 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 608 uint64_t /*Address*/, 609 const void *Decoder) { 610 unsigned Register = 0; 611 switch (RegNo) { 612 case 0: 613 Register = Hexagon::M0; 614 break; 615 case 1: 616 Register = Hexagon::M1; 617 break; 618 default: 619 return MCDisassembler::Fail; 620 } 621 Inst.addOperand(MCOperand::createReg(Register)); 622 return MCDisassembler::Success; 623 } 624 625 namespace { 626 uint32_t fullValue(MCInstrInfo const &MCII, 627 MCInst &MCB, 628 MCInst &MI, 629 int64_t Value) { 630 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 631 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 632 if(!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 633 return Value; 634 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 635 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 636 int64_t Bits; 637 bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); 638 assert(Success);(void)Success; 639 uint32_t Upper26 = static_cast<uint32_t>(Bits); 640 uint32_t Operand = Upper26 | Lower6; 641 return Operand; 642 } 643 template <size_t T> 644 void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 645 HexagonDisassembler const &Disassembler = disassembler(Decoder); 646 int64_t FullValue = fullValue(*Disassembler.MCII, 647 **Disassembler.CurrentBundle, 648 MI, SignExtend64<T>(tmp)); 649 int64_t Extended = SignExtend64<32>(FullValue); 650 HexagonMCInstrInfo::addConstant(MI, Extended, 651 Disassembler.getContext()); 652 } 653 } 654 655 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 656 uint64_t /*Address*/, 657 const void *Decoder) { 658 HexagonDisassembler const &Disassembler = disassembler(Decoder); 659 int64_t FullValue = fullValue(*Disassembler.MCII, 660 **Disassembler.CurrentBundle, 661 MI, tmp); 662 assert(FullValue >= 0 && "Negative in unsigned decoder"); 663 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 664 return MCDisassembler::Success; 665 } 666 667 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, 668 uint64_t /*Address*/, const void *Decoder) { 669 signedDecoder<16>(MI, tmp, Decoder); 670 return MCDisassembler::Success; 671 } 672 673 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, 674 uint64_t /*Address*/, const void *Decoder) { 675 signedDecoder<12>(MI, tmp, Decoder); 676 return MCDisassembler::Success; 677 } 678 679 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, 680 uint64_t /*Address*/, const void *Decoder) { 681 signedDecoder<11>(MI, tmp, Decoder); 682 return MCDisassembler::Success; 683 } 684 685 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, 686 uint64_t /*Address*/, const void *Decoder) { 687 HexagonMCInstrInfo::addConstant(MI, SignExtend64<12>(tmp), contextFromDecoder(Decoder)); 688 return MCDisassembler::Success; 689 } 690 691 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, 692 uint64_t /*Address*/, const void *Decoder) { 693 signedDecoder<13>(MI, tmp, Decoder); 694 return MCDisassembler::Success; 695 } 696 697 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, 698 uint64_t /*Address*/, const void *Decoder) { 699 signedDecoder<14>(MI, tmp, Decoder); 700 return MCDisassembler::Success; 701 } 702 703 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, 704 uint64_t /*Address*/, const void *Decoder) { 705 signedDecoder<10>(MI, tmp, Decoder); 706 return MCDisassembler::Success; 707 } 708 709 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, 710 const void *Decoder) { 711 signedDecoder<8>(MI, tmp, Decoder); 712 return MCDisassembler::Success; 713 } 714 715 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, 716 uint64_t /*Address*/, const void *Decoder) { 717 signedDecoder<6>(MI, tmp, Decoder); 718 return MCDisassembler::Success; 719 } 720 721 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, 722 uint64_t /*Address*/, const void *Decoder) { 723 signedDecoder<4>(MI, tmp, Decoder); 724 return MCDisassembler::Success; 725 } 726 727 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, 728 uint64_t /*Address*/, const void *Decoder) { 729 signedDecoder<5>(MI, tmp, Decoder); 730 return MCDisassembler::Success; 731 } 732 733 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, 734 uint64_t /*Address*/, const void *Decoder) { 735 signedDecoder<6>(MI, tmp, Decoder); 736 return MCDisassembler::Success; 737 } 738 739 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, 740 uint64_t /*Address*/, const void *Decoder) { 741 signedDecoder<7>(MI, tmp, Decoder); 742 return MCDisassembler::Success; 743 } 744 745 static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, 746 uint64_t /*Address*/, const void *Decoder) { 747 signedDecoder<10>(MI, tmp, Decoder); 748 return MCDisassembler::Success; 749 } 750 751 static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, 752 uint64_t /*Address*/, const void *Decoder) { 753 signedDecoder<19>(MI, tmp, Decoder); 754 return MCDisassembler::Success; 755 } 756 757 // custom decoder for various jump/call immediates 758 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 759 const void *Decoder) { 760 HexagonDisassembler const &Disassembler = disassembler(Decoder); 761 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 762 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 763 if (Bits == 0) 764 Bits = 15; 765 uint32_t FullValue = fullValue(*Disassembler.MCII, 766 **Disassembler.CurrentBundle, 767 MI, SignExtend64(tmp, Bits)); 768 int64_t Extended = SignExtend64<32>(FullValue) + Address; 769 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 770 0, 4)) 771 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 772 return MCDisassembler::Success; 773 } 774 775 // Addressing mode dependent load store opcode map. 776 // - If an insn is preceded by an extender the address is absolute. 777 // - memw(##symbol) = r0 778 // - If an insn is not preceded by an extender the address is GP relative. 779 // - memw(gp + #symbol) = r0 780 // Please note that the instructions must be ordered in the descending order 781 // of their opcode. 782 // HexagonII::INST_ICLASS_ST 783 static const unsigned int StoreConditionalOpcodeData[][2] = { 784 {S4_pstorerdfnew_abs, 0xafc02084}, 785 {S4_pstorerdtnew_abs, 0xafc02080}, 786 {S4_pstorerdf_abs, 0xafc00084}, 787 {S4_pstorerdt_abs, 0xafc00080}, 788 {S4_pstorerinewfnew_abs, 0xafa03084}, 789 {S4_pstorerinewtnew_abs, 0xafa03080}, 790 {S4_pstorerhnewfnew_abs, 0xafa02884}, 791 {S4_pstorerhnewtnew_abs, 0xafa02880}, 792 {S4_pstorerbnewfnew_abs, 0xafa02084}, 793 {S4_pstorerbnewtnew_abs, 0xafa02080}, 794 {S4_pstorerinewf_abs, 0xafa01084}, 795 {S4_pstorerinewt_abs, 0xafa01080}, 796 {S4_pstorerhnewf_abs, 0xafa00884}, 797 {S4_pstorerhnewt_abs, 0xafa00880}, 798 {S4_pstorerbnewf_abs, 0xafa00084}, 799 {S4_pstorerbnewt_abs, 0xafa00080}, 800 {S4_pstorerifnew_abs, 0xaf802084}, 801 {S4_pstoreritnew_abs, 0xaf802080}, 802 {S4_pstorerif_abs, 0xaf800084}, 803 {S4_pstorerit_abs, 0xaf800080}, 804 {S4_pstorerhfnew_abs, 0xaf402084}, 805 {S4_pstorerhtnew_abs, 0xaf402080}, 806 {S4_pstorerhf_abs, 0xaf400084}, 807 {S4_pstorerht_abs, 0xaf400080}, 808 {S4_pstorerbfnew_abs, 0xaf002084}, 809 {S4_pstorerbtnew_abs, 0xaf002080}, 810 {S4_pstorerbf_abs, 0xaf000084}, 811 {S4_pstorerbt_abs, 0xaf000080}}; 812 // HexagonII::INST_ICLASS_LD 813 814 // HexagonII::INST_ICLASS_LD_ST_2 815 static unsigned int LoadStoreOpcodeData[][2] = {{L4_loadrd_abs, 0x49c00000}, 816 {L4_loadri_abs, 0x49800000}, 817 {L4_loadruh_abs, 0x49600000}, 818 {L4_loadrh_abs, 0x49400000}, 819 {L4_loadrub_abs, 0x49200000}, 820 {L4_loadrb_abs, 0x49000000}, 821 {S2_storerdabs, 0x48c00000}, 822 {S2_storerinewabs, 0x48a01000}, 823 {S2_storerhnewabs, 0x48a00800}, 824 {S2_storerbnewabs, 0x48a00000}, 825 {S2_storeriabs, 0x48800000}, 826 {S2_storerfabs, 0x48600000}, 827 {S2_storerhabs, 0x48400000}, 828 {S2_storerbabs, 0x48000000}}; 829 static const size_t NumCondS = array_lengthof(StoreConditionalOpcodeData); 830 static const size_t NumLS = array_lengthof(LoadStoreOpcodeData); 831 832 static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) { 833 834 unsigned MachineOpcode = 0; 835 unsigned LLVMOpcode = 0; 836 837 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_ST) { 838 for (size_t i = 0; i < NumCondS; ++i) { 839 if ((insn & StoreConditionalOpcodeData[i][1]) == 840 StoreConditionalOpcodeData[i][1]) { 841 MachineOpcode = StoreConditionalOpcodeData[i][1]; 842 LLVMOpcode = StoreConditionalOpcodeData[i][0]; 843 break; 844 } 845 } 846 } 847 if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_LD_ST_2) { 848 for (size_t i = 0; i < NumLS; ++i) { 849 if ((insn & LoadStoreOpcodeData[i][1]) == LoadStoreOpcodeData[i][1]) { 850 MachineOpcode = LoadStoreOpcodeData[i][1]; 851 LLVMOpcode = LoadStoreOpcodeData[i][0]; 852 break; 853 } 854 } 855 } 856 857 if (MachineOpcode) { 858 unsigned Value = 0; 859 unsigned shift = 0; 860 MI.setOpcode(LLVMOpcode); 861 // Remove the parse bits from the insn. 862 insn &= ~HexagonII::INST_PARSE_MASK; 863 864 switch (LLVMOpcode) { 865 default: 866 return MCDisassembler::Fail; 867 break; 868 869 case Hexagon::S4_pstorerdf_abs: 870 case Hexagon::S4_pstorerdt_abs: 871 case Hexagon::S4_pstorerdfnew_abs: 872 case Hexagon::S4_pstorerdtnew_abs: { 873 // op: Pv 874 Value = insn & UINT64_C(3); 875 DecodePredRegsRegisterClass(MI, Value, 0, 0); 876 // op: u6 877 Value = (insn >> 12) & UINT64_C(48); 878 Value |= (insn >> 3) & UINT64_C(15); 879 MI.addOperand(MCOperand::createImm(Value)); 880 // op: Rtt 881 Value = (insn >> 8) & UINT64_C(31); 882 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 883 break; 884 } 885 886 case Hexagon::S4_pstorerbnewf_abs: 887 case Hexagon::S4_pstorerbnewt_abs: 888 case Hexagon::S4_pstorerbnewfnew_abs: 889 case Hexagon::S4_pstorerbnewtnew_abs: 890 case Hexagon::S4_pstorerhnewf_abs: 891 case Hexagon::S4_pstorerhnewt_abs: 892 case Hexagon::S4_pstorerhnewfnew_abs: 893 case Hexagon::S4_pstorerhnewtnew_abs: 894 case Hexagon::S4_pstorerinewf_abs: 895 case Hexagon::S4_pstorerinewt_abs: 896 case Hexagon::S4_pstorerinewfnew_abs: 897 case Hexagon::S4_pstorerinewtnew_abs: { 898 // op: Pv 899 Value = insn & UINT64_C(3); 900 DecodePredRegsRegisterClass(MI, Value, 0, 0); 901 // op: u6 902 Value = (insn >> 12) & UINT64_C(48); 903 Value |= (insn >> 3) & UINT64_C(15); 904 MI.addOperand(MCOperand::createImm(Value)); 905 // op: Nt 906 Value = (insn >> 8) & UINT64_C(7); 907 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 908 break; 909 } 910 911 case Hexagon::S4_pstorerbf_abs: 912 case Hexagon::S4_pstorerbt_abs: 913 case Hexagon::S4_pstorerbfnew_abs: 914 case Hexagon::S4_pstorerbtnew_abs: 915 case Hexagon::S4_pstorerhf_abs: 916 case Hexagon::S4_pstorerht_abs: 917 case Hexagon::S4_pstorerhfnew_abs: 918 case Hexagon::S4_pstorerhtnew_abs: 919 case Hexagon::S4_pstorerif_abs: 920 case Hexagon::S4_pstorerit_abs: 921 case Hexagon::S4_pstorerifnew_abs: 922 case Hexagon::S4_pstoreritnew_abs: { 923 // op: Pv 924 Value = insn & UINT64_C(3); 925 DecodePredRegsRegisterClass(MI, Value, 0, 0); 926 // op: u6 927 Value = (insn >> 12) & UINT64_C(48); 928 Value |= (insn >> 3) & UINT64_C(15); 929 MI.addOperand(MCOperand::createImm(Value)); 930 // op: Rt 931 Value = (insn >> 8) & UINT64_C(31); 932 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 933 break; 934 } 935 936 case Hexagon::L4_ploadrdf_abs: 937 case Hexagon::L4_ploadrdt_abs: 938 case Hexagon::L4_ploadrdfnew_abs: 939 case Hexagon::L4_ploadrdtnew_abs: { 940 // op: Rdd 941 Value = insn & UINT64_C(31); 942 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 943 // op: Pt 944 Value = ((insn >> 9) & UINT64_C(3)); 945 DecodePredRegsRegisterClass(MI, Value, 0, 0); 946 // op: u6 947 Value = ((insn >> 15) & UINT64_C(62)); 948 Value |= ((insn >> 8) & UINT64_C(1)); 949 MI.addOperand(MCOperand::createImm(Value)); 950 break; 951 } 952 953 case Hexagon::L4_ploadrbf_abs: 954 case Hexagon::L4_ploadrbt_abs: 955 case Hexagon::L4_ploadrbfnew_abs: 956 case Hexagon::L4_ploadrbtnew_abs: 957 case Hexagon::L4_ploadrhf_abs: 958 case Hexagon::L4_ploadrht_abs: 959 case Hexagon::L4_ploadrhfnew_abs: 960 case Hexagon::L4_ploadrhtnew_abs: 961 case Hexagon::L4_ploadrubf_abs: 962 case Hexagon::L4_ploadrubt_abs: 963 case Hexagon::L4_ploadrubfnew_abs: 964 case Hexagon::L4_ploadrubtnew_abs: 965 case Hexagon::L4_ploadruhf_abs: 966 case Hexagon::L4_ploadruht_abs: 967 case Hexagon::L4_ploadruhfnew_abs: 968 case Hexagon::L4_ploadruhtnew_abs: 969 case Hexagon::L4_ploadrif_abs: 970 case Hexagon::L4_ploadrit_abs: 971 case Hexagon::L4_ploadrifnew_abs: 972 case Hexagon::L4_ploadritnew_abs: 973 // op: Rd 974 Value = insn & UINT64_C(31); 975 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 976 // op: Pt 977 Value = (insn >> 9) & UINT64_C(3); 978 DecodePredRegsRegisterClass(MI, Value, 0, 0); 979 // op: u6 980 Value = (insn >> 15) & UINT64_C(62); 981 Value |= (insn >> 8) & UINT64_C(1); 982 MI.addOperand(MCOperand::createImm(Value)); 983 break; 984 985 // op: g16_2 986 case (Hexagon::L4_loadri_abs): 987 ++shift; 988 // op: g16_1 989 case Hexagon::L4_loadrh_abs: 990 case Hexagon::L4_loadruh_abs: 991 ++shift; 992 // op: g16_0 993 case Hexagon::L4_loadrb_abs: 994 case Hexagon::L4_loadrub_abs: { 995 // op: Rd 996 Value |= insn & UINT64_C(31); 997 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 998 Value = (insn >> 11) & UINT64_C(49152); 999 Value |= (insn >> 7) & UINT64_C(15872); 1000 Value |= (insn >> 5) & UINT64_C(511); 1001 MI.addOperand(MCOperand::createImm(Value << shift)); 1002 break; 1003 } 1004 1005 case Hexagon::L4_loadrd_abs: { 1006 Value = insn & UINT64_C(31); 1007 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 1008 Value = (insn >> 11) & UINT64_C(49152); 1009 Value |= (insn >> 7) & UINT64_C(15872); 1010 Value |= (insn >> 5) & UINT64_C(511); 1011 MI.addOperand(MCOperand::createImm(Value << 3)); 1012 break; 1013 } 1014 1015 case Hexagon::S2_storerdabs: { 1016 // op: g16_3 1017 Value = (insn >> 11) & UINT64_C(49152); 1018 Value |= (insn >> 7) & UINT64_C(15872); 1019 Value |= (insn >> 5) & UINT64_C(256); 1020 Value |= insn & UINT64_C(255); 1021 MI.addOperand(MCOperand::createImm(Value << 3)); 1022 // op: Rtt 1023 Value = (insn >> 8) & UINT64_C(31); 1024 DecodeDoubleRegsRegisterClass(MI, Value, 0, 0); 1025 break; 1026 } 1027 1028 // op: g16_2 1029 case Hexagon::S2_storerinewabs: 1030 ++shift; 1031 // op: g16_1 1032 case Hexagon::S2_storerhnewabs: 1033 ++shift; 1034 // op: g16_0 1035 case Hexagon::S2_storerbnewabs: { 1036 Value = (insn >> 11) & UINT64_C(49152); 1037 Value |= (insn >> 7) & UINT64_C(15872); 1038 Value |= (insn >> 5) & UINT64_C(256); 1039 Value |= insn & UINT64_C(255); 1040 MI.addOperand(MCOperand::createImm(Value << shift)); 1041 // op: Nt 1042 Value = (insn >> 8) & UINT64_C(7); 1043 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1044 break; 1045 } 1046 1047 // op: g16_2 1048 case Hexagon::S2_storeriabs: 1049 ++shift; 1050 // op: g16_1 1051 case Hexagon::S2_storerhabs: 1052 case Hexagon::S2_storerfabs: 1053 ++shift; 1054 // op: g16_0 1055 case Hexagon::S2_storerbabs: { 1056 Value = (insn >> 11) & UINT64_C(49152); 1057 Value |= (insn >> 7) & UINT64_C(15872); 1058 Value |= (insn >> 5) & UINT64_C(256); 1059 Value |= insn & UINT64_C(255); 1060 MI.addOperand(MCOperand::createImm(Value << shift)); 1061 // op: Rt 1062 Value = (insn >> 8) & UINT64_C(31); 1063 DecodeIntRegsRegisterClass(MI, Value, 0, 0); 1064 break; 1065 } 1066 } 1067 return MCDisassembler::Success; 1068 } 1069 return MCDisassembler::Fail; 1070 } 1071 1072 static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, 1073 void const *Decoder) { 1074 1075 // Instruction Class for a constant a extender: bits 31:28 = 0x0000 1076 if ((~insn & 0xf0000000) == 0xf0000000) { 1077 unsigned Value; 1078 // 27:16 High 12 bits of 26-bit extender. 1079 Value = (insn & 0x0fff0000) << 4; 1080 // 13:0 Low 14 bits of 26-bit extender. 1081 Value |= ((insn & 0x3fff) << 6); 1082 MI.setOpcode(Hexagon::A4_ext); 1083 HexagonMCInstrInfo::addConstant(MI, Value, contextFromDecoder(Decoder)); 1084 return MCDisassembler::Success; 1085 } 1086 return MCDisassembler::Fail; 1087 } 1088 1089 // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td 1090 enum subInstBinaryValues { 1091 V4_SA1_addi_BITS = 0x0000, 1092 V4_SA1_addi_MASK = 0x1800, 1093 V4_SA1_addrx_BITS = 0x1800, 1094 V4_SA1_addrx_MASK = 0x1f00, 1095 V4_SA1_addsp_BITS = 0x0c00, 1096 V4_SA1_addsp_MASK = 0x1c00, 1097 V4_SA1_and1_BITS = 0x1200, 1098 V4_SA1_and1_MASK = 0x1f00, 1099 V4_SA1_clrf_BITS = 0x1a70, 1100 V4_SA1_clrf_MASK = 0x1e70, 1101 V4_SA1_clrfnew_BITS = 0x1a50, 1102 V4_SA1_clrfnew_MASK = 0x1e70, 1103 V4_SA1_clrt_BITS = 0x1a60, 1104 V4_SA1_clrt_MASK = 0x1e70, 1105 V4_SA1_clrtnew_BITS = 0x1a40, 1106 V4_SA1_clrtnew_MASK = 0x1e70, 1107 V4_SA1_cmpeqi_BITS = 0x1900, 1108 V4_SA1_cmpeqi_MASK = 0x1f00, 1109 V4_SA1_combine0i_BITS = 0x1c00, 1110 V4_SA1_combine0i_MASK = 0x1d18, 1111 V4_SA1_combine1i_BITS = 0x1c08, 1112 V4_SA1_combine1i_MASK = 0x1d18, 1113 V4_SA1_combine2i_BITS = 0x1c10, 1114 V4_SA1_combine2i_MASK = 0x1d18, 1115 V4_SA1_combine3i_BITS = 0x1c18, 1116 V4_SA1_combine3i_MASK = 0x1d18, 1117 V4_SA1_combinerz_BITS = 0x1d08, 1118 V4_SA1_combinerz_MASK = 0x1d08, 1119 V4_SA1_combinezr_BITS = 0x1d00, 1120 V4_SA1_combinezr_MASK = 0x1d08, 1121 V4_SA1_dec_BITS = 0x1300, 1122 V4_SA1_dec_MASK = 0x1f00, 1123 V4_SA1_inc_BITS = 0x1100, 1124 V4_SA1_inc_MASK = 0x1f00, 1125 V4_SA1_seti_BITS = 0x0800, 1126 V4_SA1_seti_MASK = 0x1c00, 1127 V4_SA1_setin1_BITS = 0x1a00, 1128 V4_SA1_setin1_MASK = 0x1e40, 1129 V4_SA1_sxtb_BITS = 0x1500, 1130 V4_SA1_sxtb_MASK = 0x1f00, 1131 V4_SA1_sxth_BITS = 0x1400, 1132 V4_SA1_sxth_MASK = 0x1f00, 1133 V4_SA1_tfr_BITS = 0x1000, 1134 V4_SA1_tfr_MASK = 0x1f00, 1135 V4_SA1_zxtb_BITS = 0x1700, 1136 V4_SA1_zxtb_MASK = 0x1f00, 1137 V4_SA1_zxth_BITS = 0x1600, 1138 V4_SA1_zxth_MASK = 0x1f00, 1139 V4_SL1_loadri_io_BITS = 0x0000, 1140 V4_SL1_loadri_io_MASK = 0x1000, 1141 V4_SL1_loadrub_io_BITS = 0x1000, 1142 V4_SL1_loadrub_io_MASK = 0x1000, 1143 V4_SL2_deallocframe_BITS = 0x1f00, 1144 V4_SL2_deallocframe_MASK = 0x1fc0, 1145 V4_SL2_jumpr31_BITS = 0x1fc0, 1146 V4_SL2_jumpr31_MASK = 0x1fc4, 1147 V4_SL2_jumpr31_f_BITS = 0x1fc5, 1148 V4_SL2_jumpr31_f_MASK = 0x1fc7, 1149 V4_SL2_jumpr31_fnew_BITS = 0x1fc7, 1150 V4_SL2_jumpr31_fnew_MASK = 0x1fc7, 1151 V4_SL2_jumpr31_t_BITS = 0x1fc4, 1152 V4_SL2_jumpr31_t_MASK = 0x1fc7, 1153 V4_SL2_jumpr31_tnew_BITS = 0x1fc6, 1154 V4_SL2_jumpr31_tnew_MASK = 0x1fc7, 1155 V4_SL2_loadrb_io_BITS = 0x1000, 1156 V4_SL2_loadrb_io_MASK = 0x1800, 1157 V4_SL2_loadrd_sp_BITS = 0x1e00, 1158 V4_SL2_loadrd_sp_MASK = 0x1f00, 1159 V4_SL2_loadrh_io_BITS = 0x0000, 1160 V4_SL2_loadrh_io_MASK = 0x1800, 1161 V4_SL2_loadri_sp_BITS = 0x1c00, 1162 V4_SL2_loadri_sp_MASK = 0x1e00, 1163 V4_SL2_loadruh_io_BITS = 0x0800, 1164 V4_SL2_loadruh_io_MASK = 0x1800, 1165 V4_SL2_return_BITS = 0x1f40, 1166 V4_SL2_return_MASK = 0x1fc4, 1167 V4_SL2_return_f_BITS = 0x1f45, 1168 V4_SL2_return_f_MASK = 0x1fc7, 1169 V4_SL2_return_fnew_BITS = 0x1f47, 1170 V4_SL2_return_fnew_MASK = 0x1fc7, 1171 V4_SL2_return_t_BITS = 0x1f44, 1172 V4_SL2_return_t_MASK = 0x1fc7, 1173 V4_SL2_return_tnew_BITS = 0x1f46, 1174 V4_SL2_return_tnew_MASK = 0x1fc7, 1175 V4_SS1_storeb_io_BITS = 0x1000, 1176 V4_SS1_storeb_io_MASK = 0x1000, 1177 V4_SS1_storew_io_BITS = 0x0000, 1178 V4_SS1_storew_io_MASK = 0x1000, 1179 V4_SS2_allocframe_BITS = 0x1c00, 1180 V4_SS2_allocframe_MASK = 0x1e00, 1181 V4_SS2_storebi0_BITS = 0x1200, 1182 V4_SS2_storebi0_MASK = 0x1f00, 1183 V4_SS2_storebi1_BITS = 0x1300, 1184 V4_SS2_storebi1_MASK = 0x1f00, 1185 V4_SS2_stored_sp_BITS = 0x0a00, 1186 V4_SS2_stored_sp_MASK = 0x1e00, 1187 V4_SS2_storeh_io_BITS = 0x0000, 1188 V4_SS2_storeh_io_MASK = 0x1800, 1189 V4_SS2_storew_sp_BITS = 0x0800, 1190 V4_SS2_storew_sp_MASK = 0x1e00, 1191 V4_SS2_storewi0_BITS = 0x1000, 1192 V4_SS2_storewi0_MASK = 0x1f00, 1193 V4_SS2_storewi1_BITS = 0x1100, 1194 V4_SS2_storewi1_MASK = 0x1f00 1195 }; 1196 1197 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, 1198 raw_ostream &os) { 1199 switch (IClass) { 1200 case HexagonII::HSIG_L1: 1201 if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS) 1202 op = Hexagon::V4_SL1_loadri_io; 1203 else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS) 1204 op = Hexagon::V4_SL1_loadrub_io; 1205 else { 1206 os << "<unknown subinstruction>"; 1207 return MCDisassembler::Fail; 1208 } 1209 break; 1210 case HexagonII::HSIG_L2: 1211 if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS) 1212 op = Hexagon::V4_SL2_deallocframe; 1213 else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS) 1214 op = Hexagon::V4_SL2_jumpr31; 1215 else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS) 1216 op = Hexagon::V4_SL2_jumpr31_f; 1217 else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS) 1218 op = Hexagon::V4_SL2_jumpr31_fnew; 1219 else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS) 1220 op = Hexagon::V4_SL2_jumpr31_t; 1221 else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS) 1222 op = Hexagon::V4_SL2_jumpr31_tnew; 1223 else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS) 1224 op = Hexagon::V4_SL2_loadrb_io; 1225 else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS) 1226 op = Hexagon::V4_SL2_loadrd_sp; 1227 else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS) 1228 op = Hexagon::V4_SL2_loadrh_io; 1229 else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS) 1230 op = Hexagon::V4_SL2_loadri_sp; 1231 else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS) 1232 op = Hexagon::V4_SL2_loadruh_io; 1233 else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS) 1234 op = Hexagon::V4_SL2_return; 1235 else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS) 1236 op = Hexagon::V4_SL2_return_f; 1237 else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS) 1238 op = Hexagon::V4_SL2_return_fnew; 1239 else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS) 1240 op = Hexagon::V4_SL2_return_t; 1241 else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS) 1242 op = Hexagon::V4_SL2_return_tnew; 1243 else { 1244 os << "<unknown subinstruction>"; 1245 return MCDisassembler::Fail; 1246 } 1247 break; 1248 case HexagonII::HSIG_A: 1249 if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS) 1250 op = Hexagon::V4_SA1_addi; 1251 else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS) 1252 op = Hexagon::V4_SA1_addrx; 1253 else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS) 1254 op = Hexagon::V4_SA1_addsp; 1255 else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS) 1256 op = Hexagon::V4_SA1_and1; 1257 else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS) 1258 op = Hexagon::V4_SA1_clrf; 1259 else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS) 1260 op = Hexagon::V4_SA1_clrfnew; 1261 else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS) 1262 op = Hexagon::V4_SA1_clrt; 1263 else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS) 1264 op = Hexagon::V4_SA1_clrtnew; 1265 else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS) 1266 op = Hexagon::V4_SA1_cmpeqi; 1267 else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS) 1268 op = Hexagon::V4_SA1_combine0i; 1269 else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS) 1270 op = Hexagon::V4_SA1_combine1i; 1271 else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS) 1272 op = Hexagon::V4_SA1_combine2i; 1273 else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS) 1274 op = Hexagon::V4_SA1_combine3i; 1275 else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS) 1276 op = Hexagon::V4_SA1_combinerz; 1277 else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS) 1278 op = Hexagon::V4_SA1_combinezr; 1279 else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS) 1280 op = Hexagon::V4_SA1_dec; 1281 else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS) 1282 op = Hexagon::V4_SA1_inc; 1283 else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS) 1284 op = Hexagon::V4_SA1_seti; 1285 else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS) 1286 op = Hexagon::V4_SA1_setin1; 1287 else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS) 1288 op = Hexagon::V4_SA1_sxtb; 1289 else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS) 1290 op = Hexagon::V4_SA1_sxth; 1291 else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS) 1292 op = Hexagon::V4_SA1_tfr; 1293 else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS) 1294 op = Hexagon::V4_SA1_zxtb; 1295 else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS) 1296 op = Hexagon::V4_SA1_zxth; 1297 else { 1298 os << "<unknown subinstruction>"; 1299 return MCDisassembler::Fail; 1300 } 1301 break; 1302 case HexagonII::HSIG_S1: 1303 if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS) 1304 op = Hexagon::V4_SS1_storeb_io; 1305 else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS) 1306 op = Hexagon::V4_SS1_storew_io; 1307 else { 1308 os << "<unknown subinstruction>"; 1309 return MCDisassembler::Fail; 1310 } 1311 break; 1312 case HexagonII::HSIG_S2: 1313 if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS) 1314 op = Hexagon::V4_SS2_allocframe; 1315 else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS) 1316 op = Hexagon::V4_SS2_storebi0; 1317 else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS) 1318 op = Hexagon::V4_SS2_storebi1; 1319 else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS) 1320 op = Hexagon::V4_SS2_stored_sp; 1321 else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS) 1322 op = Hexagon::V4_SS2_storeh_io; 1323 else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS) 1324 op = Hexagon::V4_SS2_storew_sp; 1325 else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS) 1326 op = Hexagon::V4_SS2_storewi0; 1327 else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS) 1328 op = Hexagon::V4_SS2_storewi1; 1329 else { 1330 os << "<unknown subinstruction>"; 1331 return MCDisassembler::Fail; 1332 } 1333 break; 1334 default: 1335 os << "<unknown>"; 1336 return MCDisassembler::Fail; 1337 } 1338 return MCDisassembler::Success; 1339 } 1340 1341 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) { 1342 if (encoded_reg < 8) 1343 return Hexagon::R0 + encoded_reg; 1344 else if (encoded_reg < 16) 1345 return Hexagon::R0 + encoded_reg + 8; 1346 1347 // patently false value 1348 return Hexagon::NoRegister; 1349 } 1350 1351 static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) { 1352 if (encoded_dreg < 4) 1353 return Hexagon::D0 + encoded_dreg; 1354 else if (encoded_dreg < 8) 1355 return Hexagon::D0 + encoded_dreg + 4; 1356 1357 // patently false value 1358 return Hexagon::NoRegister; 1359 } 1360 1361 void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode, 1362 unsigned inst) const { 1363 int64_t operand; 1364 MCOperand Op; 1365 switch (opcode) { 1366 case Hexagon::V4_SL2_deallocframe: 1367 case Hexagon::V4_SL2_jumpr31: 1368 case Hexagon::V4_SL2_jumpr31_f: 1369 case Hexagon::V4_SL2_jumpr31_fnew: 1370 case Hexagon::V4_SL2_jumpr31_t: 1371 case Hexagon::V4_SL2_jumpr31_tnew: 1372 case Hexagon::V4_SL2_return: 1373 case Hexagon::V4_SL2_return_f: 1374 case Hexagon::V4_SL2_return_fnew: 1375 case Hexagon::V4_SL2_return_t: 1376 case Hexagon::V4_SL2_return_tnew: 1377 // no operands for these instructions 1378 break; 1379 case Hexagon::V4_SS2_allocframe: 1380 // u 8-4{5_3} 1381 operand = ((inst & 0x1f0) >> 4) << 3; 1382 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1383 break; 1384 case Hexagon::V4_SL1_loadri_io: 1385 // Rd 3-0, Rs 7-4, u 11-8{4_2} 1386 operand = getRegFromSubinstEncoding(inst & 0xf); 1387 Op = MCOperand::createReg(operand); 1388 MI->addOperand(Op); 1389 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1390 Op = MCOperand::createReg(operand); 1391 MI->addOperand(Op); 1392 operand = (inst & 0xf00) >> 6; 1393 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1394 break; 1395 case Hexagon::V4_SL1_loadrub_io: 1396 // Rd 3-0, Rs 7-4, u 11-8 1397 operand = getRegFromSubinstEncoding(inst & 0xf); 1398 Op = MCOperand::createReg(operand); 1399 MI->addOperand(Op); 1400 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1401 Op = MCOperand::createReg(operand); 1402 MI->addOperand(Op); 1403 operand = (inst & 0xf00) >> 8; 1404 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1405 break; 1406 case Hexagon::V4_SL2_loadrb_io: 1407 // Rd 3-0, Rs 7-4, u 10-8 1408 operand = getRegFromSubinstEncoding(inst & 0xf); 1409 Op = MCOperand::createReg(operand); 1410 MI->addOperand(Op); 1411 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1412 Op = MCOperand::createReg(operand); 1413 MI->addOperand(Op); 1414 operand = (inst & 0x700) >> 8; 1415 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1416 break; 1417 case Hexagon::V4_SL2_loadrh_io: 1418 case Hexagon::V4_SL2_loadruh_io: 1419 // Rd 3-0, Rs 7-4, u 10-8{3_1} 1420 operand = getRegFromSubinstEncoding(inst & 0xf); 1421 Op = MCOperand::createReg(operand); 1422 MI->addOperand(Op); 1423 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1424 Op = MCOperand::createReg(operand); 1425 MI->addOperand(Op); 1426 operand = ((inst & 0x700) >> 8) << 1; 1427 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1428 break; 1429 case Hexagon::V4_SL2_loadrd_sp: 1430 // Rdd 2-0, u 7-3{5_3} 1431 operand = getDRegFromSubinstEncoding(inst & 0x7); 1432 Op = MCOperand::createReg(operand); 1433 MI->addOperand(Op); 1434 operand = ((inst & 0x0f8) >> 3) << 3; 1435 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1436 break; 1437 case Hexagon::V4_SL2_loadri_sp: 1438 // Rd 3-0, u 8-4{5_2} 1439 operand = getRegFromSubinstEncoding(inst & 0xf); 1440 Op = MCOperand::createReg(operand); 1441 MI->addOperand(Op); 1442 operand = ((inst & 0x1f0) >> 4) << 2; 1443 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1444 break; 1445 case Hexagon::V4_SA1_addi: 1446 // Rx 3-0 (x2), s7 10-4 1447 operand = getRegFromSubinstEncoding(inst & 0xf); 1448 Op = MCOperand::createReg(operand); 1449 MI->addOperand(Op); 1450 MI->addOperand(Op); 1451 operand = SignExtend64<7>((inst & 0x7f0) >> 4); 1452 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1453 break; 1454 case Hexagon::V4_SA1_addrx: 1455 // Rx 3-0 (x2), Rs 7-4 1456 operand = getRegFromSubinstEncoding(inst & 0xf); 1457 Op = MCOperand::createReg(operand); 1458 MI->addOperand(Op); 1459 MI->addOperand(Op); 1460 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1461 Op = MCOperand::createReg(operand); 1462 MI->addOperand(Op); 1463 break; 1464 case Hexagon::V4_SA1_and1: 1465 case Hexagon::V4_SA1_dec: 1466 case Hexagon::V4_SA1_inc: 1467 case Hexagon::V4_SA1_sxtb: 1468 case Hexagon::V4_SA1_sxth: 1469 case Hexagon::V4_SA1_tfr: 1470 case Hexagon::V4_SA1_zxtb: 1471 case Hexagon::V4_SA1_zxth: 1472 // Rd 3-0, Rs 7-4 1473 operand = getRegFromSubinstEncoding(inst & 0xf); 1474 Op = MCOperand::createReg(operand); 1475 MI->addOperand(Op); 1476 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1477 Op = MCOperand::createReg(operand); 1478 MI->addOperand(Op); 1479 break; 1480 case Hexagon::V4_SA1_addsp: 1481 // Rd 3-0, u 9-4{6_2} 1482 operand = getRegFromSubinstEncoding(inst & 0xf); 1483 Op = MCOperand::createReg(operand); 1484 MI->addOperand(Op); 1485 operand = ((inst & 0x3f0) >> 4) << 2; 1486 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1487 break; 1488 case Hexagon::V4_SA1_seti: 1489 // Rd 3-0, u 9-4 1490 operand = getRegFromSubinstEncoding(inst & 0xf); 1491 Op = MCOperand::createReg(operand); 1492 MI->addOperand(Op); 1493 operand = (inst & 0x3f0) >> 4; 1494 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1495 break; 1496 case Hexagon::V4_SA1_clrf: 1497 case Hexagon::V4_SA1_clrfnew: 1498 case Hexagon::V4_SA1_clrt: 1499 case Hexagon::V4_SA1_clrtnew: 1500 case Hexagon::V4_SA1_setin1: 1501 // Rd 3-0 1502 operand = getRegFromSubinstEncoding(inst & 0xf); 1503 Op = MCOperand::createReg(operand); 1504 MI->addOperand(Op); 1505 break; 1506 case Hexagon::V4_SA1_cmpeqi: 1507 // Rs 7-4, u 1-0 1508 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1509 Op = MCOperand::createReg(operand); 1510 MI->addOperand(Op); 1511 operand = inst & 0x3; 1512 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1513 break; 1514 case Hexagon::V4_SA1_combine0i: 1515 case Hexagon::V4_SA1_combine1i: 1516 case Hexagon::V4_SA1_combine2i: 1517 case Hexagon::V4_SA1_combine3i: 1518 // Rdd 2-0, u 6-5 1519 operand = getDRegFromSubinstEncoding(inst & 0x7); 1520 Op = MCOperand::createReg(operand); 1521 MI->addOperand(Op); 1522 operand = (inst & 0x060) >> 5; 1523 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1524 break; 1525 case Hexagon::V4_SA1_combinerz: 1526 case Hexagon::V4_SA1_combinezr: 1527 // Rdd 2-0, Rs 7-4 1528 operand = getDRegFromSubinstEncoding(inst & 0x7); 1529 Op = MCOperand::createReg(operand); 1530 MI->addOperand(Op); 1531 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1532 Op = MCOperand::createReg(operand); 1533 MI->addOperand(Op); 1534 break; 1535 case Hexagon::V4_SS1_storeb_io: 1536 // Rs 7-4, u 11-8, Rt 3-0 1537 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1538 Op = MCOperand::createReg(operand); 1539 MI->addOperand(Op); 1540 operand = (inst & 0xf00) >> 8; 1541 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1542 operand = getRegFromSubinstEncoding(inst & 0xf); 1543 Op = MCOperand::createReg(operand); 1544 MI->addOperand(Op); 1545 break; 1546 case Hexagon::V4_SS1_storew_io: 1547 // Rs 7-4, u 11-8{4_2}, Rt 3-0 1548 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1549 Op = MCOperand::createReg(operand); 1550 MI->addOperand(Op); 1551 operand = ((inst & 0xf00) >> 8) << 2; 1552 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1553 operand = getRegFromSubinstEncoding(inst & 0xf); 1554 Op = MCOperand::createReg(operand); 1555 MI->addOperand(Op); 1556 break; 1557 case Hexagon::V4_SS2_storebi0: 1558 case Hexagon::V4_SS2_storebi1: 1559 // Rs 7-4, u 3-0 1560 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1561 Op = MCOperand::createReg(operand); 1562 MI->addOperand(Op); 1563 operand = inst & 0xf; 1564 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1565 break; 1566 case Hexagon::V4_SS2_storewi0: 1567 case Hexagon::V4_SS2_storewi1: 1568 // Rs 7-4, u 3-0{4_2} 1569 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1570 Op = MCOperand::createReg(operand); 1571 MI->addOperand(Op); 1572 operand = (inst & 0xf) << 2; 1573 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1574 break; 1575 case Hexagon::V4_SS2_stored_sp: 1576 // s 8-3{6_3}, Rtt 2-0 1577 operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3); 1578 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1579 operand = getDRegFromSubinstEncoding(inst & 0x7); 1580 Op = MCOperand::createReg(operand); 1581 MI->addOperand(Op); 1582 break; 1583 case Hexagon::V4_SS2_storeh_io: 1584 // Rs 7-4, u 10-8{3_1}, Rt 3-0 1585 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); 1586 Op = MCOperand::createReg(operand); 1587 MI->addOperand(Op); 1588 operand = ((inst & 0x700) >> 8) << 1; 1589 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1590 operand = getRegFromSubinstEncoding(inst & 0xf); 1591 Op = MCOperand::createReg(operand); 1592 MI->addOperand(Op); 1593 break; 1594 case Hexagon::V4_SS2_storew_sp: 1595 // u 8-4{5_2}, Rd 3-0 1596 operand = ((inst & 0x1f0) >> 4) << 2; 1597 HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); 1598 operand = getRegFromSubinstEncoding(inst & 0xf); 1599 Op = MCOperand::createReg(operand); 1600 MI->addOperand(Op); 1601 break; 1602 default: 1603 // don't crash with an invalid subinstruction 1604 // llvm_unreachable("Invalid subinstruction in duplex instruction"); 1605 break; 1606 } 1607 } 1608