1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "hexagon-disassembler" 11 12 #include "Hexagon.h" 13 #include "MCTargetDesc/HexagonBaseInfo.h" 14 #include "MCTargetDesc/HexagonMCChecker.h" 15 #include "MCTargetDesc/HexagonMCTargetDesc.h" 16 #include "MCTargetDesc/HexagonMCInstrInfo.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCFixedLenDisassembler.h" 23 #include "llvm/MC/MCInst.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include <cassert> 31 #include <cstddef> 32 #include <cstdint> 33 #include <memory> 34 35 using namespace llvm; 36 using namespace Hexagon; 37 38 typedef MCDisassembler::DecodeStatus DecodeStatus; 39 40 namespace { 41 42 /// \brief Hexagon disassembler for all Hexagon platforms. 43 class HexagonDisassembler : public MCDisassembler { 44 public: 45 std::unique_ptr<MCInstrInfo const> const MCII; 46 std::unique_ptr<MCInst *> CurrentBundle; 47 48 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 49 MCInstrInfo const *MCII) 50 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} 51 52 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 53 ArrayRef<uint8_t> Bytes, uint64_t Address, 54 raw_ostream &VStream, raw_ostream &CStream, 55 bool &Complete) const; 56 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 57 ArrayRef<uint8_t> Bytes, uint64_t Address, 58 raw_ostream &VStream, 59 raw_ostream &CStream) const override; 60 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; 61 }; 62 63 namespace { 64 uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, 65 int64_t Value) { 66 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 67 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 68 if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 69 return Value; 70 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 71 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 72 int64_t Bits; 73 bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); 74 assert(Success); (void)Success; 75 uint32_t Upper26 = static_cast<uint32_t>(Bits); 76 uint32_t Operand = Upper26 | Lower6; 77 return Operand; 78 } 79 HexagonDisassembler const &disassembler(void const *Decoder) { 80 return *static_cast<HexagonDisassembler const *>(Decoder); 81 } 82 template <size_t T> 83 void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 84 HexagonDisassembler const &Disassembler = disassembler(Decoder); 85 int64_t FullValue = 86 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, 87 SignExtend64<T>(tmp)); 88 int64_t Extended = SignExtend64<32>(FullValue); 89 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 90 } 91 } 92 } // end anonymous namespace 93 94 // Forward declare these because the auto-generated code will reference them. 95 // Definitions are further down. 96 97 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 98 uint64_t Address, 99 const void *Decoder); 100 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 101 unsigned RegNo, 102 uint64_t Address, 103 const void *Decoder); 104 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 108 uint64_t Address, 109 const void *Decoder); 110 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t Address, 112 const void *Decoder); 113 static DecodeStatus 114 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 117 uint64_t Address, 118 const void *Decoder); 119 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 132 uint64_t Address, 133 const void *Decoder); 134 135 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 138 uint64_t /*Address*/, const void *Decoder); 139 static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 140 const void *Decoder); 141 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 142 const void *Decoder); 143 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 144 const void *Decoder); 145 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 146 const void *Decoder); 147 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 152 const void *Decoder); 153 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 154 const void *Decoder); 155 156 #include "HexagonDepDecoders.h" 157 #include "HexagonGenDisassemblerTables.inc" 158 159 static MCDisassembler *createHexagonDisassembler(const Target &T, 160 const MCSubtargetInfo &STI, 161 MCContext &Ctx) { 162 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 163 } 164 165 extern "C" void LLVMInitializeHexagonDisassembler() { 166 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 167 createHexagonDisassembler); 168 } 169 170 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 171 ArrayRef<uint8_t> Bytes, 172 uint64_t Address, 173 raw_ostream &os, 174 raw_ostream &cs) const { 175 DecodeStatus Result = DecodeStatus::Success; 176 bool Complete = false; 177 Size = 0; 178 179 *CurrentBundle = &MI; 180 MI = HexagonMCInstrInfo::createBundle(); 181 while (Result == Success && !Complete) { 182 if (Bytes.size() < HEXAGON_INSTR_SIZE) 183 return MCDisassembler::Fail; 184 MCInst *Inst = new (getContext()) MCInst; 185 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete); 186 MI.addOperand(MCOperand::createInst(Inst)); 187 Size += HEXAGON_INSTR_SIZE; 188 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 189 } 190 if (Result == MCDisassembler::Fail) 191 return Result; 192 if (Size > HEXAGON_MAX_PACKET_SIZE) 193 return MCDisassembler::Fail; 194 HexagonMCChecker Checker(*MCII, STI, MI, MI, *getContext().getRegisterInfo()); 195 if (!Checker.check()) 196 return MCDisassembler::Fail; 197 return MCDisassembler::Success; 198 } 199 200 namespace { 201 void adjustDuplex(MCInst &MI, MCContext &Context) { 202 switch (MI.getOpcode()) { 203 case Hexagon::SA1_setin1: 204 MI.insert(MI.begin() + 1, 205 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 206 break; 207 case Hexagon::SA1_dec: 208 MI.insert(MI.begin() + 2, 209 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 210 break; 211 default: 212 break; 213 } 214 } 215 } 216 217 DecodeStatus HexagonDisassembler::getSingleInstruction( 218 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, 219 raw_ostream &os, raw_ostream &cs, bool &Complete) const { 220 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 221 222 uint32_t Instruction = support::endian::read32le(Bytes.data()); 223 224 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 225 if ((Instruction & HexagonII::INST_PARSE_MASK) == 226 HexagonII::INST_PARSE_LOOP_END) { 227 if (BundleSize == 0) 228 HexagonMCInstrInfo::setInnerLoop(MCB); 229 else if (BundleSize == 1) 230 HexagonMCInstrInfo::setOuterLoop(MCB); 231 else 232 return DecodeStatus::Fail; 233 } 234 235 MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( 236 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 237 238 DecodeStatus Result = DecodeStatus::Fail; 239 if ((Instruction & HexagonII::INST_PARSE_MASK) == 240 HexagonII::INST_PARSE_DUPLEX) { 241 unsigned duplexIClass; 242 uint8_t const *DecodeLow, *DecodeHigh; 243 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 244 switch (duplexIClass) { 245 default: 246 return MCDisassembler::Fail; 247 case 0: 248 DecodeLow = DecoderTableSUBINSN_L132; 249 DecodeHigh = DecoderTableSUBINSN_L132; 250 break; 251 case 1: 252 DecodeLow = DecoderTableSUBINSN_L232; 253 DecodeHigh = DecoderTableSUBINSN_L132; 254 break; 255 case 2: 256 DecodeLow = DecoderTableSUBINSN_L232; 257 DecodeHigh = DecoderTableSUBINSN_L232; 258 break; 259 case 3: 260 DecodeLow = DecoderTableSUBINSN_A32; 261 DecodeHigh = DecoderTableSUBINSN_A32; 262 break; 263 case 4: 264 DecodeLow = DecoderTableSUBINSN_L132; 265 DecodeHigh = DecoderTableSUBINSN_A32; 266 break; 267 case 5: 268 DecodeLow = DecoderTableSUBINSN_L232; 269 DecodeHigh = DecoderTableSUBINSN_A32; 270 break; 271 case 6: 272 DecodeLow = DecoderTableSUBINSN_S132; 273 DecodeHigh = DecoderTableSUBINSN_A32; 274 break; 275 case 7: 276 DecodeLow = DecoderTableSUBINSN_S232; 277 DecodeHigh = DecoderTableSUBINSN_A32; 278 break; 279 case 8: 280 DecodeLow = DecoderTableSUBINSN_S132; 281 DecodeHigh = DecoderTableSUBINSN_L132; 282 break; 283 case 9: 284 DecodeLow = DecoderTableSUBINSN_S132; 285 DecodeHigh = DecoderTableSUBINSN_L232; 286 break; 287 case 10: 288 DecodeLow = DecoderTableSUBINSN_S132; 289 DecodeHigh = DecoderTableSUBINSN_S132; 290 break; 291 case 11: 292 DecodeLow = DecoderTableSUBINSN_S232; 293 DecodeHigh = DecoderTableSUBINSN_S132; 294 break; 295 case 12: 296 DecodeLow = DecoderTableSUBINSN_S232; 297 DecodeHigh = DecoderTableSUBINSN_L132; 298 break; 299 case 13: 300 DecodeLow = DecoderTableSUBINSN_S232; 301 DecodeHigh = DecoderTableSUBINSN_L232; 302 break; 303 case 14: 304 DecodeLow = DecoderTableSUBINSN_S232; 305 DecodeHigh = DecoderTableSUBINSN_S232; 306 break; 307 } 308 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); 309 MCInst *MILow = new (getContext()) MCInst; 310 MCInst *MIHigh = new (getContext()) MCInst; 311 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, 312 this, STI); 313 if (Result != DecodeStatus::Success) 314 return DecodeStatus::Fail; 315 adjustDuplex(*MILow, getContext()); 316 Result = decodeInstruction( 317 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); 318 if (Result != DecodeStatus::Success) 319 return DecodeStatus::Fail; 320 adjustDuplex(*MIHigh, getContext()); 321 MCOperand OPLow = MCOperand::createInst(MILow); 322 MCOperand OPHigh = MCOperand::createInst(MIHigh); 323 MI.addOperand(OPLow); 324 MI.addOperand(OPHigh); 325 Complete = true; 326 } else { 327 if ((Instruction & HexagonII::INST_PARSE_MASK) == 328 HexagonII::INST_PARSE_PACKET_END) 329 Complete = true; 330 331 if (Extender != nullptr) 332 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, 333 Address, this, STI); 334 335 if (Result != MCDisassembler::Success) 336 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, 337 STI); 338 339 if (Result != MCDisassembler::Success && 340 STI.getFeatureBits()[Hexagon::ExtensionHVX]) 341 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, 342 Address, this, STI); 343 344 } 345 346 switch (MI.getOpcode()) { 347 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 348 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 349 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 350 case Hexagon::J4_cmpeqn1_fp0_jump_t: 351 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 352 case Hexagon::J4_cmpeqn1_fp1_jump_t: 353 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 354 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 355 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 356 case Hexagon::J4_cmpeqn1_tp0_jump_t: 357 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 358 case Hexagon::J4_cmpeqn1_tp1_jump_t: 359 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 360 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 361 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 362 case Hexagon::J4_cmpgtn1_fp0_jump_t: 363 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 364 case Hexagon::J4_cmpgtn1_fp1_jump_t: 365 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 366 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 367 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 368 case Hexagon::J4_cmpgtn1_tp0_jump_t: 369 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 370 case Hexagon::J4_cmpgtn1_tp1_jump_t: 371 MI.insert(MI.begin() + 1, 372 MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 373 break; 374 default: 375 break; 376 } 377 378 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 379 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 380 MCOperand &MCO = MI.getOperand(OpIndex); 381 assert(MCO.isReg() && "New value consumers must be registers"); 382 unsigned Register = 383 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 384 if ((Register & 0x6) == 0) 385 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 386 return MCDisassembler::Fail; 387 unsigned Lookback = (Register & 0x6) >> 1; 388 unsigned Offset = 1; 389 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 390 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 391 auto i = Instructions.end() - 1; 392 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 393 if (i == n) 394 // Couldn't find producer 395 return MCDisassembler::Fail; 396 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) 397 // Skip scalars when calculating distances for vectors 398 ++Lookback; 399 if (HexagonMCInstrInfo::isImmext(*i->getInst())) 400 ++Lookback; 401 if (Offset == Lookback) 402 break; 403 } 404 auto const &Inst = *i->getInst(); 405 bool SubregBit = (Register & 0x1) != 0; 406 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 407 // If subreg bit is set we're selecting the second produced newvalue 408 unsigned Producer = 409 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 410 assert(Producer != Hexagon::NoRegister); 411 MCO.setReg(Producer); 412 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 413 unsigned Producer = 414 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 415 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 416 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; 417 else if (SubregBit) 418 // Hexagon PRM 10.11 New-value operands 419 // Nt[0] is reserved and should always be encoded as zero. 420 return MCDisassembler::Fail; 421 assert(Producer != Hexagon::NoRegister); 422 MCO.setReg(Producer); 423 } else 424 return MCDisassembler::Fail; 425 } 426 427 if (Extender != nullptr) { 428 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) 429 ? *MI.getOperand(1).getInst() 430 : MI; 431 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 432 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 433 return MCDisassembler::Fail; 434 } 435 return Result; 436 } 437 438 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 439 ArrayRef<MCPhysReg> Table) { 440 if (RegNo < Table.size()) { 441 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 442 return MCDisassembler::Success; 443 } 444 445 return MCDisassembler::Fail; 446 } 447 448 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 449 uint64_t Address, 450 const void *Decoder) { 451 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 452 } 453 454 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 455 uint64_t Address, 456 const void *Decoder) { 457 static const MCPhysReg IntRegDecoderTable[] = { 458 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 459 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 460 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 461 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 462 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 463 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 464 Hexagon::R30, Hexagon::R31}; 465 466 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 467 } 468 469 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 470 unsigned RegNo, 471 uint64_t Address, 472 const void *Decoder) { 473 static const MCPhysReg GeneralSubRegDecoderTable[] = { 474 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 475 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, 476 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 477 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 478 }; 479 480 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); 481 } 482 483 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 484 uint64_t /*Address*/, 485 const void *Decoder) { 486 static const MCPhysReg VecRegDecoderTable[] = { 487 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 488 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 489 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 490 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 491 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 492 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 493 Hexagon::V30, Hexagon::V31}; 494 495 return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable); 496 } 497 498 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 499 uint64_t /*Address*/, 500 const void *Decoder) { 501 static const MCPhysReg DoubleRegDecoderTable[] = { 502 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 503 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 504 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 505 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 506 507 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 508 } 509 510 static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( 511 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { 512 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { 513 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 514 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; 515 516 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); 517 } 518 519 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 520 uint64_t /*Address*/, 521 const void *Decoder) { 522 static const MCPhysReg VecDblRegDecoderTable[] = { 523 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, 524 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, 525 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, 526 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15}; 527 528 return (DecodeRegisterClass(Inst, RegNo >> 1, VecDblRegDecoderTable)); 529 } 530 531 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 532 uint64_t /*Address*/, 533 const void *Decoder) { 534 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 535 Hexagon::P2, Hexagon::P3}; 536 537 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 538 } 539 540 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 541 uint64_t /*Address*/, 542 const void *Decoder) { 543 static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 544 Hexagon::Q2, Hexagon::Q3}; 545 546 return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable); 547 } 548 549 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 550 uint64_t /*Address*/, 551 const void *Decoder) { 552 using namespace Hexagon; 553 static const MCPhysReg CtrlRegDecoderTable[] = { 554 /* 0 */ SA0, LC0, SA1, LC1, 555 /* 4 */ P3_0, C5, C6, C7, 556 /* 8 */ USR, PC, UGP, GP, 557 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, 558 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, 559 /* 20 */ 0, 0, 0, 0, 560 /* 24 */ 0, 0, 0, 0, 561 /* 28 */ 0, 0, UTIMERLO, UTIMERHI 562 }; 563 564 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 565 return MCDisassembler::Fail; 566 567 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 568 if (CtrlRegDecoderTable[RegNo] == NoRegister) 569 return MCDisassembler::Fail; 570 571 unsigned Register = CtrlRegDecoderTable[RegNo]; 572 Inst.addOperand(MCOperand::createReg(Register)); 573 return MCDisassembler::Success; 574 } 575 576 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 577 uint64_t /*Address*/, 578 const void *Decoder) { 579 using namespace Hexagon; 580 static const MCPhysReg CtrlReg64DecoderTable[] = { 581 /* 0 */ C1_0, 0, C3_2, 0, 582 /* 4 */ C5_4, 0, C7_6, 0, 583 /* 8 */ C9_8, 0, C11_10, 0, 584 /* 12 */ CS, 0, UPCYCLE, 0, 585 /* 16 */ C17_16, 0, PKTCOUNT, 0, 586 /* 20 */ 0, 0, 0, 0, 587 /* 24 */ 0, 0, 0, 0, 588 /* 28 */ 0, 0, UTIMER, 0 589 }; 590 591 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 592 return MCDisassembler::Fail; 593 594 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 595 if (CtrlReg64DecoderTable[RegNo] == NoRegister) 596 return MCDisassembler::Fail; 597 598 unsigned Register = CtrlReg64DecoderTable[RegNo]; 599 Inst.addOperand(MCOperand::createReg(Register)); 600 return MCDisassembler::Success; 601 } 602 603 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 604 uint64_t /*Address*/, 605 const void *Decoder) { 606 unsigned Register = 0; 607 switch (RegNo) { 608 case 0: 609 Register = Hexagon::M0; 610 break; 611 case 1: 612 Register = Hexagon::M1; 613 break; 614 default: 615 return MCDisassembler::Fail; 616 } 617 Inst.addOperand(MCOperand::createReg(Register)); 618 return MCDisassembler::Success; 619 } 620 621 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 622 uint64_t /*Address*/, 623 const void *Decoder) { 624 HexagonDisassembler const &Disassembler = disassembler(Decoder); 625 int64_t FullValue = 626 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, tmp); 627 assert(FullValue >= 0 && "Negative in unsigned decoder"); 628 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 629 return MCDisassembler::Success; 630 } 631 632 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 633 uint64_t /*Address*/, const void *Decoder) { 634 HexagonDisassembler const &Disassembler = disassembler(Decoder); 635 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 636 tmp = SignExtend64(tmp, Bits); 637 signedDecoder<32>(MI, tmp, Decoder); 638 return MCDisassembler::Success; 639 } 640 641 // custom decoder for various jump/call immediates 642 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 643 const void *Decoder) { 644 HexagonDisassembler const &Disassembler = disassembler(Decoder); 645 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 646 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 647 if (Bits == 0) 648 Bits = 15; 649 uint32_t FullValue = 650 fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, 651 SignExtend64(tmp, Bits)); 652 int64_t Extended = SignExtend64<32>(FullValue) + Address; 653 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) 654 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 655 return MCDisassembler::Success; 656 } 657 658 659