1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #define DEBUG_TYPE "mcasmparser"
11 
12 #include "Hexagon.h"
13 #include "HexagonRegisterInfo.h"
14 #include "HexagonTargetStreamer.h"
15 #include "MCTargetDesc/HexagonBaseInfo.h"
16 #include "MCTargetDesc/HexagonMCAsmInfo.h"
17 #include "MCTargetDesc/HexagonMCChecker.h"
18 #include "MCTargetDesc/HexagonMCELFStreamer.h"
19 #include "MCTargetDesc/HexagonMCExpr.h"
20 #include "MCTargetDesc/HexagonMCShuffler.h"
21 #include "MCTargetDesc/HexagonMCTargetDesc.h"
22 #include "MCTargetDesc/HexagonShuffler.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCELFStreamer.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCParser/MCAsmLexer.h"
31 #include "llvm/MC/MCParser/MCAsmParser.h"
32 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
33 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/MC/MCValue.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ELF.h"
41 #include "llvm/Support/Format.h"
42 #include "llvm/Support/MemoryBuffer.h"
43 #include "llvm/Support/SourceMgr.h"
44 #include "llvm/Support/TargetRegistry.h"
45 #include "llvm/Support/raw_ostream.h"
46 
47 using namespace llvm;
48 
49 static cl::opt<bool> EnableFutureRegs("mfuture-regs",
50                                       cl::desc("Enable future registers"));
51 
52 static cl::opt<bool> WarnMissingParenthesis("mwarn-missing-parenthesis",
53 cl::desc("Warn for missing parenthesis around predicate registers"),
54 cl::init(true));
55 static cl::opt<bool> ErrorMissingParenthesis("merror-missing-parenthesis",
56 cl::desc("Error for missing parenthesis around predicate registers"),
57 cl::init(false));
58 static cl::opt<bool> WarnSignedMismatch("mwarn-sign-mismatch",
59 cl::desc("Warn for mismatching a signed and unsigned value"),
60 cl::init(true));
61 static cl::opt<bool> WarnNoncontigiousRegister("mwarn-noncontigious-register",
62 cl::desc("Warn for register names that arent contigious"),
63 cl::init(true));
64 static cl::opt<bool> ErrorNoncontigiousRegister("merror-noncontigious-register",
65 cl::desc("Error for register names that aren't contigious"),
66 cl::init(false));
67 
68 
69 namespace {
70 struct HexagonOperand;
71 
72 class HexagonAsmParser : public MCTargetAsmParser {
73 
74   HexagonTargetStreamer &getTargetStreamer() {
75     MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
76     return static_cast<HexagonTargetStreamer &>(TS);
77   }
78 
79   MCAsmParser &Parser;
80   MCAssembler *Assembler;
81   MCInstrInfo const &MCII;
82   MCInst MCB;
83   bool InBrackets;
84 
85   MCAsmParser &getParser() const { return Parser; }
86   MCAssembler *getAssembler() const { return Assembler; }
87   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
88 
89   bool equalIsAsmAssignment() override { return false; }
90   bool isLabel(AsmToken &Token) override;
91 
92   void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
93   bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
94   bool ParseDirectiveFalign(unsigned Size, SMLoc L);
95 
96   virtual bool ParseRegister(unsigned &RegNo,
97                              SMLoc &StartLoc,
98                              SMLoc &EndLoc) override;
99   bool ParseDirectiveSubsection(SMLoc L);
100   bool ParseDirectiveValue(unsigned Size, SMLoc L);
101   bool ParseDirectiveComm(bool IsLocal, SMLoc L);
102   bool RegisterMatchesArch(unsigned MatchNum) const;
103 
104   bool matchBundleOptions();
105   bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);
106   bool finishBundle(SMLoc IDLoc, MCStreamer &Out);
107   void canonicalizeImmediates(MCInst &MCI);
108   bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
109                            OperandVector &InstOperands, uint64_t &ErrorInfo,
110                            bool MatchingInlineAsm);
111 
112   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
113                                OperandVector &Operands, MCStreamer &Out,
114                                uint64_t &ErrorInfo, bool MatchingInlineAsm) override;
115 
116   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override;
117   bool OutOfRange(SMLoc IDLoc, long long Val, long long Max);
118   int processInstruction(MCInst &Inst, OperandVector const &Operands,
119                          SMLoc IDLoc);
120 
121   // Check if we have an assembler and, if so, set the ELF e_header flags.
122   void chksetELFHeaderEFlags(unsigned flags) {
123     if (getAssembler())
124       getAssembler()->setELFHeaderEFlags(flags);
125   }
126 
127   unsigned matchRegister(StringRef Name);
128 
129 /// @name Auto-generated Match Functions
130 /// {
131 
132 #define GET_ASSEMBLER_HEADER
133 #include "HexagonGenAsmMatcher.inc"
134 
135   /// }
136 
137 public:
138   HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
139                    const MCInstrInfo &MII, const MCTargetOptions &Options)
140     : MCTargetAsmParser(Options, _STI), Parser(_Parser),
141       MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
142     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
143 
144   MCAsmParserExtension::Initialize(_Parser);
145 
146   Assembler = nullptr;
147   // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
148   if (!Parser.getStreamer().hasRawTextSupport()) {
149     MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
150     Assembler = &MES->getAssembler();
151   }
152   }
153 
154   bool splitIdentifier(OperandVector &Operands);
155   bool parseOperand(OperandVector &Operands);
156   bool parseInstruction(OperandVector &Operands);
157   bool implicitExpressionLocation(OperandVector &Operands);
158   bool parseExpressionOrOperand(OperandVector &Operands);
159   bool parseExpression(MCExpr const *& Expr);
160   virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
161                                 SMLoc NameLoc, OperandVector &Operands) override
162   {
163     llvm_unreachable("Unimplemented");
164   }
165   virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
166                                 AsmToken ID, OperandVector &Operands) override;
167 
168   virtual bool ParseDirective(AsmToken DirectiveID) override;
169 };
170 
171 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
172 /// instruction.
173 struct HexagonOperand : public MCParsedAsmOperand {
174   enum KindTy { Token, Immediate, Register } Kind;
175 
176   SMLoc StartLoc, EndLoc;
177 
178   struct TokTy {
179     const char *Data;
180     unsigned Length;
181   };
182 
183   struct RegTy {
184     unsigned RegNum;
185   };
186 
187   struct ImmTy {
188     const MCExpr *Val;
189   };
190 
191   struct InstTy {
192     OperandVector *SubInsts;
193   };
194 
195   union {
196     struct TokTy Tok;
197     struct RegTy Reg;
198     struct ImmTy Imm;
199   };
200 
201   HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
202 
203 public:
204   HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() {
205     Kind = o.Kind;
206     StartLoc = o.StartLoc;
207     EndLoc = o.EndLoc;
208     switch (Kind) {
209     case Register:
210       Reg = o.Reg;
211       break;
212     case Immediate:
213       Imm = o.Imm;
214       break;
215     case Token:
216       Tok = o.Tok;
217       break;
218     }
219   }
220 
221   /// getStartLoc - Get the location of the first token of this operand.
222   SMLoc getStartLoc() const { return StartLoc; }
223 
224   /// getEndLoc - Get the location of the last token of this operand.
225   SMLoc getEndLoc() const { return EndLoc; }
226 
227   unsigned getReg() const {
228     assert(Kind == Register && "Invalid access!");
229     return Reg.RegNum;
230   }
231 
232   const MCExpr *getImm() const {
233     assert(Kind == Immediate && "Invalid access!");
234     return Imm.Val;
235   }
236 
237   bool isToken() const { return Kind == Token; }
238   bool isImm() const { return Kind == Immediate; }
239   bool isMem() const { llvm_unreachable("No isMem"); }
240   bool isReg() const { return Kind == Register; }
241 
242   bool CheckImmRange(int immBits, int zeroBits, bool isSigned,
243                      bool isRelocatable, bool Extendable) const {
244     if (Kind == Immediate) {
245       const MCExpr *myMCExpr = &HexagonMCInstrInfo::getExpr(*getImm());
246       if (HexagonMCInstrInfo::mustExtend(*Imm.Val) && !Extendable)
247         return false;
248       int64_t Res;
249       if (myMCExpr->evaluateAsAbsolute(Res)) {
250         int bits = immBits + zeroBits;
251         // Field bit range is zerobits + bits
252         // zeroBits must be 0
253         if (Res & ((1 << zeroBits) - 1))
254           return false;
255         if (isSigned) {
256           if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1)))
257             return true;
258         } else {
259           if (bits == 64)
260             return true;
261           if (Res >= 0)
262             return ((uint64_t)Res < (uint64_t)(1ULL << bits)) ? true : false;
263           else {
264             const int64_t high_bit_set = 1ULL << 63;
265             const uint64_t mask = (high_bit_set >> (63 - bits));
266             return (((uint64_t)Res & mask) == mask) ? true : false;
267           }
268         }
269       } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable)
270         return true;
271       else if (myMCExpr->getKind() == MCExpr::Binary ||
272                myMCExpr->getKind() == MCExpr::Unary)
273         return true;
274     }
275     return false;
276   }
277 
278   bool isf32Ext() const { return false; }
279   bool iss32_0Imm() const { return CheckImmRange(32, 0, true, true, false); }
280   bool iss23_2Imm() const { return CheckImmRange(23, 2, true, true, false); }
281   bool iss8_0Imm() const { return CheckImmRange(8, 0, true, false, false); }
282   bool iss8_0Imm64() const { return CheckImmRange(8, 0, true, true, false); }
283   bool iss7_0Imm() const { return CheckImmRange(7, 0, true, false, false); }
284   bool iss6_0Imm() const { return CheckImmRange(6, 0, true, false, false); }
285   bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); }
286   bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
287   bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
288   bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
289   bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); }
290   bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); }
291   bool iss3_0Imm() const { return CheckImmRange(3, 0, true, false, false); }
292 
293   bool isu64_0Imm() const { return CheckImmRange(64, 0, false, true, true); }
294   bool isu32_0Imm() const { return CheckImmRange(32, 0, false, true, false); }
295   bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); }
296   bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); }
297   bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); }
298   bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); }
299   bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); }
300   bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); }
301   bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); }
302   bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); }
303   bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); }
304   bool isu10_0Imm() const { return CheckImmRange(10, 0, false, false, false); }
305   bool isu9_0Imm() const { return CheckImmRange(9, 0, false, false, false); }
306   bool isu8_0Imm() const { return CheckImmRange(8, 0, false, false, false); }
307   bool isu7_0Imm() const { return CheckImmRange(7, 0, false, false, false); }
308   bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
309   bool isu5_0Imm() const { return CheckImmRange(5, 0, false, false, false); }
310   bool isu4_0Imm() const { return CheckImmRange(4, 0, false, false, false); }
311   bool isu3_0Imm() const { return CheckImmRange(3, 0, false, false, false); }
312   bool isu2_0Imm() const { return CheckImmRange(2, 0, false, false, false); }
313   bool isu1_0Imm() const { return CheckImmRange(1, 0, false, false, false); }
314 
315   bool ism6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
316   bool isn8_0Imm() const { return CheckImmRange(8, 0, false, false, false); }
317   bool isn1Const() const {
318     if (!isImm())
319       return false;
320     int64_t Value;
321     if (!getImm()->evaluateAsAbsolute(Value))
322       return false;
323     return Value == -1;
324   }
325 
326   bool iss16_0Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); }
327   bool iss12_0Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); }
328   bool iss10_0Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); }
329   bool iss9_0Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); }
330   bool iss8_0Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); }
331   bool iss7_0Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); }
332   bool iss6_0Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); }
333   bool iss11_0Ext() const {
334     return CheckImmRange(11 + 26, 0, true, true, true);
335   }
336   bool iss11_1Ext() const {
337     return CheckImmRange(11 + 26, 1, true, true, true);
338   }
339   bool iss11_2Ext() const {
340     return CheckImmRange(11 + 26, 2, true, true, true);
341   }
342   bool iss11_3Ext() const {
343     return CheckImmRange(11 + 26, 3, true, true, true);
344   }
345 
346   bool isu7_0Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); }
347   bool isu8_0Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); }
348   bool isu9_0Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); }
349   bool isu10_0Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); }
350   bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
351   bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); }
352   bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); }
353   bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); }
354   bool isu32_0MustExt() const { return isImm(); }
355 
356   void addRegOperands(MCInst &Inst, unsigned N) const {
357     assert(N == 1 && "Invalid number of operands!");
358     Inst.addOperand(MCOperand::createReg(getReg()));
359   }
360 
361   void addImmOperands(MCInst &Inst, unsigned N) const {
362     assert(N == 1 && "Invalid number of operands!");
363     Inst.addOperand(MCOperand::createExpr(getImm()));
364   }
365 
366   void addSignedImmOperands(MCInst &Inst, unsigned N) const {
367     assert(N == 1 && "Invalid number of operands!");
368     HexagonMCExpr *Expr =
369         const_cast<HexagonMCExpr *>(cast<HexagonMCExpr>(getImm()));
370     int64_t Value;
371     if (!Expr->evaluateAsAbsolute(Value)) {
372       Inst.addOperand(MCOperand::createExpr(Expr));
373       return;
374     }
375     int64_t Extended = SignExtend64(Value, 32);
376     if ((Extended < 0) != (Value < 0))
377       Expr->setSignMismatch();
378     Inst.addOperand(MCOperand::createExpr(Expr));
379   }
380 
381   void addf32ExtOperands(MCInst &Inst, unsigned N) const {
382     addImmOperands(Inst, N);
383   }
384 
385   void adds32_0ImmOperands(MCInst &Inst, unsigned N) const {
386     addSignedImmOperands(Inst, N);
387   }
388   void adds23_2ImmOperands(MCInst &Inst, unsigned N) const {
389     addSignedImmOperands(Inst, N);
390   }
391   void adds8_0ImmOperands(MCInst &Inst, unsigned N) const {
392     addSignedImmOperands(Inst, N);
393   }
394   void adds8_0Imm64Operands(MCInst &Inst, unsigned N) const {
395     addSignedImmOperands(Inst, N);
396   }
397   void adds6_0ImmOperands(MCInst &Inst, unsigned N) const {
398     addSignedImmOperands(Inst, N);
399   }
400   void adds4_0ImmOperands(MCInst &Inst, unsigned N) const {
401     addSignedImmOperands(Inst, N);
402   }
403   void adds4_1ImmOperands(MCInst &Inst, unsigned N) const {
404     addSignedImmOperands(Inst, N);
405   }
406   void adds4_2ImmOperands(MCInst &Inst, unsigned N) const {
407     addSignedImmOperands(Inst, N);
408   }
409   void adds4_3ImmOperands(MCInst &Inst, unsigned N) const {
410     addSignedImmOperands(Inst, N);
411   }
412   void adds3_0ImmOperands(MCInst &Inst, unsigned N) const {
413     addSignedImmOperands(Inst, N);
414   }
415 
416   void addu64_0ImmOperands(MCInst &Inst, unsigned N) const {
417     addImmOperands(Inst, N);
418   }
419   void addu32_0ImmOperands(MCInst &Inst, unsigned N) const {
420     addImmOperands(Inst, N);
421   }
422   void addu26_6ImmOperands(MCInst &Inst, unsigned N) const {
423     addImmOperands(Inst, N);
424   }
425   void addu16_0ImmOperands(MCInst &Inst, unsigned N) const {
426     addImmOperands(Inst, N);
427   }
428   void addu16_1ImmOperands(MCInst &Inst, unsigned N) const {
429     addImmOperands(Inst, N);
430   }
431   void addu16_2ImmOperands(MCInst &Inst, unsigned N) const {
432     addImmOperands(Inst, N);
433   }
434   void addu16_3ImmOperands(MCInst &Inst, unsigned N) const {
435     addImmOperands(Inst, N);
436   }
437   void addu11_3ImmOperands(MCInst &Inst, unsigned N) const {
438     addImmOperands(Inst, N);
439   }
440   void addu10_0ImmOperands(MCInst &Inst, unsigned N) const {
441     addImmOperands(Inst, N);
442   }
443   void addu9_0ImmOperands(MCInst &Inst, unsigned N) const {
444     addImmOperands(Inst, N);
445   }
446   void addu8_0ImmOperands(MCInst &Inst, unsigned N) const {
447     addImmOperands(Inst, N);
448   }
449   void addu7_0ImmOperands(MCInst &Inst, unsigned N) const {
450     addImmOperands(Inst, N);
451   }
452   void addu6_0ImmOperands(MCInst &Inst, unsigned N) const {
453     addImmOperands(Inst, N);
454   }
455   void addu6_1ImmOperands(MCInst &Inst, unsigned N) const {
456     addImmOperands(Inst, N);
457   }
458   void addu6_2ImmOperands(MCInst &Inst, unsigned N) const {
459     addImmOperands(Inst, N);
460   }
461   void addu6_3ImmOperands(MCInst &Inst, unsigned N) const {
462     addImmOperands(Inst, N);
463   }
464   void addu5_0ImmOperands(MCInst &Inst, unsigned N) const {
465     addImmOperands(Inst, N);
466   }
467   void addu4_0ImmOperands(MCInst &Inst, unsigned N) const {
468     addImmOperands(Inst, N);
469   }
470   void addu3_0ImmOperands(MCInst &Inst, unsigned N) const {
471     addImmOperands(Inst, N);
472   }
473   void addu2_0ImmOperands(MCInst &Inst, unsigned N) const {
474     addImmOperands(Inst, N);
475   }
476   void addu1_0ImmOperands(MCInst &Inst, unsigned N) const {
477     addImmOperands(Inst, N);
478   }
479 
480   void addm6_0ImmOperands(MCInst &Inst, unsigned N) const {
481     addImmOperands(Inst, N);
482   }
483   void addn8_0ImmOperands(MCInst &Inst, unsigned N) const {
484     addImmOperands(Inst, N);
485   }
486 
487   void adds16_0ExtOperands(MCInst &Inst, unsigned N) const {
488     addSignedImmOperands(Inst, N);
489   }
490   void adds12_0ExtOperands(MCInst &Inst, unsigned N) const {
491     addSignedImmOperands(Inst, N);
492   }
493   void adds10_0ExtOperands(MCInst &Inst, unsigned N) const {
494     addSignedImmOperands(Inst, N);
495   }
496   void adds9_0ExtOperands(MCInst &Inst, unsigned N) const {
497     addSignedImmOperands(Inst, N);
498   }
499   void adds8_0ExtOperands(MCInst &Inst, unsigned N) const {
500     addSignedImmOperands(Inst, N);
501   }
502   void adds6_0ExtOperands(MCInst &Inst, unsigned N) const {
503     addSignedImmOperands(Inst, N);
504   }
505   void adds11_0ExtOperands(MCInst &Inst, unsigned N) const {
506     addSignedImmOperands(Inst, N);
507   }
508   void adds11_1ExtOperands(MCInst &Inst, unsigned N) const {
509     addSignedImmOperands(Inst, N);
510   }
511   void adds11_2ExtOperands(MCInst &Inst, unsigned N) const {
512     addSignedImmOperands(Inst, N);
513   }
514   void adds11_3ExtOperands(MCInst &Inst, unsigned N) const {
515     addSignedImmOperands(Inst, N);
516   }
517   void addn1ConstOperands(MCInst &Inst, unsigned N) const {
518     addImmOperands(Inst, N);
519   }
520 
521   void addu7_0ExtOperands(MCInst &Inst, unsigned N) const {
522     addImmOperands(Inst, N);
523   }
524   void addu8_0ExtOperands(MCInst &Inst, unsigned N) const {
525     addImmOperands(Inst, N);
526   }
527   void addu9_0ExtOperands(MCInst &Inst, unsigned N) const {
528     addImmOperands(Inst, N);
529   }
530   void addu10_0ExtOperands(MCInst &Inst, unsigned N) const {
531     addImmOperands(Inst, N);
532   }
533   void addu6_0ExtOperands(MCInst &Inst, unsigned N) const {
534     addImmOperands(Inst, N);
535   }
536   void addu6_1ExtOperands(MCInst &Inst, unsigned N) const {
537     addImmOperands(Inst, N);
538   }
539   void addu6_2ExtOperands(MCInst &Inst, unsigned N) const {
540     addImmOperands(Inst, N);
541   }
542   void addu6_3ExtOperands(MCInst &Inst, unsigned N) const {
543     addImmOperands(Inst, N);
544   }
545   void addu32_0MustExtOperands(MCInst &Inst, unsigned N) const {
546     addImmOperands(Inst, N);
547   }
548 
549   void adds4_6ImmOperands(MCInst &Inst, unsigned N) const {
550     assert(N == 1 && "Invalid number of operands!");
551     const MCConstantExpr *CE =
552         dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm()));
553     Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
554   }
555 
556   void adds3_6ImmOperands(MCInst &Inst, unsigned N) const {
557     assert(N == 1 && "Invalid number of operands!");
558     const MCConstantExpr *CE =
559         dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm()));
560     Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
561   }
562 
563   StringRef getToken() const {
564     assert(Kind == Token && "Invalid access!");
565     return StringRef(Tok.Data, Tok.Length);
566   }
567 
568   virtual void print(raw_ostream &OS) const;
569 
570   static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) {
571     HexagonOperand *Op = new HexagonOperand(Token);
572     Op->Tok.Data = Str.data();
573     Op->Tok.Length = Str.size();
574     Op->StartLoc = S;
575     Op->EndLoc = S;
576     return std::unique_ptr<HexagonOperand>(Op);
577   }
578 
579   static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S,
580                                                    SMLoc E) {
581     HexagonOperand *Op = new HexagonOperand(Register);
582     Op->Reg.RegNum = RegNum;
583     Op->StartLoc = S;
584     Op->EndLoc = E;
585     return std::unique_ptr<HexagonOperand>(Op);
586   }
587 
588   static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S,
589                                                    SMLoc E) {
590     HexagonOperand *Op = new HexagonOperand(Immediate);
591     Op->Imm.Val = Val;
592     Op->StartLoc = S;
593     Op->EndLoc = E;
594     return std::unique_ptr<HexagonOperand>(Op);
595   }
596 };
597 
598 } // end anonymous namespace.
599 
600 void HexagonOperand::print(raw_ostream &OS) const {
601   switch (Kind) {
602   case Immediate:
603     getImm()->print(OS, nullptr);
604     break;
605   case Register:
606     OS << "<register R";
607     OS << getReg() << ">";
608     break;
609   case Token:
610     OS << "'" << getToken() << "'";
611     break;
612   }
613 }
614 
615 bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
616   DEBUG(dbgs() << "Bundle:");
617   DEBUG(MCB.dump_pretty(dbgs()));
618   DEBUG(dbgs() << "--\n");
619 
620   // Check the bundle for errors.
621   const MCRegisterInfo *RI = getContext().getRegisterInfo();
622   HexagonMCChecker Check(MCII, getSTI(), MCB, MCB, *RI);
623 
624   bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(),
625                                                         getContext(), MCB,
626                                                         &Check);
627 
628   while (Check.getNextErrInfo() == true) {
629     unsigned Reg = Check.getErrRegister();
630     Twine R(RI->getName(Reg));
631 
632     uint64_t Err = Check.getError();
633     if (Err != HexagonMCErrInfo::CHECK_SUCCESS) {
634       if (HexagonMCErrInfo::CHECK_ERROR_BRANCHES & Err)
635         return Error(
636             IDLoc,
637             "unconditional branch cannot precede another branch in packet");
638 
639       if (HexagonMCErrInfo::CHECK_ERROR_NEWP & Err ||
640           HexagonMCErrInfo::CHECK_ERROR_NEWV & Err)
641         return Error(IDLoc, "register `" + R +
642                                 "' used with `.new' "
643                                 "but not validly modified in the same packet");
644 
645       if (HexagonMCErrInfo::CHECK_ERROR_REGISTERS & Err)
646         return Error(IDLoc, "register `" + R + "' modified more than once");
647 
648       if (HexagonMCErrInfo::CHECK_ERROR_READONLY & Err)
649         return Error(IDLoc, "cannot write to read-only register `" + R + "'");
650 
651       if (HexagonMCErrInfo::CHECK_ERROR_LOOP & Err)
652         return Error(IDLoc, "loop-setup and some branch instructions "
653                             "cannot be in the same packet");
654 
655       if (HexagonMCErrInfo::CHECK_ERROR_ENDLOOP & Err) {
656         Twine N(HexagonMCInstrInfo::isInnerLoop(MCB) ? '0' : '1');
657         return Error(IDLoc,
658                      "packet marked with `:endloop" + N + "' " +
659                          "cannot contain instructions that modify register " +
660                          "`" + R + "'");
661       }
662 
663       if (HexagonMCErrInfo::CHECK_ERROR_SOLO & Err)
664         return Error(
665             IDLoc,
666             "instruction cannot appear in packet with other instructions");
667 
668       if (HexagonMCErrInfo::CHECK_ERROR_NOSLOTS & Err)
669         return Error(IDLoc, "too many slots used in packet");
670 
671       if (Err & HexagonMCErrInfo::CHECK_ERROR_SHUFFLE) {
672         uint64_t Erm = Check.getShuffleError();
673 
674         if (HexagonShuffler::SHUFFLE_ERROR_INVALID == Erm)
675           return Error(IDLoc, "invalid instruction packet");
676         else if (HexagonShuffler::SHUFFLE_ERROR_STORES == Erm)
677           return Error(IDLoc, "invalid instruction packet: too many stores");
678         else if (HexagonShuffler::SHUFFLE_ERROR_LOADS == Erm)
679           return Error(IDLoc, "invalid instruction packet: too many loads");
680         else if (HexagonShuffler::SHUFFLE_ERROR_BRANCHES == Erm)
681           return Error(IDLoc, "too many branches in packet");
682         else if (HexagonShuffler::SHUFFLE_ERROR_NOSLOTS == Erm)
683           return Error(IDLoc, "invalid instruction packet: out of slots");
684         else if (HexagonShuffler::SHUFFLE_ERROR_SLOTS == Erm)
685           return Error(IDLoc, "invalid instruction packet: slot error");
686         else if (HexagonShuffler::SHUFFLE_ERROR_ERRATA2 == Erm)
687           return Error(IDLoc, "v60 packet violation");
688         else if (HexagonShuffler::SHUFFLE_ERROR_STORE_LOAD_CONFLICT == Erm)
689           return Error(IDLoc, "slot 0 instruction does not allow slot 1 store");
690         else
691           return Error(IDLoc, "unknown error in instruction packet");
692       }
693     }
694 
695     unsigned Warn = Check.getWarning();
696     if (Warn != HexagonMCErrInfo::CHECK_SUCCESS) {
697       if (HexagonMCErrInfo::CHECK_WARN_CURRENT & Warn)
698         Warning(IDLoc, "register `" + R + "' used with `.cur' "
699                                           "but not used in the same packet");
700       else if (HexagonMCErrInfo::CHECK_WARN_TEMPORARY & Warn)
701         Warning(IDLoc, "register `" + R + "' used with `.tmp' "
702                                           "but not used in the same packet");
703     }
704   }
705 
706   if (CheckOk) {
707     MCB.setLoc(IDLoc);
708     if (HexagonMCInstrInfo::bundleSize(MCB) == 0) {
709       assert(!HexagonMCInstrInfo::isInnerLoop(MCB));
710       assert(!HexagonMCInstrInfo::isOuterLoop(MCB));
711       // Empty packets are valid yet aren't emitted
712       return false;
713     }
714     Out.EmitInstruction(MCB, getSTI());
715   } else {
716     // If compounding and duplexing didn't reduce the size below
717     // 4 or less we have a packet that is too big.
718     if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {
719       Error(IDLoc, "invalid instruction packet: out of slots");
720       return true; // Error
721     }
722   }
723 
724   return false; // No error
725 }
726 
727 bool HexagonAsmParser::matchBundleOptions() {
728   MCAsmParser &Parser = getParser();
729   while (true) {
730     if (!Parser.getTok().is(AsmToken::Colon))
731       return false;
732     Lex();
733     StringRef Option = Parser.getTok().getString();
734     if (Option.compare_lower("endloop0") == 0)
735       HexagonMCInstrInfo::setInnerLoop(MCB);
736     else if (Option.compare_lower("endloop1") == 0)
737       HexagonMCInstrInfo::setOuterLoop(MCB);
738     else if (Option.compare_lower("mem_noshuf") == 0)
739       HexagonMCInstrInfo::setMemReorderDisabled(MCB);
740     else if (Option.compare_lower("mem_shuf") == 0)
741       HexagonMCInstrInfo::setMemStoreReorderEnabled(MCB);
742     else
743       return true;
744     Lex();
745   }
746 }
747 
748 // For instruction aliases, immediates are generated rather than
749 // MCConstantExpr.  Convert them for uniform MCExpr.
750 // Also check for signed/unsigned mismatches and warn
751 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
752   MCInst NewInst;
753   NewInst.setOpcode(MCI.getOpcode());
754   for (MCOperand &I : MCI)
755     if (I.isImm()) {
756       int64_t Value (I.getImm());
757       NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
758           MCConstantExpr::create(Value, getContext()), getContext())));
759     }
760     else {
761       if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() &&
762           WarnSignedMismatch)
763         Warning (MCI.getLoc(), "Signed/Unsigned mismatch");
764       NewInst.addOperand(I);
765     }
766   MCI = NewInst;
767 }
768 
769 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
770                                            OperandVector &InstOperands,
771                                            uint64_t &ErrorInfo,
772                                            bool MatchingInlineAsm) {
773   // Perform matching with tablegen asmmatcher generated function
774   int result =
775       MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);
776   if (result == Match_Success) {
777     MCI.setLoc(IDLoc);
778     canonicalizeImmediates(MCI);
779     result = processInstruction(MCI, InstOperands, IDLoc);
780 
781     DEBUG(dbgs() << "Insn:");
782     DEBUG(MCI.dump_pretty(dbgs()));
783     DEBUG(dbgs() << "\n\n");
784 
785     MCI.setLoc(IDLoc);
786   }
787 
788   // Create instruction operand for bundle instruction
789   //   Break this into a separate function Code here is less readable
790   //   Think about how to get an instruction error to report correctly.
791   //   SMLoc will return the "{"
792   switch (result) {
793   default:
794     break;
795   case Match_Success:
796     return false;
797   case Match_MissingFeature:
798     return Error(IDLoc, "invalid instruction");
799   case Match_MnemonicFail:
800     return Error(IDLoc, "unrecognized instruction");
801   case Match_InvalidOperand:
802     SMLoc ErrorLoc = IDLoc;
803     if (ErrorInfo != ~0U) {
804       if (ErrorInfo >= InstOperands.size())
805         return Error(IDLoc, "too few operands for instruction");
806 
807       ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get()))
808                      ->getStartLoc();
809       if (ErrorLoc == SMLoc())
810         ErrorLoc = IDLoc;
811     }
812     return Error(ErrorLoc, "invalid operand for instruction");
813   }
814   llvm_unreachable("Implement any new match types added!");
815 }
816 
817 bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
818                                                OperandVector &Operands,
819                                                MCStreamer &Out,
820                                                uint64_t &ErrorInfo,
821                                                bool MatchingInlineAsm) {
822   if (!InBrackets) {
823     MCB.clear();
824     MCB.addOperand(MCOperand::createImm(0));
825   }
826   HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]);
827   if (FirstOperand.isToken() && FirstOperand.getToken() == "{") {
828     assert(Operands.size() == 1 && "Brackets should be by themselves");
829     if (InBrackets) {
830       getParser().Error(IDLoc, "Already in a packet");
831       return true;
832     }
833     InBrackets = true;
834     return false;
835   }
836   if (FirstOperand.isToken() && FirstOperand.getToken() == "}") {
837     assert(Operands.size() == 1 && "Brackets should be by themselves");
838     if (!InBrackets) {
839       getParser().Error(IDLoc, "Not in a packet");
840       return true;
841     }
842     InBrackets = false;
843     if (matchBundleOptions())
844       return true;
845     return finishBundle(IDLoc, Out);
846   }
847   MCInst *SubInst = new (getParser().getContext()) MCInst;
848   if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
849                           MatchingInlineAsm))
850     return true;
851   HexagonMCInstrInfo::extendIfNeeded(
852       getParser().getContext(), MCII, MCB, *SubInst);
853   MCB.addOperand(MCOperand::createInst(SubInst));
854   if (!InBrackets)
855     return finishBundle(IDLoc, Out);
856   return false;
857 }
858 
859 /// ParseDirective parses the Hexagon specific directives
860 bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
861   StringRef IDVal = DirectiveID.getIdentifier();
862   if ((IDVal.lower() == ".word") || (IDVal.lower() == ".4byte"))
863     return ParseDirectiveValue(4, DirectiveID.getLoc());
864   if (IDVal.lower() == ".short" || IDVal.lower() == ".hword" ||
865       IDVal.lower() == ".half")
866     return ParseDirectiveValue(2, DirectiveID.getLoc());
867   if (IDVal.lower() == ".falign")
868     return ParseDirectiveFalign(256, DirectiveID.getLoc());
869   if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon"))
870     return ParseDirectiveComm(true, DirectiveID.getLoc());
871   if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common"))
872     return ParseDirectiveComm(false, DirectiveID.getLoc());
873   if (IDVal.lower() == ".subsection")
874     return ParseDirectiveSubsection(DirectiveID.getLoc());
875 
876   return true;
877 }
878 bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) {
879   const MCExpr *Subsection = 0;
880   int64_t Res;
881 
882   assert((getLexer().isNot(AsmToken::EndOfStatement)) &&
883          "Invalid subsection directive");
884   getParser().parseExpression(Subsection);
885 
886   if (!Subsection->evaluateAsAbsolute(Res))
887     return Error(L, "Cannot evaluate subsection number");
888 
889   if (getLexer().isNot(AsmToken::EndOfStatement))
890     return TokError("unexpected token in directive");
891 
892   // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the
893   // negative subsections together and in the same order but at the opposite
894   // end of the section.  Only legacy hexagon-gcc created assembly code
895   // used negative subsections.
896   if ((Res < 0) && (Res > -8193))
897     Subsection = HexagonMCExpr::create(
898         MCConstantExpr::create(8192 + Res, getContext()), getContext());
899 
900   getStreamer().SubSection(Subsection);
901   return false;
902 }
903 
904 ///  ::= .falign [expression]
905 bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) {
906 
907   int64_t MaxBytesToFill = 15;
908 
909   // if there is an argument
910   if (getLexer().isNot(AsmToken::EndOfStatement)) {
911     const MCExpr *Value;
912     SMLoc ExprLoc = L;
913 
914     // Make sure we have a number (false is returned if expression is a number)
915     if (getParser().parseExpression(Value) == false) {
916       // Make sure this is a number that is in range
917       const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value);
918       uint64_t IntValue = MCE->getValue();
919       if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue))
920         return Error(ExprLoc, "literal value out of range (256) for falign");
921       MaxBytesToFill = IntValue;
922       Lex();
923     } else {
924       return Error(ExprLoc, "not a valid expression for falign directive");
925     }
926   }
927 
928   getTargetStreamer().emitFAlign(16, MaxBytesToFill);
929   Lex();
930 
931   return false;
932 }
933 
934 ///  ::= .word [ expression (, expression)* ]
935 bool HexagonAsmParser::ParseDirectiveValue(unsigned Size, SMLoc L) {
936   if (getLexer().isNot(AsmToken::EndOfStatement)) {
937 
938     for (;;) {
939       const MCExpr *Value;
940       SMLoc ExprLoc = L;
941       if (getParser().parseExpression(Value))
942         return true;
943 
944       // Special case constant expressions to match code generator.
945       if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value)) {
946         assert(Size <= 8 && "Invalid size");
947         uint64_t IntValue = MCE->getValue();
948         if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
949           return Error(ExprLoc, "literal value out of range for directive");
950         getStreamer().EmitIntValue(IntValue, Size);
951       } else
952         getStreamer().EmitValue(Value, Size);
953 
954       if (getLexer().is(AsmToken::EndOfStatement))
955         break;
956 
957       // FIXME: Improve diagnostic.
958       if (getLexer().isNot(AsmToken::Comma))
959         return TokError("unexpected token in directive");
960       Lex();
961     }
962   }
963 
964   Lex();
965   return false;
966 }
967 
968 // This is largely a copy of AsmParser's ParseDirectiveComm extended to
969 // accept a 3rd argument, AccessAlignment which indicates the smallest
970 // memory access made to the symbol, expressed in bytes.  If no
971 // AccessAlignment is specified it defaults to the Alignment Value.
972 // Hexagon's .lcomm:
973 //   .lcomm Symbol, Length, Alignment, AccessAlignment
974 bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
975   // FIXME: need better way to detect if AsmStreamer (upstream removed
976   // getKind())
977   if (getStreamer().hasRawTextSupport())
978     return true; // Only object file output requires special treatment.
979 
980   StringRef Name;
981   if (getParser().parseIdentifier(Name))
982     return TokError("expected identifier in directive");
983   // Handle the identifier as the key symbol.
984   MCSymbol *Sym = getContext().getOrCreateSymbol(Name);
985 
986   if (getLexer().isNot(AsmToken::Comma))
987     return TokError("unexpected token in directive");
988   Lex();
989 
990   int64_t Size;
991   SMLoc SizeLoc = getLexer().getLoc();
992   if (getParser().parseAbsoluteExpression(Size))
993     return true;
994 
995   int64_t ByteAlignment = 1;
996   SMLoc ByteAlignmentLoc;
997   if (getLexer().is(AsmToken::Comma)) {
998     Lex();
999     ByteAlignmentLoc = getLexer().getLoc();
1000     if (getParser().parseAbsoluteExpression(ByteAlignment))
1001       return true;
1002     if (!isPowerOf2_64(ByteAlignment))
1003       return Error(ByteAlignmentLoc, "alignment must be a power of 2");
1004   }
1005 
1006   int64_t AccessAlignment = 0;
1007   if (getLexer().is(AsmToken::Comma)) {
1008     // The optional access argument specifies the size of the smallest memory
1009     //   access to be made to the symbol, expressed in bytes.
1010     SMLoc AccessAlignmentLoc;
1011     Lex();
1012     AccessAlignmentLoc = getLexer().getLoc();
1013     if (getParser().parseAbsoluteExpression(AccessAlignment))
1014       return true;
1015 
1016     if (!isPowerOf2_64(AccessAlignment))
1017       return Error(AccessAlignmentLoc, "access alignment must be a power of 2");
1018   }
1019 
1020   if (getLexer().isNot(AsmToken::EndOfStatement))
1021     return TokError("unexpected token in '.comm' or '.lcomm' directive");
1022 
1023   Lex();
1024 
1025   // NOTE: a size of zero for a .comm should create a undefined symbol
1026   // but a size of .lcomm creates a bss symbol of size zero.
1027   if (Size < 0)
1028     return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't "
1029                           "be less than zero");
1030 
1031   // NOTE: The alignment in the directive is a power of 2 value, the assembler
1032   // may internally end up wanting an alignment in bytes.
1033   // FIXME: Diagnose overflow.
1034   if (ByteAlignment < 0)
1035     return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive "
1036                                    "alignment, can't be less than zero");
1037 
1038   if (!Sym->isUndefined())
1039     return Error(Loc, "invalid symbol redefinition");
1040 
1041   HexagonMCELFStreamer &HexagonELFStreamer =
1042       static_cast<HexagonMCELFStreamer &>(getStreamer());
1043   if (IsLocal) {
1044     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment,
1045                                                       AccessAlignment);
1046     return false;
1047   }
1048 
1049   HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment,
1050                                                AccessAlignment);
1051   return false;
1052 }
1053 
1054 // validate register against architecture
1055 bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
1056   return true;
1057 }
1058 
1059 // extern "C" void LLVMInitializeHexagonAsmLexer();
1060 
1061 /// Force static initialization.
1062 extern "C" void LLVMInitializeHexagonAsmParser() {
1063   RegisterMCAsmParser<HexagonAsmParser> X(getTheHexagonTarget());
1064 }
1065 
1066 #define GET_MATCHER_IMPLEMENTATION
1067 #define GET_REGISTER_MATCHER
1068 #include "HexagonGenAsmMatcher.inc"
1069 
1070 namespace {
1071 bool previousEqual(OperandVector &Operands, size_t Index, StringRef String) {
1072   if (Index >= Operands.size())
1073     return false;
1074   MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1];
1075   if (!Operand.isToken())
1076     return false;
1077   return static_cast<HexagonOperand &>(Operand).getToken().equals_lower(String);
1078 }
1079 bool previousIsLoop(OperandVector &Operands, size_t Index) {
1080   return previousEqual(Operands, Index, "loop0") ||
1081          previousEqual(Operands, Index, "loop1") ||
1082          previousEqual(Operands, Index, "sp1loop0") ||
1083          previousEqual(Operands, Index, "sp2loop0") ||
1084          previousEqual(Operands, Index, "sp3loop0");
1085 }
1086 }
1087 
1088 bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {
1089   AsmToken const &Token = getParser().getTok();
1090   StringRef String = Token.getString();
1091   SMLoc Loc = Token.getLoc();
1092   Lex();
1093   do {
1094     std::pair<StringRef, StringRef> HeadTail = String.split('.');
1095     if (!HeadTail.first.empty())
1096       Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc));
1097     if (!HeadTail.second.empty())
1098       Operands.push_back(HexagonOperand::CreateToken(
1099           String.substr(HeadTail.first.size(), 1), Loc));
1100     String = HeadTail.second;
1101   } while (!String.empty());
1102   return false;
1103 }
1104 
1105 bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
1106   unsigned Register;
1107   SMLoc Begin;
1108   SMLoc End;
1109   MCAsmLexer &Lexer = getLexer();
1110   if (!ParseRegister(Register, Begin, End)) {
1111     if (!ErrorMissingParenthesis)
1112       switch (Register) {
1113       default:
1114         break;
1115       case Hexagon::P0:
1116       case Hexagon::P1:
1117       case Hexagon::P2:
1118       case Hexagon::P3:
1119         if (previousEqual(Operands, 0, "if")) {
1120           if (WarnMissingParenthesis)
1121             Warning (Begin, "Missing parenthesis around predicate register");
1122           static char const *LParen = "(";
1123           static char const *RParen = ")";
1124           Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));
1125           Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
1126           const AsmToken &MaybeDotNew = Lexer.getTok();
1127           if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
1128               MaybeDotNew.getString().equals_lower(".new"))
1129             splitIdentifier(Operands);
1130           Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
1131           return false;
1132         }
1133         if (previousEqual(Operands, 0, "!") &&
1134             previousEqual(Operands, 1, "if")) {
1135           if (WarnMissingParenthesis)
1136             Warning (Begin, "Missing parenthesis around predicate register");
1137           static char const *LParen = "(";
1138           static char const *RParen = ")";
1139           Operands.insert(Operands.end () - 1,
1140                           HexagonOperand::CreateToken(LParen, Begin));
1141           Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
1142           const AsmToken &MaybeDotNew = Lexer.getTok();
1143           if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
1144               MaybeDotNew.getString().equals_lower(".new"))
1145             splitIdentifier(Operands);
1146           Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
1147           return false;
1148         }
1149         break;
1150       }
1151     Operands.push_back(HexagonOperand::CreateReg(
1152         Register, Begin, End));
1153     return false;
1154   }
1155   return splitIdentifier(Operands);
1156 }
1157 
1158 bool HexagonAsmParser::isLabel(AsmToken &Token) {
1159   MCAsmLexer &Lexer = getLexer();
1160   AsmToken const &Second = Lexer.getTok();
1161   AsmToken Third = Lexer.peekTok();
1162   StringRef String = Token.getString();
1163   if (Token.is(AsmToken::TokenKind::LCurly) ||
1164       Token.is(AsmToken::TokenKind::RCurly))
1165     return false;
1166   if (!Token.is(AsmToken::TokenKind::Identifier))
1167     return true;
1168   if (!matchRegister(String.lower()))
1169     return true;
1170   (void)Second;
1171   assert(Second.is(AsmToken::Colon));
1172   StringRef Raw (String.data(), Third.getString().data() - String.data() +
1173                  Third.getString().size());
1174   std::string Collapsed = Raw;
1175   Collapsed.erase(remove_if(Collapsed, isspace), Collapsed.end());
1176   StringRef Whole = Collapsed;
1177   std::pair<StringRef, StringRef> DotSplit = Whole.split('.');
1178   if (!matchRegister(DotSplit.first.lower()))
1179     return true;
1180   return false;
1181 }
1182 
1183 bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) {
1184   if (!Contigious && ErrorNoncontigiousRegister) {
1185     Error(Loc, "Register name is not contigious");
1186     return true;
1187   }
1188   if (!Contigious && WarnNoncontigiousRegister)
1189     Warning(Loc, "Register name is not contigious");
1190   return false;
1191 }
1192 
1193 bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1194   MCAsmLexer &Lexer = getLexer();
1195   StartLoc = getLexer().getLoc();
1196   SmallVector<AsmToken, 5> Lookahead;
1197   StringRef RawString(Lexer.getTok().getString().data(), 0);
1198   bool Again = Lexer.is(AsmToken::Identifier);
1199   bool NeededWorkaround = false;
1200   while (Again) {
1201     AsmToken const &Token = Lexer.getTok();
1202     RawString = StringRef(RawString.data(),
1203                           Token.getString().data() - RawString.data () +
1204                           Token.getString().size());
1205     Lookahead.push_back(Token);
1206     Lexer.Lex();
1207     bool Contigious = Lexer.getTok().getString().data() ==
1208                       Lookahead.back().getString().data() +
1209                       Lookahead.back().getString().size();
1210     bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||
1211                 Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
1212                 Lexer.is(AsmToken::Colon);
1213     bool Workaround = Lexer.is(AsmToken::Colon) ||
1214                       Lookahead.back().is(AsmToken::Colon);
1215     Again = (Contigious && Type) || (Workaround && Type);
1216     NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));
1217   }
1218   std::string Collapsed = RawString;
1219   Collapsed.erase(remove_if(Collapsed, isspace), Collapsed.end());
1220   StringRef FullString = Collapsed;
1221   std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
1222   unsigned DotReg = matchRegister(DotSplit.first.lower());
1223   if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1224     if (DotSplit.second.empty()) {
1225       RegNo = DotReg;
1226       EndLoc = Lexer.getLoc();
1227       if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1228         return true;
1229       return false;
1230     } else {
1231       RegNo = DotReg;
1232       size_t First = RawString.find('.');
1233       StringRef DotString (RawString.data() + First, RawString.size() - First);
1234       Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString));
1235       EndLoc = Lexer.getLoc();
1236       if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1237         return true;
1238       return false;
1239     }
1240   }
1241   std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
1242   unsigned ColonReg = matchRegister(ColonSplit.first.lower());
1243   if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1244     Lexer.UnLex(Lookahead.back());
1245     Lookahead.pop_back();
1246     Lexer.UnLex(Lookahead.back());
1247     Lookahead.pop_back();
1248     RegNo = ColonReg;
1249     EndLoc = Lexer.getLoc();
1250     if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1251       return true;
1252     return false;
1253   }
1254   while (!Lookahead.empty()) {
1255     Lexer.UnLex(Lookahead.back());
1256     Lookahead.pop_back();
1257   }
1258   return true;
1259 }
1260 
1261 bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) {
1262   if (previousEqual(Operands, 0, "call"))
1263     return true;
1264   if (previousEqual(Operands, 0, "jump"))
1265     if (!getLexer().getTok().is(AsmToken::Colon))
1266       return true;
1267   if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1))
1268     return true;
1269   if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") &&
1270       (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t")))
1271     return true;
1272   return false;
1273 }
1274 
1275 bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {
1276   llvm::SmallVector<AsmToken, 4> Tokens;
1277   MCAsmLexer &Lexer = getLexer();
1278   bool Done = false;
1279   static char const * Comma = ",";
1280   do {
1281     Tokens.emplace_back (Lexer.getTok());
1282     Lex();
1283     switch (Tokens.back().getKind())
1284     {
1285     case AsmToken::TokenKind::Hash:
1286       if (Tokens.size () > 1)
1287         if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) {
1288           Tokens.insert(Tokens.end() - 2,
1289                         AsmToken(AsmToken::TokenKind::Comma, Comma));
1290           Done = true;
1291         }
1292       break;
1293     case AsmToken::TokenKind::RCurly:
1294     case AsmToken::TokenKind::EndOfStatement:
1295     case AsmToken::TokenKind::Eof:
1296       Done = true;
1297       break;
1298     default:
1299       break;
1300     }
1301   } while (!Done);
1302   while (!Tokens.empty()) {
1303     Lexer.UnLex(Tokens.back());
1304     Tokens.pop_back();
1305   }
1306   return getParser().parseExpression(Expr);
1307 }
1308 
1309 bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
1310   if (implicitExpressionLocation(Operands)) {
1311     MCAsmParser &Parser = getParser();
1312     SMLoc Loc = Parser.getLexer().getLoc();
1313     MCExpr const *Expr = nullptr;
1314     bool Error = parseExpression(Expr);
1315     Expr = HexagonMCExpr::create(Expr, getContext());
1316     if (!Error)
1317       Operands.push_back(HexagonOperand::CreateImm(Expr, Loc, Loc));
1318     return Error;
1319   }
1320   return parseOperand(Operands);
1321 }
1322 
1323 /// Parse an instruction.
1324 bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
1325   MCAsmParser &Parser = getParser();
1326   MCAsmLexer &Lexer = getLexer();
1327   while (true) {
1328     AsmToken const &Token = Parser.getTok();
1329     switch (Token.getKind()) {
1330     case AsmToken::EndOfStatement: {
1331       Lex();
1332       return false;
1333     }
1334     case AsmToken::LCurly: {
1335       if (!Operands.empty())
1336         return true;
1337       Operands.push_back(
1338           HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1339       Lex();
1340       return false;
1341     }
1342     case AsmToken::RCurly: {
1343       if (Operands.empty()) {
1344         Operands.push_back(
1345             HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1346         Lex();
1347       }
1348       return false;
1349     }
1350     case AsmToken::Comma: {
1351       Lex();
1352       continue;
1353     }
1354     case AsmToken::EqualEqual:
1355     case AsmToken::ExclaimEqual:
1356     case AsmToken::GreaterEqual:
1357     case AsmToken::GreaterGreater:
1358     case AsmToken::LessEqual:
1359     case AsmToken::LessLess: {
1360       Operands.push_back(HexagonOperand::CreateToken(
1361           Token.getString().substr(0, 1), Token.getLoc()));
1362       Operands.push_back(HexagonOperand::CreateToken(
1363           Token.getString().substr(1, 1), Token.getLoc()));
1364       Lex();
1365       continue;
1366     }
1367     case AsmToken::Hash: {
1368       bool MustNotExtend = false;
1369       bool ImplicitExpression = implicitExpressionLocation(Operands);
1370       SMLoc ExprLoc = Lexer.getLoc();
1371       if (!ImplicitExpression)
1372         Operands.push_back(
1373           HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1374       Lex();
1375       bool MustExtend = false;
1376       bool HiOnly = false;
1377       bool LoOnly = false;
1378       if (Lexer.is(AsmToken::Hash)) {
1379         Lex();
1380         MustExtend = true;
1381       } else if (ImplicitExpression)
1382         MustNotExtend = true;
1383       AsmToken const &Token = Parser.getTok();
1384       if (Token.is(AsmToken::Identifier)) {
1385         StringRef String = Token.getString();
1386         if (String.lower() == "hi") {
1387           HiOnly = true;
1388         } else if (String.lower() == "lo") {
1389           LoOnly = true;
1390         }
1391         if (HiOnly || LoOnly) {
1392           AsmToken LParen = Lexer.peekTok();
1393           if (!LParen.is(AsmToken::LParen)) {
1394             HiOnly = false;
1395             LoOnly = false;
1396           } else {
1397             Lex();
1398           }
1399         }
1400       }
1401       MCExpr const *Expr = nullptr;
1402       if (parseExpression(Expr))
1403         return true;
1404       int64_t Value;
1405       MCContext &Context = Parser.getContext();
1406       assert(Expr != nullptr);
1407       if (Expr->evaluateAsAbsolute(Value)) {
1408         if (HiOnly)
1409           Expr = MCBinaryExpr::createLShr(
1410               Expr,  MCConstantExpr::create(16, Context), Context);
1411         if (HiOnly || LoOnly)
1412           Expr = MCBinaryExpr::createAnd(Expr,
1413               MCConstantExpr::create(0xffff, Context),
1414                                     Context);
1415       } else {
1416         MCValue Value;
1417         if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) {
1418           if (!Value.isAbsolute()) {
1419             switch(Value.getAccessVariant()) {
1420             case MCSymbolRefExpr::VariantKind::VK_TPREL:
1421             case MCSymbolRefExpr::VariantKind::VK_DTPREL:
1422               // Don't lazy extend these expression variants
1423               MustNotExtend = !MustExtend;
1424               break;
1425             default:
1426               break;
1427             }
1428           }
1429         }
1430       }
1431       Expr = HexagonMCExpr::create(Expr, Context);
1432       HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);
1433       HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
1434       std::unique_ptr<HexagonOperand> Operand =
1435           HexagonOperand::CreateImm(Expr, ExprLoc, ExprLoc);
1436       Operands.push_back(std::move(Operand));
1437       continue;
1438     }
1439     default:
1440       break;
1441     }
1442     if (parseExpressionOrOperand(Operands))
1443       return true;
1444   }
1445 }
1446 
1447 bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1448                                         StringRef Name,
1449                                         AsmToken ID,
1450                                         OperandVector &Operands) {
1451   getLexer().UnLex(ID);
1452   return parseInstruction(Operands);
1453 }
1454 
1455 namespace {
1456 MCInst makeCombineInst(int opCode, MCOperand &Rdd,
1457                        MCOperand &MO1, MCOperand &MO2) {
1458   MCInst TmpInst;
1459   TmpInst.setOpcode(opCode);
1460   TmpInst.addOperand(Rdd);
1461   TmpInst.addOperand(MO1);
1462   TmpInst.addOperand(MO2);
1463 
1464   return TmpInst;
1465 }
1466 }
1467 
1468 // Define this matcher function after the auto-generated include so we
1469 // have the match class enum definitions.
1470 unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1471                                                       unsigned Kind) {
1472   HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp);
1473 
1474   switch (Kind) {
1475   case MCK_0: {
1476     int64_t Value;
1477     return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0
1478                ? Match_Success
1479                : Match_InvalidOperand;
1480   }
1481   case MCK_1: {
1482     int64_t Value;
1483     return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1
1484                ? Match_Success
1485                : Match_InvalidOperand;
1486   }
1487   }
1488   if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) {
1489     StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length);
1490     if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind)
1491       return Match_Success;
1492     if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind)
1493       return Match_Success;
1494   }
1495 
1496   DEBUG(dbgs() << "Unmatched Operand:");
1497   DEBUG(Op->dump());
1498   DEBUG(dbgs() << "\n");
1499 
1500   return Match_InvalidOperand;
1501 }
1502 
1503 // FIXME: Calls to OutOfRange shoudl propagate failure up to parseStatement.
1504 bool HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
1505   std::string errStr;
1506   raw_string_ostream ES(errStr);
1507   ES << "value " << Val << "(" << format_hex(Val, 0) << ") out of range: ";
1508   if (Max >= 0)
1509     ES << "0-" << Max;
1510   else
1511     ES << Max << "-" << (-Max - 1);
1512   return Parser.printError(IDLoc, ES.str());
1513 }
1514 
1515 int HexagonAsmParser::processInstruction(MCInst &Inst,
1516                                          OperandVector const &Operands,
1517                                          SMLoc IDLoc) {
1518   MCContext &Context = getParser().getContext();
1519   const MCRegisterInfo *RI = getContext().getRegisterInfo();
1520   std::string r = "r";
1521   std::string v = "v";
1522   std::string Colon = ":";
1523 
1524   bool is32bit = false; // used to distinguish between CONST32 and CONST64
1525   switch (Inst.getOpcode()) {
1526   default:
1527     break;
1528 
1529   case Hexagon::A2_iconst: {
1530     Inst.setOpcode(Hexagon::A2_addi);
1531     MCOperand Reg = Inst.getOperand(0);
1532     MCOperand S16 = Inst.getOperand(1);
1533     HexagonMCInstrInfo::setMustNotExtend(*S16.getExpr());
1534     HexagonMCInstrInfo::setS23_2_reloc(*S16.getExpr());
1535     Inst.clear();
1536     Inst.addOperand(Reg);
1537     Inst.addOperand(MCOperand::createReg(Hexagon::R0));
1538     Inst.addOperand(S16);
1539     break;
1540   }
1541   case Hexagon::M4_mpyrr_addr:
1542   case Hexagon::S4_addi_asl_ri:
1543   case Hexagon::S4_addi_lsr_ri:
1544   case Hexagon::S4_andi_asl_ri:
1545   case Hexagon::S4_andi_lsr_ri:
1546   case Hexagon::S4_ori_asl_ri:
1547   case Hexagon::S4_ori_lsr_ri:
1548   case Hexagon::S4_or_andix:
1549   case Hexagon::S4_subi_asl_ri:
1550   case Hexagon::S4_subi_lsr_ri: {
1551     MCOperand &Ry = Inst.getOperand(0);
1552     MCOperand &src = Inst.getOperand(2);
1553     if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg()))
1554       return Match_InvalidOperand;
1555     break;
1556   }
1557 
1558   case Hexagon::C2_cmpgei: {
1559     MCOperand &MO = Inst.getOperand(2);
1560     MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1561         MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
1562     Inst.setOpcode(Hexagon::C2_cmpgti);
1563     break;
1564   }
1565 
1566   case Hexagon::C2_cmpgeui: {
1567     MCOperand &MO = Inst.getOperand(2);
1568     int64_t Value;
1569     bool Success = MO.getExpr()->evaluateAsAbsolute(Value);
1570     (void)Success;
1571     assert(Success && "Assured by matcher");
1572     if (Value == 0) {
1573       MCInst TmpInst;
1574       MCOperand &Pd = Inst.getOperand(0);
1575       MCOperand &Rt = Inst.getOperand(1);
1576       TmpInst.setOpcode(Hexagon::C2_cmpeq);
1577       TmpInst.addOperand(Pd);
1578       TmpInst.addOperand(Rt);
1579       TmpInst.addOperand(Rt);
1580       Inst = TmpInst;
1581     } else {
1582       MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1583           MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
1584       Inst.setOpcode(Hexagon::C2_cmpgtui);
1585     }
1586     break;
1587   }
1588 
1589   // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1590   case Hexagon::A2_tfrp: {
1591     MCOperand &MO = Inst.getOperand(1);
1592     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1593     std::string R1 = r + llvm::utostr(RegPairNum + 1);
1594     StringRef Reg1(R1);
1595     MO.setReg(matchRegister(Reg1));
1596     // Add a new operand for the second register in the pair.
1597     std::string R2 = r + llvm::utostr(RegPairNum);
1598     StringRef Reg2(R2);
1599     Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1600     Inst.setOpcode(Hexagon::A2_combinew);
1601     break;
1602   }
1603 
1604   case Hexagon::A2_tfrpt:
1605   case Hexagon::A2_tfrpf: {
1606     MCOperand &MO = Inst.getOperand(2);
1607     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1608     std::string R1 = r + llvm::utostr(RegPairNum + 1);
1609     StringRef Reg1(R1);
1610     MO.setReg(matchRegister(Reg1));
1611     // Add a new operand for the second register in the pair.
1612     std::string R2 = r + llvm::utostr(RegPairNum);
1613     StringRef Reg2(R2);
1614     Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1615     Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
1616                        ? Hexagon::C2_ccombinewt
1617                        : Hexagon::C2_ccombinewf);
1618     break;
1619   }
1620   case Hexagon::A2_tfrptnew:
1621   case Hexagon::A2_tfrpfnew: {
1622     MCOperand &MO = Inst.getOperand(2);
1623     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1624     std::string R1 = r + llvm::utostr(RegPairNum + 1);
1625     StringRef Reg1(R1);
1626     MO.setReg(matchRegister(Reg1));
1627     // Add a new operand for the second register in the pair.
1628     std::string R2 = r + llvm::utostr(RegPairNum);
1629     StringRef Reg2(R2);
1630     Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1631     Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
1632                        ? Hexagon::C2_ccombinewnewt
1633                        : Hexagon::C2_ccombinewnewf);
1634     break;
1635   }
1636 
1637   // Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)"
1638   case Hexagon::V6_vassignp: {
1639     MCOperand &MO = Inst.getOperand(1);
1640     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1641     std::string R1 = v + llvm::utostr(RegPairNum + 1);
1642     MO.setReg(MatchRegisterName(R1));
1643     // Add a new operand for the second register in the pair.
1644     std::string R2 = v + llvm::utostr(RegPairNum);
1645     Inst.addOperand(MCOperand::createReg(MatchRegisterName(R2)));
1646     Inst.setOpcode(Hexagon::V6_vcombine);
1647     break;
1648   }
1649 
1650   // Translate a "$Rx =  CONST32(#imm)" to "$Rx = memw(gp+#LABEL) "
1651   case Hexagon::CONST32:
1652     is32bit = true;
1653   // Translate a "$Rx:y =  CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "
1654   case Hexagon::CONST64:
1655     // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
1656     if (!Parser.getStreamer().hasRawTextSupport()) {
1657       MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
1658       MCOperand &MO_1 = Inst.getOperand(1);
1659       MCOperand &MO_0 = Inst.getOperand(0);
1660 
1661       // push section onto section stack
1662       MES->PushSection();
1663 
1664       std::string myCharStr;
1665       MCSectionELF *mySection;
1666 
1667       // check if this as an immediate or a symbol
1668       int64_t Value;
1669       bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value);
1670       if (Absolute) {
1671         // Create a new section - one for each constant
1672         // Some or all of the zeros are replaced with the given immediate.
1673         if (is32bit) {
1674           std::string myImmStr = utohexstr(static_cast<uint32_t>(Value));
1675           myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000")
1676                           .drop_back(myImmStr.size())
1677                           .str() +
1678                       myImmStr;
1679         } else {
1680           std::string myImmStr = utohexstr(Value);
1681           myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000")
1682                           .drop_back(myImmStr.size())
1683                           .str() +
1684                       myImmStr;
1685         }
1686 
1687         mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1688                                                ELF::SHF_ALLOC | ELF::SHF_WRITE);
1689       } else if (MO_1.isExpr()) {
1690         // .lita - for expressions
1691         myCharStr = ".lita";
1692         mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1693                                                ELF::SHF_ALLOC | ELF::SHF_WRITE);
1694       } else
1695         llvm_unreachable("unexpected type of machine operand!");
1696 
1697       MES->SwitchSection(mySection);
1698       unsigned byteSize = is32bit ? 4 : 8;
1699       getStreamer().EmitCodeAlignment(byteSize, byteSize);
1700 
1701       MCSymbol *Sym;
1702 
1703       // for symbols, get rid of prepended ".gnu.linkonce.lx."
1704 
1705       // emit symbol if needed
1706       if (Absolute) {
1707         Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16));
1708         if (Sym->isUndefined()) {
1709           getStreamer().EmitLabel(Sym);
1710           getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
1711           getStreamer().EmitIntValue(Value, byteSize);
1712         }
1713       } else if (MO_1.isExpr()) {
1714         const char *StringStart = 0;
1715         const char *StringEnd = 0;
1716         if (*Operands[4]->getStartLoc().getPointer() == '#') {
1717           StringStart = Operands[5]->getStartLoc().getPointer();
1718           StringEnd = Operands[6]->getStartLoc().getPointer();
1719         } else { // no pound
1720           StringStart = Operands[4]->getStartLoc().getPointer();
1721           StringEnd = Operands[5]->getStartLoc().getPointer();
1722         }
1723 
1724         unsigned size = StringEnd - StringStart;
1725         std::string DotConst = ".CONST_";
1726         Sym = getContext().getOrCreateSymbol(DotConst +
1727                                              StringRef(StringStart, size));
1728 
1729         if (Sym->isUndefined()) {
1730           // case where symbol is not yet defined: emit symbol
1731           getStreamer().EmitLabel(Sym);
1732           getStreamer().EmitSymbolAttribute(Sym, MCSA_Local);
1733           getStreamer().EmitValue(MO_1.getExpr(), 4);
1734         }
1735       } else
1736         llvm_unreachable("unexpected type of machine operand!");
1737 
1738       MES->PopSection();
1739 
1740       if (Sym) {
1741         MCInst TmpInst;
1742         if (is32bit) // 32 bit
1743           TmpInst.setOpcode(Hexagon::L2_loadrigp);
1744         else // 64 bit
1745           TmpInst.setOpcode(Hexagon::L2_loadrdgp);
1746 
1747         TmpInst.addOperand(MO_0);
1748         TmpInst.addOperand(
1749             MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext())));
1750         Inst = TmpInst;
1751       }
1752     }
1753     break;
1754 
1755   // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)"
1756   case Hexagon::A2_tfrpi: {
1757     MCOperand &Rdd = Inst.getOperand(0);
1758     MCOperand &MO = Inst.getOperand(1);
1759     int64_t Value;
1760     int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0;
1761     MCOperand imm(MCOperand::createExpr(
1762         HexagonMCExpr::create(MCConstantExpr::create(sVal, Context), Context)));
1763     Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO);
1764     break;
1765   }
1766 
1767   // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)"
1768   case Hexagon::TFRI64_V4: {
1769     MCOperand &Rdd = Inst.getOperand(0);
1770     MCOperand &MO = Inst.getOperand(1);
1771     int64_t Value;
1772     if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1773       int s8 = Hi_32(Value);
1774       if (!isInt<8>(s8))
1775         OutOfRange(IDLoc, s8, -128);
1776       MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1777           MCConstantExpr::create(s8, Context), Context))); // upper 32
1778       auto Expr = HexagonMCExpr::create(
1779           MCConstantExpr::create(Lo_32(Value), Context), Context);
1780       HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
1781       MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
1782       Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
1783     } else {
1784       MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1785           MCConstantExpr::create(0, Context), Context))); // upper 32
1786       Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO);
1787     }
1788     break;
1789   }
1790 
1791   // Handle $Rdd = combine(##imm, #imm)"
1792   case Hexagon::TFRI64_V2_ext: {
1793     MCOperand &Rdd = Inst.getOperand(0);
1794     MCOperand &MO1 = Inst.getOperand(1);
1795     MCOperand &MO2 = Inst.getOperand(2);
1796     int64_t Value;
1797     if (MO2.getExpr()->evaluateAsAbsolute(Value)) {
1798       int s8 = Value;
1799       if (s8 < -128 || s8 > 127)
1800         OutOfRange(IDLoc, s8, -128);
1801     }
1802     Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);
1803     break;
1804   }
1805 
1806   // Handle $Rdd = combine(#imm, ##imm)"
1807   case Hexagon::A4_combineii: {
1808     MCOperand &Rdd = Inst.getOperand(0);
1809     MCOperand &MO1 = Inst.getOperand(1);
1810     int64_t Value;
1811     if (MO1.getExpr()->evaluateAsAbsolute(Value)) {
1812       int s8 = Value;
1813       if (s8 < -128 || s8 > 127)
1814         OutOfRange(IDLoc, s8, -128);
1815     }
1816     MCOperand &MO2 = Inst.getOperand(2);
1817     Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);
1818     break;
1819   }
1820 
1821   case Hexagon::S2_tableidxb_goodsyntax: {
1822     Inst.setOpcode(Hexagon::S2_tableidxb);
1823     break;
1824   }
1825 
1826   case Hexagon::S2_tableidxh_goodsyntax: {
1827     MCInst TmpInst;
1828     MCOperand &Rx = Inst.getOperand(0);
1829     MCOperand &_dst_ = Inst.getOperand(1);
1830     MCOperand &Rs = Inst.getOperand(2);
1831     MCOperand &Imm4 = Inst.getOperand(3);
1832     MCOperand &Imm6 = Inst.getOperand(4);
1833     Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1834         Imm6.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
1835     TmpInst.setOpcode(Hexagon::S2_tableidxh);
1836     TmpInst.addOperand(Rx);
1837     TmpInst.addOperand(_dst_);
1838     TmpInst.addOperand(Rs);
1839     TmpInst.addOperand(Imm4);
1840     TmpInst.addOperand(Imm6);
1841     Inst = TmpInst;
1842     break;
1843   }
1844 
1845   case Hexagon::S2_tableidxw_goodsyntax: {
1846     MCInst TmpInst;
1847     MCOperand &Rx = Inst.getOperand(0);
1848     MCOperand &_dst_ = Inst.getOperand(1);
1849     MCOperand &Rs = Inst.getOperand(2);
1850     MCOperand &Imm4 = Inst.getOperand(3);
1851     MCOperand &Imm6 = Inst.getOperand(4);
1852     Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1853         Imm6.getExpr(), MCConstantExpr::create(2, Context), Context), Context));
1854     TmpInst.setOpcode(Hexagon::S2_tableidxw);
1855     TmpInst.addOperand(Rx);
1856     TmpInst.addOperand(_dst_);
1857     TmpInst.addOperand(Rs);
1858     TmpInst.addOperand(Imm4);
1859     TmpInst.addOperand(Imm6);
1860     Inst = TmpInst;
1861     break;
1862   }
1863 
1864   case Hexagon::S2_tableidxd_goodsyntax: {
1865     MCInst TmpInst;
1866     MCOperand &Rx = Inst.getOperand(0);
1867     MCOperand &_dst_ = Inst.getOperand(1);
1868     MCOperand &Rs = Inst.getOperand(2);
1869     MCOperand &Imm4 = Inst.getOperand(3);
1870     MCOperand &Imm6 = Inst.getOperand(4);
1871     Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1872         Imm6.getExpr(), MCConstantExpr::create(3, Context), Context), Context));
1873     TmpInst.setOpcode(Hexagon::S2_tableidxd);
1874     TmpInst.addOperand(Rx);
1875     TmpInst.addOperand(_dst_);
1876     TmpInst.addOperand(Rs);
1877     TmpInst.addOperand(Imm4);
1878     TmpInst.addOperand(Imm6);
1879     Inst = TmpInst;
1880     break;
1881   }
1882 
1883   case Hexagon::M2_mpyui: {
1884     Inst.setOpcode(Hexagon::M2_mpyi);
1885     break;
1886   }
1887   case Hexagon::M2_mpysmi: {
1888     MCInst TmpInst;
1889     MCOperand &Rd = Inst.getOperand(0);
1890     MCOperand &Rs = Inst.getOperand(1);
1891     MCOperand &Imm = Inst.getOperand(2);
1892     int64_t Value;
1893     MCExpr const &Expr = *Imm.getExpr();
1894     bool Absolute = Expr.evaluateAsAbsolute(Value);
1895     assert(Absolute);
1896     (void)Absolute;
1897     if (!HexagonMCInstrInfo::mustExtend(Expr)) {
1898       if (Value < 0 && Value > -256) {
1899         Imm.setExpr(HexagonMCExpr::create(
1900             MCConstantExpr::create(Value * -1, Context), Context));
1901         TmpInst.setOpcode(Hexagon::M2_mpysin);
1902       } else if (Value < 256 && Value >= 0)
1903         TmpInst.setOpcode(Hexagon::M2_mpysip);
1904       else
1905         return Match_InvalidOperand;
1906     } else {
1907       if (Value >= 0)
1908         TmpInst.setOpcode(Hexagon::M2_mpysip);
1909       else
1910         return Match_InvalidOperand;
1911     }
1912     TmpInst.addOperand(Rd);
1913     TmpInst.addOperand(Rs);
1914     TmpInst.addOperand(Imm);
1915     Inst = TmpInst;
1916     break;
1917   }
1918 
1919   case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
1920     MCOperand &Imm = Inst.getOperand(2);
1921     MCInst TmpInst;
1922     int64_t Value;
1923     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1924     assert(Absolute);
1925     (void)Absolute;
1926     if (Value == 0) { // convert to $Rd = $Rs
1927       TmpInst.setOpcode(Hexagon::A2_tfr);
1928       MCOperand &Rd = Inst.getOperand(0);
1929       MCOperand &Rs = Inst.getOperand(1);
1930       TmpInst.addOperand(Rd);
1931       TmpInst.addOperand(Rs);
1932     } else {
1933       Imm.setExpr(HexagonMCExpr::create(
1934           MCBinaryExpr::createSub(Imm.getExpr(),
1935                                   MCConstantExpr::create(1, Context), Context),
1936           Context));
1937       TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
1938       MCOperand &Rd = Inst.getOperand(0);
1939       MCOperand &Rs = Inst.getOperand(1);
1940       TmpInst.addOperand(Rd);
1941       TmpInst.addOperand(Rs);
1942       TmpInst.addOperand(Imm);
1943     }
1944     Inst = TmpInst;
1945     break;
1946   }
1947 
1948   case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
1949     MCOperand &Rdd = Inst.getOperand(0);
1950     MCOperand &Rss = Inst.getOperand(1);
1951     MCOperand &Imm = Inst.getOperand(2);
1952     int64_t Value;
1953     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1954     assert(Absolute);
1955     (void)Absolute;
1956     if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1])
1957       MCInst TmpInst;
1958       unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1959       std::string R1 = r + llvm::utostr(RegPairNum + 1);
1960       StringRef Reg1(R1);
1961       Rss.setReg(matchRegister(Reg1));
1962       // Add a new operand for the second register in the pair.
1963       std::string R2 = r + llvm::utostr(RegPairNum);
1964       StringRef Reg2(R2);
1965       TmpInst.setOpcode(Hexagon::A2_combinew);
1966       TmpInst.addOperand(Rdd);
1967       TmpInst.addOperand(Rss);
1968       TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1969       Inst = TmpInst;
1970     } else {
1971       Imm.setExpr(HexagonMCExpr::create(
1972           MCBinaryExpr::createSub(Imm.getExpr(),
1973                                   MCConstantExpr::create(1, Context), Context),
1974           Context));
1975       Inst.setOpcode(Hexagon::S2_asr_i_p_rnd);
1976     }
1977     break;
1978   }
1979 
1980   case Hexagon::A4_boundscheck: {
1981     MCOperand &Rs = Inst.getOperand(1);
1982     unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1983     if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1984       Inst.setOpcode(Hexagon::A4_boundscheck_hi);
1985       std::string Name =
1986           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
1987       StringRef RegPair = Name;
1988       Rs.setReg(matchRegister(RegPair));
1989     } else { // raw:lo
1990       Inst.setOpcode(Hexagon::A4_boundscheck_lo);
1991       std::string Name =
1992           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
1993       StringRef RegPair = Name;
1994       Rs.setReg(matchRegister(RegPair));
1995     }
1996     break;
1997   }
1998 
1999   case Hexagon::A2_addsp: {
2000     MCOperand &Rs = Inst.getOperand(1);
2001     unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
2002     if (RegNum & 1) { // Odd mapped to raw:hi
2003       Inst.setOpcode(Hexagon::A2_addsph);
2004       std::string Name =
2005           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2006       StringRef RegPair = Name;
2007       Rs.setReg(matchRegister(RegPair));
2008     } else { // Even mapped raw:lo
2009       Inst.setOpcode(Hexagon::A2_addspl);
2010       std::string Name =
2011           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2012       StringRef RegPair = Name;
2013       Rs.setReg(matchRegister(RegPair));
2014     }
2015     break;
2016   }
2017 
2018   case Hexagon::M2_vrcmpys_s1: {
2019     MCOperand &Rt = Inst.getOperand(2);
2020     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2021     if (RegNum & 1) { // Odd mapped to sat:raw:hi
2022       Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
2023       std::string Name =
2024           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2025       StringRef RegPair = Name;
2026       Rt.setReg(matchRegister(RegPair));
2027     } else { // Even mapped sat:raw:lo
2028       Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
2029       std::string Name =
2030           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2031       StringRef RegPair = Name;
2032       Rt.setReg(matchRegister(RegPair));
2033     }
2034     break;
2035   }
2036 
2037   case Hexagon::M2_vrcmpys_acc_s1: {
2038     MCInst TmpInst;
2039     MCOperand &Rxx = Inst.getOperand(0);
2040     MCOperand &Rss = Inst.getOperand(2);
2041     MCOperand &Rt = Inst.getOperand(3);
2042     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2043     if (RegNum & 1) { // Odd mapped to sat:raw:hi
2044       TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
2045       std::string Name =
2046           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2047       StringRef RegPair = Name;
2048       Rt.setReg(matchRegister(RegPair));
2049     } else { // Even mapped sat:raw:lo
2050       TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
2051       std::string Name =
2052           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2053       StringRef RegPair = Name;
2054       Rt.setReg(matchRegister(RegPair));
2055     }
2056     // Registers are in different positions
2057     TmpInst.addOperand(Rxx);
2058     TmpInst.addOperand(Rxx);
2059     TmpInst.addOperand(Rss);
2060     TmpInst.addOperand(Rt);
2061     Inst = TmpInst;
2062     break;
2063   }
2064 
2065   case Hexagon::M2_vrcmpys_s1rp: {
2066     MCOperand &Rt = Inst.getOperand(2);
2067     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2068     if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi
2069       Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
2070       std::string Name =
2071           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2072       StringRef RegPair = Name;
2073       Rt.setReg(matchRegister(RegPair));
2074     } else { // Even mapped rnd:sat:raw:lo
2075       Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
2076       std::string Name =
2077           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2078       StringRef RegPair = Name;
2079       Rt.setReg(matchRegister(RegPair));
2080     }
2081     break;
2082   }
2083 
2084   case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
2085     MCOperand &Imm = Inst.getOperand(2);
2086     int64_t Value;
2087     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
2088     assert(Absolute);
2089     (void)Absolute;
2090     if (Value == 0)
2091       Inst.setOpcode(Hexagon::S2_vsathub);
2092     else {
2093       Imm.setExpr(HexagonMCExpr::create(
2094           MCBinaryExpr::createSub(Imm.getExpr(),
2095                                   MCConstantExpr::create(1, Context), Context),
2096           Context));
2097       Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
2098     }
2099     break;
2100   }
2101 
2102   case Hexagon::S5_vasrhrnd_goodsyntax: {
2103     MCOperand &Rdd = Inst.getOperand(0);
2104     MCOperand &Rss = Inst.getOperand(1);
2105     MCOperand &Imm = Inst.getOperand(2);
2106     int64_t Value;
2107     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
2108     assert(Absolute);
2109     (void)Absolute;
2110     if (Value == 0) {
2111       MCInst TmpInst;
2112       unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
2113       std::string R1 = r + llvm::utostr(RegPairNum + 1);
2114       StringRef Reg1(R1);
2115       Rss.setReg(matchRegister(Reg1));
2116       // Add a new operand for the second register in the pair.
2117       std::string R2 = r + llvm::utostr(RegPairNum);
2118       StringRef Reg2(R2);
2119       TmpInst.setOpcode(Hexagon::A2_combinew);
2120       TmpInst.addOperand(Rdd);
2121       TmpInst.addOperand(Rss);
2122       TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
2123       Inst = TmpInst;
2124     } else {
2125       Imm.setExpr(HexagonMCExpr::create(
2126           MCBinaryExpr::createSub(Imm.getExpr(),
2127                                   MCConstantExpr::create(1, Context), Context),
2128           Context));
2129       Inst.setOpcode(Hexagon::S5_vasrhrnd);
2130     }
2131     break;
2132   }
2133 
2134   case Hexagon::A2_not: {
2135     MCInst TmpInst;
2136     MCOperand &Rd = Inst.getOperand(0);
2137     MCOperand &Rs = Inst.getOperand(1);
2138     TmpInst.setOpcode(Hexagon::A2_subri);
2139     TmpInst.addOperand(Rd);
2140     TmpInst.addOperand(MCOperand::createExpr(
2141         HexagonMCExpr::create(MCConstantExpr::create(-1, Context), Context)));
2142     TmpInst.addOperand(Rs);
2143     Inst = TmpInst;
2144     break;
2145   }
2146   } // switch
2147 
2148   return Match_Success;
2149 }
2150 
2151 
2152 unsigned HexagonAsmParser::matchRegister(StringRef Name) {
2153   if (unsigned Reg = MatchRegisterName(Name))
2154     return Reg;
2155   return MatchRegisterAltName(Name);
2156 }
2157