1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #define DEBUG_TYPE "mcasmparser"
11 
12 #include "Hexagon.h"
13 #include "HexagonRegisterInfo.h"
14 #include "HexagonTargetStreamer.h"
15 #include "MCTargetDesc/HexagonBaseInfo.h"
16 #include "MCTargetDesc/HexagonMCAsmInfo.h"
17 #include "MCTargetDesc/HexagonMCChecker.h"
18 #include "MCTargetDesc/HexagonMCELFStreamer.h"
19 #include "MCTargetDesc/HexagonMCExpr.h"
20 #include "MCTargetDesc/HexagonMCShuffler.h"
21 #include "MCTargetDesc/HexagonMCTargetDesc.h"
22 #include "MCTargetDesc/HexagonShuffler.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCELFStreamer.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCParser/MCAsmLexer.h"
31 #include "llvm/MC/MCParser/MCAsmParser.h"
32 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
33 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/MC/MCValue.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ELF.h"
41 #include "llvm/Support/Format.h"
42 #include "llvm/Support/MemoryBuffer.h"
43 #include "llvm/Support/SourceMgr.h"
44 #include "llvm/Support/TargetRegistry.h"
45 #include "llvm/Support/raw_ostream.h"
46 
47 using namespace llvm;
48 
49 static cl::opt<bool> EnableFutureRegs("mfuture-regs",
50                                       cl::desc("Enable future registers"));
51 
52 static cl::opt<bool> WarnMissingParenthesis("mwarn-missing-parenthesis",
53 cl::desc("Warn for missing parenthesis around predicate registers"),
54 cl::init(true));
55 static cl::opt<bool> ErrorMissingParenthesis("merror-missing-parenthesis",
56 cl::desc("Error for missing parenthesis around predicate registers"),
57 cl::init(false));
58 static cl::opt<bool> WarnSignedMismatch("mwarn-sign-mismatch",
59 cl::desc("Warn for mismatching a signed and unsigned value"),
60 cl::init(true));
61 static cl::opt<bool> WarnNoncontigiousRegister("mwarn-noncontigious-register",
62 cl::desc("Warn for register names that arent contigious"),
63 cl::init(true));
64 static cl::opt<bool> ErrorNoncontigiousRegister("merror-noncontigious-register",
65 cl::desc("Error for register names that aren't contigious"),
66 cl::init(false));
67 
68 
69 namespace {
70 struct HexagonOperand;
71 
72 class HexagonAsmParser : public MCTargetAsmParser {
73 
74   HexagonTargetStreamer &getTargetStreamer() {
75     MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
76     return static_cast<HexagonTargetStreamer &>(TS);
77   }
78 
79   MCAsmParser &Parser;
80   MCAssembler *Assembler;
81   MCInstrInfo const &MCII;
82   MCInst MCB;
83   bool InBrackets;
84 
85   MCAsmParser &getParser() const { return Parser; }
86   MCAssembler *getAssembler() const { return Assembler; }
87   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
88 
89   bool equalIsAsmAssignment() override { return false; }
90   bool isLabel(AsmToken &Token) override;
91 
92   void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
93   bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
94   bool ParseDirectiveFalign(unsigned Size, SMLoc L);
95 
96   virtual bool ParseRegister(unsigned &RegNo,
97                              SMLoc &StartLoc,
98                              SMLoc &EndLoc) override;
99   bool ParseDirectiveSubsection(SMLoc L);
100   bool ParseDirectiveValue(unsigned Size, SMLoc L);
101   bool ParseDirectiveComm(bool IsLocal, SMLoc L);
102   bool RegisterMatchesArch(unsigned MatchNum) const;
103 
104   bool matchBundleOptions();
105   bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);
106   bool finishBundle(SMLoc IDLoc, MCStreamer &Out);
107   void canonicalizeImmediates(MCInst &MCI);
108   bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
109                            OperandVector &InstOperands, uint64_t &ErrorInfo,
110                            bool MatchingInlineAsm);
111 
112   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
113                                OperandVector &Operands, MCStreamer &Out,
114                                uint64_t &ErrorInfo, bool MatchingInlineAsm) override;
115 
116   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override;
117   void OutOfRange(SMLoc IDLoc, long long Val, long long Max);
118   int processInstruction(MCInst &Inst, OperandVector const &Operands,
119                          SMLoc IDLoc);
120 
121   // Check if we have an assembler and, if so, set the ELF e_header flags.
122   void chksetELFHeaderEFlags(unsigned flags) {
123     if (getAssembler())
124       getAssembler()->setELFHeaderEFlags(flags);
125   }
126 
127   unsigned matchRegister(StringRef Name);
128 
129 /// @name Auto-generated Match Functions
130 /// {
131 
132 #define GET_ASSEMBLER_HEADER
133 #include "HexagonGenAsmMatcher.inc"
134 
135   /// }
136 
137 public:
138   HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
139                    const MCInstrInfo &MII, const MCTargetOptions &Options)
140     : MCTargetAsmParser(Options, _STI), Parser(_Parser),
141       MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
142     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
143 
144   MCAsmParserExtension::Initialize(_Parser);
145 
146   Assembler = nullptr;
147   // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
148   if (!Parser.getStreamer().hasRawTextSupport()) {
149     MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
150     Assembler = &MES->getAssembler();
151   }
152   }
153 
154   bool mustExtend(OperandVector &Operands);
155   bool splitIdentifier(OperandVector &Operands);
156   bool parseOperand(OperandVector &Operands);
157   bool parseInstruction(OperandVector &Operands);
158   bool implicitExpressionLocation(OperandVector &Operands);
159   bool parseExpressionOrOperand(OperandVector &Operands);
160   bool parseExpression(MCExpr const *& Expr);
161   virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
162                                 SMLoc NameLoc, OperandVector &Operands) override
163   {
164     llvm_unreachable("Unimplemented");
165   }
166   virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
167                                 AsmToken ID, OperandVector &Operands) override;
168 
169   virtual bool ParseDirective(AsmToken DirectiveID) override;
170 };
171 
172 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
173 /// instruction.
174 struct HexagonOperand : public MCParsedAsmOperand {
175   enum KindTy { Token, Immediate, Register } Kind;
176 
177   SMLoc StartLoc, EndLoc;
178 
179   struct TokTy {
180     const char *Data;
181     unsigned Length;
182   };
183 
184   struct RegTy {
185     unsigned RegNum;
186   };
187 
188   struct ImmTy {
189     const MCExpr *Val;
190   };
191 
192   struct InstTy {
193     OperandVector *SubInsts;
194   };
195 
196   union {
197     struct TokTy Tok;
198     struct RegTy Reg;
199     struct ImmTy Imm;
200   };
201 
202   HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
203 
204 public:
205   HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() {
206     Kind = o.Kind;
207     StartLoc = o.StartLoc;
208     EndLoc = o.EndLoc;
209     switch (Kind) {
210     case Register:
211       Reg = o.Reg;
212       break;
213     case Immediate:
214       Imm = o.Imm;
215       break;
216     case Token:
217       Tok = o.Tok;
218       break;
219     }
220   }
221 
222   /// getStartLoc - Get the location of the first token of this operand.
223   SMLoc getStartLoc() const { return StartLoc; }
224 
225   /// getEndLoc - Get the location of the last token of this operand.
226   SMLoc getEndLoc() const { return EndLoc; }
227 
228   unsigned getReg() const {
229     assert(Kind == Register && "Invalid access!");
230     return Reg.RegNum;
231   }
232 
233   const MCExpr *getImm() const {
234     assert(Kind == Immediate && "Invalid access!");
235     return Imm.Val;
236   }
237 
238   bool isToken() const { return Kind == Token; }
239   bool isImm() const { return Kind == Immediate; }
240   bool isMem() const { llvm_unreachable("No isMem"); }
241   bool isReg() const { return Kind == Register; }
242 
243   bool CheckImmRange(int immBits, int zeroBits, bool isSigned,
244                      bool isRelocatable, bool Extendable) const {
245     if (Kind == Immediate) {
246       const MCExpr *myMCExpr = &HexagonMCInstrInfo::getExpr(*getImm());
247       if (HexagonMCInstrInfo::mustExtend(*Imm.Val) && !Extendable)
248         return false;
249       int64_t Res;
250       if (myMCExpr->evaluateAsAbsolute(Res)) {
251         int bits = immBits + zeroBits;
252         // Field bit range is zerobits + bits
253         // zeroBits must be 0
254         if (Res & ((1 << zeroBits) - 1))
255           return false;
256         if (isSigned) {
257           if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1)))
258             return true;
259         } else {
260           if (bits == 64)
261             return true;
262           if (Res >= 0)
263             return ((uint64_t)Res < (uint64_t)(1ULL << bits)) ? true : false;
264           else {
265             const int64_t high_bit_set = 1ULL << 63;
266             const uint64_t mask = (high_bit_set >> (63 - bits));
267             return (((uint64_t)Res & mask) == mask) ? true : false;
268           }
269         }
270       } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable)
271         return true;
272       else if (myMCExpr->getKind() == MCExpr::Binary ||
273                myMCExpr->getKind() == MCExpr::Unary)
274         return true;
275     }
276     return false;
277   }
278 
279   bool isf32Ext() const { return false; }
280   bool iss32Imm() const { return CheckImmRange(32, 0, true, true, false); }
281   bool iss23_2Imm() const { return CheckImmRange(23, 2, true, true, false); }
282   bool iss8Imm() const { return CheckImmRange(8, 0, true, false, false); }
283   bool iss8Imm64() const { return CheckImmRange(8, 0, true, true, false); }
284   bool iss7Imm() const { return CheckImmRange(7, 0, true, false, false); }
285   bool iss6Imm() const { return CheckImmRange(6, 0, true, false, false); }
286   bool iss4Imm() const { return CheckImmRange(4, 0, true, false, false); }
287   bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); }
288   bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
289   bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
290   bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
291   bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); }
292   bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); }
293   bool iss3Imm() const { return CheckImmRange(3, 0, true, false, false); }
294 
295   bool isu64Imm() const { return CheckImmRange(64, 0, false, true, true); }
296   bool isu32Imm() const { return CheckImmRange(32, 0, false, true, false); }
297   bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); }
298   bool isu16Imm() const { return CheckImmRange(16, 0, false, true, false); }
299   bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); }
300   bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); }
301   bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); }
302   bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); }
303   bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); }
304   bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
305   bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); }
306   bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); }
307   bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); }
308   bool isu10Imm() const { return CheckImmRange(10, 0, false, false, false); }
309   bool isu9Imm() const { return CheckImmRange(9, 0, false, false, false); }
310   bool isu8Imm() const { return CheckImmRange(8, 0, false, false, false); }
311   bool isu7Imm() const { return CheckImmRange(7, 0, false, false, false); }
312   bool isu6Imm() const { return CheckImmRange(6, 0, false, false, false); }
313   bool isu5Imm() const { return CheckImmRange(5, 0, false, false, false); }
314   bool isu4Imm() const { return CheckImmRange(4, 0, false, false, false); }
315   bool isu3Imm() const { return CheckImmRange(3, 0, false, false, false); }
316   bool isu2Imm() const { return CheckImmRange(2, 0, false, false, false); }
317   bool isu1Imm() const { return CheckImmRange(1, 0, false, false, false); }
318 
319   bool ism6Imm() const { return CheckImmRange(6, 0, false, false, false); }
320   bool isn8Imm() const { return CheckImmRange(8, 0, false, false, false); }
321 
322   bool iss16Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); }
323   bool iss12Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); }
324   bool iss10Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); }
325   bool iss9Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); }
326   bool iss8Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); }
327   bool iss7Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); }
328   bool iss6Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); }
329   bool iss11_0Ext() const {
330     return CheckImmRange(11 + 26, 0, true, true, true);
331   }
332   bool iss11_1Ext() const {
333     return CheckImmRange(11 + 26, 1, true, true, true);
334   }
335   bool iss11_2Ext() const {
336     return CheckImmRange(11 + 26, 2, true, true, true);
337   }
338   bool iss11_3Ext() const {
339     return CheckImmRange(11 + 26, 3, true, true, true);
340   }
341 
342   bool isu6Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
343   bool isu7Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); }
344   bool isu8Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); }
345   bool isu9Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); }
346   bool isu10Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); }
347   bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
348   bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); }
349   bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); }
350   bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); }
351   bool isu32MustExt() const { return isImm(); }
352 
353   void addRegOperands(MCInst &Inst, unsigned N) const {
354     assert(N == 1 && "Invalid number of operands!");
355     Inst.addOperand(MCOperand::createReg(getReg()));
356   }
357 
358   void addImmOperands(MCInst &Inst, unsigned N) const {
359     assert(N == 1 && "Invalid number of operands!");
360     Inst.addOperand(MCOperand::createExpr(getImm()));
361   }
362 
363   void addSignedImmOperands(MCInst &Inst, unsigned N) const {
364     assert(N == 1 && "Invalid number of operands!");
365     HexagonMCExpr *Expr =
366         const_cast<HexagonMCExpr *>(cast<HexagonMCExpr>(getImm()));
367     int64_t Value;
368     if (!Expr->evaluateAsAbsolute(Value)) {
369       Inst.addOperand(MCOperand::createExpr(Expr));
370       return;
371     }
372     int64_t Extended = SignExtend64(Value, 32);
373     if ((Extended < 0) != (Value < 0))
374       Expr->setSignMismatch();
375     Inst.addOperand(MCOperand::createExpr(Expr));
376   }
377 
378   void addf32ExtOperands(MCInst &Inst, unsigned N) const {
379     addImmOperands(Inst, N);
380   }
381 
382   void adds32ImmOperands(MCInst &Inst, unsigned N) const {
383     addSignedImmOperands(Inst, N);
384   }
385   void adds23_2ImmOperands(MCInst &Inst, unsigned N) const {
386     addSignedImmOperands(Inst, N);
387   }
388   void adds8ImmOperands(MCInst &Inst, unsigned N) const {
389     addSignedImmOperands(Inst, N);
390   }
391   void adds8Imm64Operands(MCInst &Inst, unsigned N) const {
392     addSignedImmOperands(Inst, N);
393   }
394   void adds6ImmOperands(MCInst &Inst, unsigned N) const {
395     addSignedImmOperands(Inst, N);
396   }
397   void adds4ImmOperands(MCInst &Inst, unsigned N) const {
398     addSignedImmOperands(Inst, N);
399   }
400   void adds4_0ImmOperands(MCInst &Inst, unsigned N) const {
401     addSignedImmOperands(Inst, N);
402   }
403   void adds4_1ImmOperands(MCInst &Inst, unsigned N) const {
404     addSignedImmOperands(Inst, N);
405   }
406   void adds4_2ImmOperands(MCInst &Inst, unsigned N) const {
407     addSignedImmOperands(Inst, N);
408   }
409   void adds4_3ImmOperands(MCInst &Inst, unsigned N) const {
410     addSignedImmOperands(Inst, N);
411   }
412   void adds3ImmOperands(MCInst &Inst, unsigned N) const {
413     addSignedImmOperands(Inst, N);
414   }
415 
416   void addu64ImmOperands(MCInst &Inst, unsigned N) const {
417     addImmOperands(Inst, N);
418   }
419   void addu32ImmOperands(MCInst &Inst, unsigned N) const {
420     addImmOperands(Inst, N);
421   }
422   void addu26_6ImmOperands(MCInst &Inst, unsigned N) const {
423     addImmOperands(Inst, N);
424   }
425   void addu16ImmOperands(MCInst &Inst, unsigned N) const {
426     addImmOperands(Inst, N);
427   }
428   void addu16_0ImmOperands(MCInst &Inst, unsigned N) const {
429     addImmOperands(Inst, N);
430   }
431   void addu16_1ImmOperands(MCInst &Inst, unsigned N) const {
432     addImmOperands(Inst, N);
433   }
434   void addu16_2ImmOperands(MCInst &Inst, unsigned N) const {
435     addImmOperands(Inst, N);
436   }
437   void addu16_3ImmOperands(MCInst &Inst, unsigned N) const {
438     addImmOperands(Inst, N);
439   }
440   void addu11_3ImmOperands(MCInst &Inst, unsigned N) const {
441     addImmOperands(Inst, N);
442   }
443   void addu10ImmOperands(MCInst &Inst, unsigned N) const {
444     addImmOperands(Inst, N);
445   }
446   void addu9ImmOperands(MCInst &Inst, unsigned N) const {
447     addImmOperands(Inst, N);
448   }
449   void addu8ImmOperands(MCInst &Inst, unsigned N) const {
450     addImmOperands(Inst, N);
451   }
452   void addu7ImmOperands(MCInst &Inst, unsigned N) const {
453     addImmOperands(Inst, N);
454   }
455   void addu6ImmOperands(MCInst &Inst, unsigned N) const {
456     addImmOperands(Inst, N);
457   }
458   void addu6_0ImmOperands(MCInst &Inst, unsigned N) const {
459     addImmOperands(Inst, N);
460   }
461   void addu6_1ImmOperands(MCInst &Inst, unsigned N) const {
462     addImmOperands(Inst, N);
463   }
464   void addu6_2ImmOperands(MCInst &Inst, unsigned N) const {
465     addImmOperands(Inst, N);
466   }
467   void addu6_3ImmOperands(MCInst &Inst, unsigned N) const {
468     addImmOperands(Inst, N);
469   }
470   void addu5ImmOperands(MCInst &Inst, unsigned N) const {
471     addImmOperands(Inst, N);
472   }
473   void addu4ImmOperands(MCInst &Inst, unsigned N) const {
474     addImmOperands(Inst, N);
475   }
476   void addu3ImmOperands(MCInst &Inst, unsigned N) const {
477     addImmOperands(Inst, N);
478   }
479   void addu2ImmOperands(MCInst &Inst, unsigned N) const {
480     addImmOperands(Inst, N);
481   }
482   void addu1ImmOperands(MCInst &Inst, unsigned N) const {
483     addImmOperands(Inst, N);
484   }
485 
486   void addm6ImmOperands(MCInst &Inst, unsigned N) const {
487     addImmOperands(Inst, N);
488   }
489   void addn8ImmOperands(MCInst &Inst, unsigned N) const {
490     addImmOperands(Inst, N);
491   }
492 
493   void adds16ExtOperands(MCInst &Inst, unsigned N) const {
494     addSignedImmOperands(Inst, N);
495   }
496   void adds12ExtOperands(MCInst &Inst, unsigned N) const {
497     addSignedImmOperands(Inst, N);
498   }
499   void adds10ExtOperands(MCInst &Inst, unsigned N) const {
500     addSignedImmOperands(Inst, N);
501   }
502   void adds9ExtOperands(MCInst &Inst, unsigned N) const {
503     addSignedImmOperands(Inst, N);
504   }
505   void adds8ExtOperands(MCInst &Inst, unsigned N) const {
506     addSignedImmOperands(Inst, N);
507   }
508   void adds6ExtOperands(MCInst &Inst, unsigned N) const {
509     addSignedImmOperands(Inst, N);
510   }
511   void adds11_0ExtOperands(MCInst &Inst, unsigned N) const {
512     addSignedImmOperands(Inst, N);
513   }
514   void adds11_1ExtOperands(MCInst &Inst, unsigned N) const {
515     addSignedImmOperands(Inst, N);
516   }
517   void adds11_2ExtOperands(MCInst &Inst, unsigned N) const {
518     addSignedImmOperands(Inst, N);
519   }
520   void adds11_3ExtOperands(MCInst &Inst, unsigned N) const {
521     addSignedImmOperands(Inst, N);
522   }
523 
524   void addu6ExtOperands(MCInst &Inst, unsigned N) const {
525     addImmOperands(Inst, N);
526   }
527   void addu7ExtOperands(MCInst &Inst, unsigned N) const {
528     addImmOperands(Inst, N);
529   }
530   void addu8ExtOperands(MCInst &Inst, unsigned N) const {
531     addImmOperands(Inst, N);
532   }
533   void addu9ExtOperands(MCInst &Inst, unsigned N) const {
534     addImmOperands(Inst, N);
535   }
536   void addu10ExtOperands(MCInst &Inst, unsigned N) const {
537     addImmOperands(Inst, N);
538   }
539   void addu6_0ExtOperands(MCInst &Inst, unsigned N) const {
540     addImmOperands(Inst, N);
541   }
542   void addu6_1ExtOperands(MCInst &Inst, unsigned N) const {
543     addImmOperands(Inst, N);
544   }
545   void addu6_2ExtOperands(MCInst &Inst, unsigned N) const {
546     addImmOperands(Inst, N);
547   }
548   void addu6_3ExtOperands(MCInst &Inst, unsigned N) const {
549     addImmOperands(Inst, N);
550   }
551   void addu32MustExtOperands(MCInst &Inst, unsigned N) const {
552     addImmOperands(Inst, N);
553   }
554 
555   void adds4_6ImmOperands(MCInst &Inst, unsigned N) const {
556     assert(N == 1 && "Invalid number of operands!");
557     const MCConstantExpr *CE =
558         dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm()));
559     Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
560   }
561 
562   void adds3_6ImmOperands(MCInst &Inst, unsigned N) const {
563     assert(N == 1 && "Invalid number of operands!");
564     const MCConstantExpr *CE =
565         dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm()));
566     Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
567   }
568 
569   StringRef getToken() const {
570     assert(Kind == Token && "Invalid access!");
571     return StringRef(Tok.Data, Tok.Length);
572   }
573 
574   virtual void print(raw_ostream &OS) const;
575 
576   static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) {
577     HexagonOperand *Op = new HexagonOperand(Token);
578     Op->Tok.Data = Str.data();
579     Op->Tok.Length = Str.size();
580     Op->StartLoc = S;
581     Op->EndLoc = S;
582     return std::unique_ptr<HexagonOperand>(Op);
583   }
584 
585   static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S,
586                                                    SMLoc E) {
587     HexagonOperand *Op = new HexagonOperand(Register);
588     Op->Reg.RegNum = RegNum;
589     Op->StartLoc = S;
590     Op->EndLoc = E;
591     return std::unique_ptr<HexagonOperand>(Op);
592   }
593 
594   static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S,
595                                                    SMLoc E) {
596     HexagonOperand *Op = new HexagonOperand(Immediate);
597     Op->Imm.Val = Val;
598     Op->StartLoc = S;
599     Op->EndLoc = E;
600     return std::unique_ptr<HexagonOperand>(Op);
601   }
602 };
603 
604 } // end anonymous namespace.
605 
606 void HexagonOperand::print(raw_ostream &OS) const {
607   switch (Kind) {
608   case Immediate:
609     getImm()->print(OS, nullptr);
610     break;
611   case Register:
612     OS << "<register R";
613     OS << getReg() << ">";
614     break;
615   case Token:
616     OS << "'" << getToken() << "'";
617     break;
618   }
619 }
620 
621 bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
622   DEBUG(dbgs() << "Bundle:");
623   DEBUG(MCB.dump_pretty(dbgs()));
624   DEBUG(dbgs() << "--\n");
625 
626   // Check the bundle for errors.
627   const MCRegisterInfo *RI = getContext().getRegisterInfo();
628   HexagonMCChecker Check(MCII, getSTI(), MCB, MCB, *RI);
629 
630   bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(),
631                                                         getContext(), MCB,
632                                                         &Check);
633 
634   while (Check.getNextErrInfo() == true) {
635     unsigned Reg = Check.getErrRegister();
636     Twine R(RI->getName(Reg));
637 
638     uint64_t Err = Check.getError();
639     if (Err != HexagonMCErrInfo::CHECK_SUCCESS) {
640       if (HexagonMCErrInfo::CHECK_ERROR_BRANCHES & Err)
641         Error(IDLoc,
642               "unconditional branch cannot precede another branch in packet");
643 
644       if (HexagonMCErrInfo::CHECK_ERROR_NEWP & Err ||
645           HexagonMCErrInfo::CHECK_ERROR_NEWV & Err)
646         Error(IDLoc, "register `" + R +
647                          "' used with `.new' "
648                          "but not validly modified in the same packet");
649 
650       if (HexagonMCErrInfo::CHECK_ERROR_REGISTERS & Err)
651         Error(IDLoc, "register `" + R + "' modified more than once");
652 
653       if (HexagonMCErrInfo::CHECK_ERROR_READONLY & Err)
654         Error(IDLoc, "cannot write to read-only register `" + R + "'");
655 
656       if (HexagonMCErrInfo::CHECK_ERROR_LOOP & Err)
657         Error(IDLoc, "loop-setup and some branch instructions "
658                      "cannot be in the same packet");
659 
660       if (HexagonMCErrInfo::CHECK_ERROR_ENDLOOP & Err) {
661         Twine N(HexagonMCInstrInfo::isInnerLoop(MCB) ? '0' : '1');
662         Error(IDLoc, "packet marked with `:endloop" + N + "' " +
663                          "cannot contain instructions that modify register " +
664                          "`" + R + "'");
665       }
666 
667       if (HexagonMCErrInfo::CHECK_ERROR_SOLO & Err)
668         Error(IDLoc,
669               "instruction cannot appear in packet with other instructions");
670 
671       if (HexagonMCErrInfo::CHECK_ERROR_NOSLOTS & Err)
672         Error(IDLoc, "too many slots used in packet");
673 
674       if (Err & HexagonMCErrInfo::CHECK_ERROR_SHUFFLE) {
675         uint64_t Erm = Check.getShuffleError();
676 
677         if (HexagonShuffler::SHUFFLE_ERROR_INVALID == Erm)
678           Error(IDLoc, "invalid instruction packet");
679         else if (HexagonShuffler::SHUFFLE_ERROR_STORES == Erm)
680           Error(IDLoc, "invalid instruction packet: too many stores");
681         else if (HexagonShuffler::SHUFFLE_ERROR_LOADS == Erm)
682           Error(IDLoc, "invalid instruction packet: too many loads");
683         else if (HexagonShuffler::SHUFFLE_ERROR_BRANCHES == Erm)
684           Error(IDLoc, "too many branches in packet");
685         else if (HexagonShuffler::SHUFFLE_ERROR_NOSLOTS == Erm)
686           Error(IDLoc, "invalid instruction packet: out of slots");
687         else if (HexagonShuffler::SHUFFLE_ERROR_SLOTS == Erm)
688           Error(IDLoc, "invalid instruction packet: slot error");
689         else if (HexagonShuffler::SHUFFLE_ERROR_ERRATA2 == Erm)
690           Error(IDLoc, "v60 packet violation");
691         else if (HexagonShuffler::SHUFFLE_ERROR_STORE_LOAD_CONFLICT == Erm)
692           Error(IDLoc, "slot 0 instruction does not allow slot 1 store");
693         else
694           Error(IDLoc, "unknown error in instruction packet");
695       }
696     }
697 
698     unsigned Warn = Check.getWarning();
699     if (Warn != HexagonMCErrInfo::CHECK_SUCCESS) {
700       if (HexagonMCErrInfo::CHECK_WARN_CURRENT & Warn)
701         Warning(IDLoc, "register `" + R + "' used with `.cur' "
702                                           "but not used in the same packet");
703       else if (HexagonMCErrInfo::CHECK_WARN_TEMPORARY & Warn)
704         Warning(IDLoc, "register `" + R + "' used with `.tmp' "
705                                           "but not used in the same packet");
706     }
707   }
708 
709   if (CheckOk) {
710     MCB.setLoc(IDLoc);
711     if (HexagonMCInstrInfo::bundleSize(MCB) == 0) {
712       assert(!HexagonMCInstrInfo::isInnerLoop(MCB));
713       assert(!HexagonMCInstrInfo::isOuterLoop(MCB));
714       // Empty packets are valid yet aren't emitted
715       return false;
716     }
717     Out.EmitInstruction(MCB, getSTI());
718   } else {
719     // If compounding and duplexing didn't reduce the size below
720     // 4 or less we have a packet that is too big.
721     if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {
722       Error(IDLoc, "invalid instruction packet: out of slots");
723       return true; // Error
724     }
725   }
726 
727   return false; // No error
728 }
729 
730 bool HexagonAsmParser::matchBundleOptions() {
731   MCAsmParser &Parser = getParser();
732   MCAsmLexer &Lexer = getLexer();
733   while (true) {
734     if (!Parser.getTok().is(AsmToken::Colon))
735       return false;
736     Lexer.Lex();
737     StringRef Option = Parser.getTok().getString();
738     if (Option.compare_lower("endloop0") == 0)
739       HexagonMCInstrInfo::setInnerLoop(MCB);
740     else if (Option.compare_lower("endloop1") == 0)
741       HexagonMCInstrInfo::setOuterLoop(MCB);
742     else if (Option.compare_lower("mem_noshuf") == 0)
743       HexagonMCInstrInfo::setMemReorderDisabled(MCB);
744     else if (Option.compare_lower("mem_shuf") == 0)
745       HexagonMCInstrInfo::setMemStoreReorderEnabled(MCB);
746     else
747       return true;
748     Lexer.Lex();
749   }
750 }
751 
752 // For instruction aliases, immediates are generated rather than
753 // MCConstantExpr.  Convert them for uniform MCExpr.
754 // Also check for signed/unsigned mismatches and warn
755 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
756   MCInst NewInst;
757   NewInst.setOpcode(MCI.getOpcode());
758   for (MCOperand &I : MCI)
759     if (I.isImm()) {
760       int64_t Value (I.getImm());
761       NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
762           MCConstantExpr::create(Value, getContext()), getContext())));
763     }
764     else {
765       if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() &&
766           WarnSignedMismatch)
767         Warning (MCI.getLoc(), "Signed/Unsigned mismatch");
768       NewInst.addOperand(I);
769     }
770   MCI = NewInst;
771 }
772 
773 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
774                                            OperandVector &InstOperands,
775                                            uint64_t &ErrorInfo,
776                                            bool MatchingInlineAsm) {
777   // Perform matching with tablegen asmmatcher generated function
778   int result =
779       MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);
780   if (result == Match_Success) {
781     MCI.setLoc(IDLoc);
782     canonicalizeImmediates(MCI);
783     result = processInstruction(MCI, InstOperands, IDLoc);
784 
785     DEBUG(dbgs() << "Insn:");
786     DEBUG(MCI.dump_pretty(dbgs()));
787     DEBUG(dbgs() << "\n\n");
788 
789     MCI.setLoc(IDLoc);
790   }
791 
792   // Create instruction operand for bundle instruction
793   //   Break this into a separate function Code here is less readable
794   //   Think about how to get an instruction error to report correctly.
795   //   SMLoc will return the "{"
796   switch (result) {
797   default:
798     break;
799   case Match_Success:
800     return false;
801   case Match_MissingFeature:
802     return Error(IDLoc, "invalid instruction");
803   case Match_MnemonicFail:
804     return Error(IDLoc, "unrecognized instruction");
805   case Match_InvalidOperand:
806     SMLoc ErrorLoc = IDLoc;
807     if (ErrorInfo != ~0U) {
808       if (ErrorInfo >= InstOperands.size())
809         return Error(IDLoc, "too few operands for instruction");
810 
811       ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get()))
812                      ->getStartLoc();
813       if (ErrorLoc == SMLoc())
814         ErrorLoc = IDLoc;
815     }
816     return Error(ErrorLoc, "invalid operand for instruction");
817   }
818   llvm_unreachable("Implement any new match types added!");
819 }
820 
821 bool HexagonAsmParser::mustExtend(OperandVector &Operands) {
822   unsigned Count = 0;
823   for (std::unique_ptr<MCParsedAsmOperand> &i : Operands)
824     if (i->isImm())
825       if (HexagonMCInstrInfo::mustExtend(
826               *static_cast<HexagonOperand *>(i.get())->Imm.Val))
827         ++Count;
828   // Multiple extenders should have been filtered by iss9Ext et. al.
829   assert(Count < 2 && "Multiple extenders");
830   return Count == 1;
831 }
832 
833 bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
834                                                OperandVector &Operands,
835                                                MCStreamer &Out,
836                                                uint64_t &ErrorInfo,
837                                                bool MatchingInlineAsm) {
838   if (!InBrackets) {
839     MCB.clear();
840     MCB.addOperand(MCOperand::createImm(0));
841   }
842   HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]);
843   if (FirstOperand.isToken() && FirstOperand.getToken() == "{") {
844     assert(Operands.size() == 1 && "Brackets should be by themselves");
845     if (InBrackets) {
846       getParser().Error(IDLoc, "Already in a packet");
847       return true;
848     }
849     InBrackets = true;
850     return false;
851   }
852   if (FirstOperand.isToken() && FirstOperand.getToken() == "}") {
853     assert(Operands.size() == 1 && "Brackets should be by themselves");
854     if (!InBrackets) {
855       getParser().Error(IDLoc, "Not in a packet");
856       return true;
857     }
858     InBrackets = false;
859     if (matchBundleOptions())
860       return true;
861     return finishBundle(IDLoc, Out);
862   }
863   MCInst *SubInst = new (getParser().getContext()) MCInst;
864   if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
865                           MatchingInlineAsm))
866     return true;
867   HexagonMCInstrInfo::extendIfNeeded(
868       getParser().getContext(), MCII, MCB, *SubInst);
869   MCB.addOperand(MCOperand::createInst(SubInst));
870   if (!InBrackets)
871     return finishBundle(IDLoc, Out);
872   return false;
873 }
874 
875 /// ParseDirective parses the Hexagon specific directives
876 bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
877   StringRef IDVal = DirectiveID.getIdentifier();
878   if ((IDVal.lower() == ".word") || (IDVal.lower() == ".4byte"))
879     return ParseDirectiveValue(4, DirectiveID.getLoc());
880   if (IDVal.lower() == ".short" || IDVal.lower() == ".hword" ||
881       IDVal.lower() == ".half")
882     return ParseDirectiveValue(2, DirectiveID.getLoc());
883   if (IDVal.lower() == ".falign")
884     return ParseDirectiveFalign(256, DirectiveID.getLoc());
885   if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon"))
886     return ParseDirectiveComm(true, DirectiveID.getLoc());
887   if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common"))
888     return ParseDirectiveComm(false, DirectiveID.getLoc());
889   if (IDVal.lower() == ".subsection")
890     return ParseDirectiveSubsection(DirectiveID.getLoc());
891 
892   return true;
893 }
894 bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) {
895   const MCExpr *Subsection = 0;
896   int64_t Res;
897 
898   assert((getLexer().isNot(AsmToken::EndOfStatement)) &&
899          "Invalid subsection directive");
900   getParser().parseExpression(Subsection);
901 
902   if (!Subsection->evaluateAsAbsolute(Res))
903     return Error(L, "Cannot evaluate subsection number");
904 
905   if (getLexer().isNot(AsmToken::EndOfStatement))
906     return TokError("unexpected token in directive");
907 
908   // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the
909   // negative subsections together and in the same order but at the opposite
910   // end of the section.  Only legacy hexagon-gcc created assembly code
911   // used negative subsections.
912   if ((Res < 0) && (Res > -8193))
913     Subsection = HexagonMCExpr::create(
914         MCConstantExpr::create(8192 + Res, getContext()), getContext());
915 
916   getStreamer().SubSection(Subsection);
917   return false;
918 }
919 
920 ///  ::= .falign [expression]
921 bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) {
922 
923   int64_t MaxBytesToFill = 15;
924 
925   // if there is an arguement
926   if (getLexer().isNot(AsmToken::EndOfStatement)) {
927     const MCExpr *Value;
928     SMLoc ExprLoc = L;
929 
930     // Make sure we have a number (false is returned if expression is a number)
931     if (getParser().parseExpression(Value) == false) {
932       // Make sure this is a number that is in range
933       const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value);
934       uint64_t IntValue = MCE->getValue();
935       if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue))
936         return Error(ExprLoc, "literal value out of range (256) for falign");
937       MaxBytesToFill = IntValue;
938       Lex();
939     } else {
940       return Error(ExprLoc, "not a valid expression for falign directive");
941     }
942   }
943 
944   getTargetStreamer().emitFAlign(16, MaxBytesToFill);
945   Lex();
946 
947   return false;
948 }
949 
950 ///  ::= .word [ expression (, expression)* ]
951 bool HexagonAsmParser::ParseDirectiveValue(unsigned Size, SMLoc L) {
952   if (getLexer().isNot(AsmToken::EndOfStatement)) {
953 
954     for (;;) {
955       const MCExpr *Value;
956       SMLoc ExprLoc = L;
957       if (getParser().parseExpression(Value))
958         return true;
959 
960       // Special case constant expressions to match code generator.
961       if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value)) {
962         assert(Size <= 8 && "Invalid size");
963         uint64_t IntValue = MCE->getValue();
964         if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
965           return Error(ExprLoc, "literal value out of range for directive");
966         getStreamer().EmitIntValue(IntValue, Size);
967       } else
968         getStreamer().EmitValue(Value, Size);
969 
970       if (getLexer().is(AsmToken::EndOfStatement))
971         break;
972 
973       // FIXME: Improve diagnostic.
974       if (getLexer().isNot(AsmToken::Comma))
975         return TokError("unexpected token in directive");
976       Lex();
977     }
978   }
979 
980   Lex();
981   return false;
982 }
983 
984 // This is largely a copy of AsmParser's ParseDirectiveComm extended to
985 // accept a 3rd argument, AccessAlignment which indicates the smallest
986 // memory access made to the symbol, expressed in bytes.  If no
987 // AccessAlignment is specified it defaults to the Alignment Value.
988 // Hexagon's .lcomm:
989 //   .lcomm Symbol, Length, Alignment, AccessAlignment
990 bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
991   // FIXME: need better way to detect if AsmStreamer (upstream removed
992   // getKind())
993   if (getStreamer().hasRawTextSupport())
994     return true; // Only object file output requires special treatment.
995 
996   StringRef Name;
997   if (getParser().parseIdentifier(Name))
998     return TokError("expected identifier in directive");
999   // Handle the identifier as the key symbol.
1000   MCSymbol *Sym = getContext().getOrCreateSymbol(Name);
1001 
1002   if (getLexer().isNot(AsmToken::Comma))
1003     return TokError("unexpected token in directive");
1004   Lex();
1005 
1006   int64_t Size;
1007   SMLoc SizeLoc = getLexer().getLoc();
1008   if (getParser().parseAbsoluteExpression(Size))
1009     return true;
1010 
1011   int64_t ByteAlignment = 1;
1012   SMLoc ByteAlignmentLoc;
1013   if (getLexer().is(AsmToken::Comma)) {
1014     Lex();
1015     ByteAlignmentLoc = getLexer().getLoc();
1016     if (getParser().parseAbsoluteExpression(ByteAlignment))
1017       return true;
1018     if (!isPowerOf2_64(ByteAlignment))
1019       return Error(ByteAlignmentLoc, "alignment must be a power of 2");
1020   }
1021 
1022   int64_t AccessAlignment = 0;
1023   if (getLexer().is(AsmToken::Comma)) {
1024     // The optional access argument specifies the size of the smallest memory
1025     //   access to be made to the symbol, expressed in bytes.
1026     SMLoc AccessAlignmentLoc;
1027     Lex();
1028     AccessAlignmentLoc = getLexer().getLoc();
1029     if (getParser().parseAbsoluteExpression(AccessAlignment))
1030       return true;
1031 
1032     if (!isPowerOf2_64(AccessAlignment))
1033       return Error(AccessAlignmentLoc, "access alignment must be a power of 2");
1034   }
1035 
1036   if (getLexer().isNot(AsmToken::EndOfStatement))
1037     return TokError("unexpected token in '.comm' or '.lcomm' directive");
1038 
1039   Lex();
1040 
1041   // NOTE: a size of zero for a .comm should create a undefined symbol
1042   // but a size of .lcomm creates a bss symbol of size zero.
1043   if (Size < 0)
1044     return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't "
1045                           "be less than zero");
1046 
1047   // NOTE: The alignment in the directive is a power of 2 value, the assembler
1048   // may internally end up wanting an alignment in bytes.
1049   // FIXME: Diagnose overflow.
1050   if (ByteAlignment < 0)
1051     return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive "
1052                                    "alignment, can't be less than zero");
1053 
1054   if (!Sym->isUndefined())
1055     return Error(Loc, "invalid symbol redefinition");
1056 
1057   HexagonMCELFStreamer &HexagonELFStreamer =
1058       static_cast<HexagonMCELFStreamer &>(getStreamer());
1059   if (IsLocal) {
1060     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment,
1061                                                       AccessAlignment);
1062     return false;
1063   }
1064 
1065   HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment,
1066                                                AccessAlignment);
1067   return false;
1068 }
1069 
1070 // validate register against architecture
1071 bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
1072   return true;
1073 }
1074 
1075 // extern "C" void LLVMInitializeHexagonAsmLexer();
1076 
1077 /// Force static initialization.
1078 extern "C" void LLVMInitializeHexagonAsmParser() {
1079   RegisterMCAsmParser<HexagonAsmParser> X(TheHexagonTarget);
1080 }
1081 
1082 #define GET_MATCHER_IMPLEMENTATION
1083 #define GET_REGISTER_MATCHER
1084 #include "HexagonGenAsmMatcher.inc"
1085 
1086 namespace {
1087 bool previousEqual(OperandVector &Operands, size_t Index, StringRef String) {
1088   if (Index >= Operands.size())
1089     return false;
1090   MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1];
1091   if (!Operand.isToken())
1092     return false;
1093   return static_cast<HexagonOperand &>(Operand).getToken().equals_lower(String);
1094 }
1095 bool previousIsLoop(OperandVector &Operands, size_t Index) {
1096   return previousEqual(Operands, Index, "loop0") ||
1097          previousEqual(Operands, Index, "loop1") ||
1098          previousEqual(Operands, Index, "sp1loop0") ||
1099          previousEqual(Operands, Index, "sp2loop0") ||
1100          previousEqual(Operands, Index, "sp3loop0");
1101 }
1102 }
1103 
1104 bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {
1105   AsmToken const &Token = getParser().getTok();
1106   StringRef String = Token.getString();
1107   SMLoc Loc = Token.getLoc();
1108   getLexer().Lex();
1109   do {
1110     std::pair<StringRef, StringRef> HeadTail = String.split('.');
1111     if (!HeadTail.first.empty())
1112       Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc));
1113     if (!HeadTail.second.empty())
1114       Operands.push_back(HexagonOperand::CreateToken(
1115           String.substr(HeadTail.first.size(), 1), Loc));
1116     String = HeadTail.second;
1117   } while (!String.empty());
1118   return false;
1119 }
1120 
1121 bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
1122   unsigned Register;
1123   SMLoc Begin;
1124   SMLoc End;
1125   MCAsmLexer &Lexer = getLexer();
1126   if (!ParseRegister(Register, Begin, End)) {
1127     if (!ErrorMissingParenthesis)
1128       switch (Register) {
1129       default:
1130         break;
1131       case Hexagon::P0:
1132       case Hexagon::P1:
1133       case Hexagon::P2:
1134       case Hexagon::P3:
1135         if (previousEqual(Operands, 0, "if")) {
1136           if (WarnMissingParenthesis)
1137             Warning (Begin, "Missing parenthesis around predicate register");
1138           static char const *LParen = "(";
1139           static char const *RParen = ")";
1140           Operands.push_back(HexagonOperand::CreateToken(LParen, Begin));
1141           Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
1142           AsmToken MaybeDotNew = Lexer.getTok();
1143           if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
1144               MaybeDotNew.getString().equals_lower(".new"))
1145             splitIdentifier(Operands);
1146           Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
1147           return false;
1148         }
1149         if (previousEqual(Operands, 0, "!") &&
1150             previousEqual(Operands, 1, "if")) {
1151           if (WarnMissingParenthesis)
1152             Warning (Begin, "Missing parenthesis around predicate register");
1153           static char const *LParen = "(";
1154           static char const *RParen = ")";
1155           Operands.insert(Operands.end () - 1,
1156                           HexagonOperand::CreateToken(LParen, Begin));
1157           Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End));
1158           AsmToken MaybeDotNew = Lexer.getTok();
1159           if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
1160               MaybeDotNew.getString().equals_lower(".new"))
1161             splitIdentifier(Operands);
1162           Operands.push_back(HexagonOperand::CreateToken(RParen, Begin));
1163           return false;
1164         }
1165         break;
1166       }
1167     Operands.push_back(HexagonOperand::CreateReg(
1168         Register, Begin, End));
1169     return false;
1170   }
1171   return splitIdentifier(Operands);
1172 }
1173 
1174 bool HexagonAsmParser::isLabel(AsmToken &Token) {
1175   MCAsmLexer &Lexer = getLexer();
1176   AsmToken const &Second = Lexer.getTok();
1177   AsmToken Third = Lexer.peekTok();
1178   StringRef String = Token.getString();
1179   if (Token.is(AsmToken::TokenKind::LCurly) ||
1180       Token.is(AsmToken::TokenKind::RCurly))
1181     return false;
1182   if (!Token.is(AsmToken::TokenKind::Identifier))
1183     return true;
1184   if (!matchRegister(String.lower()))
1185     return true;
1186   (void)Second;
1187   assert(Second.is(AsmToken::Colon));
1188   StringRef Raw (String.data(), Third.getString().data() - String.data() +
1189                  Third.getString().size());
1190   std::string Collapsed = Raw;
1191   Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace),
1192                   Collapsed.end());
1193   StringRef Whole = Collapsed;
1194   std::pair<StringRef, StringRef> DotSplit = Whole.split('.');
1195   if (!matchRegister(DotSplit.first.lower()))
1196     return true;
1197   return false;
1198 }
1199 
1200 bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) {
1201   if (!Contigious && ErrorNoncontigiousRegister) {
1202     Error(Loc, "Register name is not contigious");
1203     return true;
1204   }
1205   if (!Contigious && WarnNoncontigiousRegister)
1206     Warning(Loc, "Register name is not contigious");
1207   return false;
1208 }
1209 
1210 bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1211   MCAsmLexer &Lexer = getLexer();
1212   StartLoc = getLexer().getLoc();
1213   SmallVector<AsmToken, 5> Lookahead;
1214   StringRef RawString(Lexer.getTok().getString().data(), 0);
1215   bool Again = Lexer.is(AsmToken::Identifier);
1216   bool NeededWorkaround = false;
1217   while (Again) {
1218     AsmToken const &Token = Lexer.getTok();
1219     RawString = StringRef(RawString.data(),
1220                           Token.getString().data() - RawString.data () +
1221                           Token.getString().size());
1222     Lookahead.push_back(Token);
1223     Lexer.Lex();
1224     bool Contigious = Lexer.getTok().getString().data() ==
1225                       Lookahead.back().getString().data() +
1226                       Lookahead.back().getString().size();
1227     bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||
1228                 Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
1229                 Lexer.is(AsmToken::Colon);
1230     bool Workaround = Lexer.is(AsmToken::Colon) ||
1231                       Lookahead.back().is(AsmToken::Colon);
1232     Again = (Contigious && Type) || (Workaround && Type);
1233     NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));
1234   }
1235   std::string Collapsed = RawString;
1236   Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace),
1237                   Collapsed.end());
1238   StringRef FullString = Collapsed;
1239   std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
1240   unsigned DotReg = matchRegister(DotSplit.first.lower());
1241   if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1242     if (DotSplit.second.empty()) {
1243       RegNo = DotReg;
1244       EndLoc = Lexer.getLoc();
1245       if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1246         return true;
1247       return false;
1248     } else {
1249       RegNo = DotReg;
1250       size_t First = RawString.find('.');
1251       StringRef DotString (RawString.data() + First, RawString.size() - First);
1252       Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString));
1253       EndLoc = Lexer.getLoc();
1254       if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1255         return true;
1256       return false;
1257     }
1258   }
1259   std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
1260   unsigned ColonReg = matchRegister(ColonSplit.first.lower());
1261   if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1262     Lexer.UnLex(Lookahead.back());
1263     Lookahead.pop_back();
1264     Lexer.UnLex(Lookahead.back());
1265     Lookahead.pop_back();
1266     RegNo = ColonReg;
1267     EndLoc = Lexer.getLoc();
1268     if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1269       return true;
1270     return false;
1271   }
1272   while (!Lookahead.empty()) {
1273     Lexer.UnLex(Lookahead.back());
1274     Lookahead.pop_back();
1275   }
1276   return true;
1277 }
1278 
1279 bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) {
1280   if (previousEqual(Operands, 0, "call"))
1281     return true;
1282   if (previousEqual(Operands, 0, "jump"))
1283     if (!getLexer().getTok().is(AsmToken::Colon))
1284       return true;
1285   if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1))
1286     return true;
1287   if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") &&
1288       (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t")))
1289     return true;
1290   return false;
1291 }
1292 
1293 bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) {
1294   llvm::SmallVector<AsmToken, 4> Tokens;
1295   MCAsmLexer &Lexer = getLexer();
1296   bool Done = false;
1297   static char const * Comma = ",";
1298   do {
1299     Tokens.emplace_back (Lexer.getTok());
1300     Lexer.Lex();
1301     switch (Tokens.back().getKind())
1302     {
1303     case AsmToken::TokenKind::Hash:
1304       if (Tokens.size () > 1)
1305         if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) {
1306           Tokens.insert(Tokens.end() - 2,
1307                         AsmToken(AsmToken::TokenKind::Comma, Comma));
1308           Done = true;
1309         }
1310       break;
1311     case AsmToken::TokenKind::RCurly:
1312     case AsmToken::TokenKind::EndOfStatement:
1313     case AsmToken::TokenKind::Eof:
1314       Done = true;
1315       break;
1316     default:
1317       break;
1318     }
1319   } while (!Done);
1320   while (!Tokens.empty()) {
1321     Lexer.UnLex(Tokens.back());
1322     Tokens.pop_back();
1323   }
1324   return getParser().parseExpression(Expr);
1325 }
1326 
1327 bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
1328   if (implicitExpressionLocation(Operands)) {
1329     MCAsmParser &Parser = getParser();
1330     SMLoc Loc = Parser.getLexer().getLoc();
1331     MCExpr const *Expr = nullptr;
1332     bool Error = parseExpression(Expr);
1333     Expr = HexagonMCExpr::create(Expr, getContext());
1334     if (!Error)
1335       Operands.push_back(HexagonOperand::CreateImm(Expr, Loc, Loc));
1336     return Error;
1337   }
1338   return parseOperand(Operands);
1339 }
1340 
1341 /// Parse an instruction.
1342 bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
1343   MCAsmParser &Parser = getParser();
1344   MCAsmLexer &Lexer = getLexer();
1345   while (true) {
1346     AsmToken const &Token = Parser.getTok();
1347     switch (Token.getKind()) {
1348     case AsmToken::EndOfStatement: {
1349       Lexer.Lex();
1350       return false;
1351     }
1352     case AsmToken::LCurly: {
1353       if (!Operands.empty())
1354         return true;
1355       Operands.push_back(
1356           HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1357       Lexer.Lex();
1358       return false;
1359     }
1360     case AsmToken::RCurly: {
1361       if (Operands.empty()) {
1362         Operands.push_back(
1363             HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1364         Lexer.Lex();
1365       }
1366       return false;
1367     }
1368     case AsmToken::Comma: {
1369       Lexer.Lex();
1370       continue;
1371     }
1372     case AsmToken::EqualEqual:
1373     case AsmToken::ExclaimEqual:
1374     case AsmToken::GreaterEqual:
1375     case AsmToken::GreaterGreater:
1376     case AsmToken::LessEqual:
1377     case AsmToken::LessLess: {
1378       Operands.push_back(HexagonOperand::CreateToken(
1379           Token.getString().substr(0, 1), Token.getLoc()));
1380       Operands.push_back(HexagonOperand::CreateToken(
1381           Token.getString().substr(1, 1), Token.getLoc()));
1382       Lexer.Lex();
1383       continue;
1384     }
1385     case AsmToken::Hash: {
1386       bool MustNotExtend = false;
1387       bool ImplicitExpression = implicitExpressionLocation(Operands);
1388       SMLoc ExprLoc = Lexer.getLoc();
1389       if (!ImplicitExpression)
1390         Operands.push_back(
1391           HexagonOperand::CreateToken(Token.getString(), Token.getLoc()));
1392       Lexer.Lex();
1393       bool MustExtend = false;
1394       bool HiOnly = false;
1395       bool LoOnly = false;
1396       if (Lexer.is(AsmToken::Hash)) {
1397         Lexer.Lex();
1398         MustExtend = true;
1399       } else if (ImplicitExpression)
1400         MustNotExtend = true;
1401       AsmToken const &Token = Parser.getTok();
1402       if (Token.is(AsmToken::Identifier)) {
1403         StringRef String = Token.getString();
1404         AsmToken IDToken = Token;
1405         if (String.lower() == "hi") {
1406           HiOnly = true;
1407         } else if (String.lower() == "lo") {
1408           LoOnly = true;
1409         }
1410         if (HiOnly || LoOnly) {
1411           AsmToken LParen = Lexer.peekTok();
1412           if (!LParen.is(AsmToken::LParen)) {
1413             HiOnly = false;
1414             LoOnly = false;
1415           } else {
1416             Lexer.Lex();
1417           }
1418         }
1419       }
1420       MCExpr const *Expr = nullptr;
1421       if (parseExpression(Expr))
1422         return true;
1423       int64_t Value;
1424       MCContext &Context = Parser.getContext();
1425       assert(Expr != nullptr);
1426       if (Expr->evaluateAsAbsolute(Value)) {
1427         if (HiOnly)
1428           Expr = MCBinaryExpr::createLShr(
1429               Expr,  MCConstantExpr::create(16, Context), Context);
1430         if (HiOnly || LoOnly)
1431           Expr = MCBinaryExpr::createAnd(Expr,
1432               MCConstantExpr::create(0xffff, Context),
1433                                     Context);
1434       } else {
1435         MCValue Value;
1436         if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) {
1437           if (!Value.isAbsolute()) {
1438             switch(Value.getAccessVariant()) {
1439             case MCSymbolRefExpr::VariantKind::VK_TPREL:
1440             case MCSymbolRefExpr::VariantKind::VK_DTPREL:
1441               // Don't lazy extend these expression variants
1442               MustNotExtend = !MustExtend;
1443               break;
1444             default:
1445               break;
1446             }
1447           }
1448         }
1449       }
1450       Expr = HexagonMCExpr::create(Expr, Context);
1451       HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);
1452       HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
1453       std::unique_ptr<HexagonOperand> Operand =
1454           HexagonOperand::CreateImm(Expr, ExprLoc, ExprLoc);
1455       Operands.push_back(std::move(Operand));
1456       continue;
1457     }
1458     default:
1459       break;
1460     }
1461     if (parseExpressionOrOperand(Operands))
1462       return true;
1463   }
1464 }
1465 
1466 bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1467                                         StringRef Name,
1468                                         AsmToken ID,
1469                                         OperandVector &Operands) {
1470   getLexer().UnLex(ID);
1471   return parseInstruction(Operands);
1472 }
1473 
1474 namespace {
1475 MCInst makeCombineInst(int opCode, MCOperand &Rdd,
1476                        MCOperand &MO1, MCOperand &MO2) {
1477   MCInst TmpInst;
1478   TmpInst.setOpcode(opCode);
1479   TmpInst.addOperand(Rdd);
1480   TmpInst.addOperand(MO1);
1481   TmpInst.addOperand(MO2);
1482 
1483   return TmpInst;
1484 }
1485 }
1486 
1487 // Define this matcher function after the auto-generated include so we
1488 // have the match class enum definitions.
1489 unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1490                                                       unsigned Kind) {
1491   HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp);
1492 
1493   switch (Kind) {
1494   case MCK_0: {
1495     int64_t Value;
1496     return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0
1497                ? Match_Success
1498                : Match_InvalidOperand;
1499   }
1500   case MCK_1: {
1501     int64_t Value;
1502     return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1
1503                ? Match_Success
1504                : Match_InvalidOperand;
1505   }
1506   case MCK__MINUS_1: {
1507     int64_t Value;
1508     return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == -1
1509                ? Match_Success
1510                : Match_InvalidOperand;
1511   }
1512   }
1513   if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) {
1514     StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length);
1515     if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind)
1516       return Match_Success;
1517     if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind)
1518       return Match_Success;
1519   }
1520 
1521   DEBUG(dbgs() << "Unmatched Operand:");
1522   DEBUG(Op->dump());
1523   DEBUG(dbgs() << "\n");
1524 
1525   return Match_InvalidOperand;
1526 }
1527 
1528 void HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
1529   std::string errStr;
1530   raw_string_ostream ES(errStr);
1531   ES << "value " << Val << "(" << format_hex(Val, 0) << ") out of range: ";
1532   if (Max >= 0)
1533     ES << "0-" << Max;
1534   else
1535     ES << Max << "-" << (-Max - 1);
1536   Error(IDLoc, ES.str().c_str());
1537 }
1538 
1539 int HexagonAsmParser::processInstruction(MCInst &Inst,
1540                                          OperandVector const &Operands,
1541                                          SMLoc IDLoc) {
1542   MCContext &Context = getParser().getContext();
1543   const MCRegisterInfo *RI = getContext().getRegisterInfo();
1544   std::string r = "r";
1545   std::string v = "v";
1546   std::string Colon = ":";
1547 
1548   bool is32bit = false; // used to distinguish between CONST32 and CONST64
1549   switch (Inst.getOpcode()) {
1550   default:
1551     break;
1552 
1553   case Hexagon::A2_iconst: {
1554     Inst.setOpcode(Hexagon::A2_addi);
1555     MCOperand Reg = Inst.getOperand(0);
1556     MCOperand S16 = Inst.getOperand(1);
1557     HexagonMCInstrInfo::setMustNotExtend(*S16.getExpr());
1558     HexagonMCInstrInfo::setS23_2_reloc(*S16.getExpr());
1559     Inst.clear();
1560     Inst.addOperand(Reg);
1561     Inst.addOperand(MCOperand::createReg(Hexagon::R0));
1562     Inst.addOperand(S16);
1563     break;
1564   }
1565   case Hexagon::M4_mpyrr_addr:
1566   case Hexagon::S4_addi_asl_ri:
1567   case Hexagon::S4_addi_lsr_ri:
1568   case Hexagon::S4_andi_asl_ri:
1569   case Hexagon::S4_andi_lsr_ri:
1570   case Hexagon::S4_ori_asl_ri:
1571   case Hexagon::S4_ori_lsr_ri:
1572   case Hexagon::S4_or_andix:
1573   case Hexagon::S4_subi_asl_ri:
1574   case Hexagon::S4_subi_lsr_ri: {
1575     MCOperand &Ry = Inst.getOperand(0);
1576     MCOperand &src = Inst.getOperand(2);
1577     if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg()))
1578       return Match_InvalidOperand;
1579     break;
1580   }
1581 
1582   case Hexagon::C2_cmpgei: {
1583     MCOperand &MO = Inst.getOperand(2);
1584     MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1585         MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
1586     Inst.setOpcode(Hexagon::C2_cmpgti);
1587     break;
1588   }
1589 
1590   case Hexagon::C2_cmpgeui: {
1591     MCOperand &MO = Inst.getOperand(2);
1592     int64_t Value;
1593     bool Success = MO.getExpr()->evaluateAsAbsolute(Value);
1594     (void)Success;
1595     assert(Success && "Assured by matcher");
1596     if (Value == 0) {
1597       MCInst TmpInst;
1598       MCOperand &Pd = Inst.getOperand(0);
1599       MCOperand &Rt = Inst.getOperand(1);
1600       TmpInst.setOpcode(Hexagon::C2_cmpeq);
1601       TmpInst.addOperand(Pd);
1602       TmpInst.addOperand(Rt);
1603       TmpInst.addOperand(Rt);
1604       Inst = TmpInst;
1605     } else {
1606       MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1607           MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
1608       Inst.setOpcode(Hexagon::C2_cmpgtui);
1609     }
1610     break;
1611   }
1612 
1613   // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1614   case Hexagon::A2_tfrp: {
1615     MCOperand &MO = Inst.getOperand(1);
1616     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1617     std::string R1 = r + llvm::utostr(RegPairNum + 1);
1618     StringRef Reg1(R1);
1619     MO.setReg(matchRegister(Reg1));
1620     // Add a new operand for the second register in the pair.
1621     std::string R2 = r + llvm::utostr(RegPairNum);
1622     StringRef Reg2(R2);
1623     Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1624     Inst.setOpcode(Hexagon::A2_combinew);
1625     break;
1626   }
1627 
1628   case Hexagon::A2_tfrpt:
1629   case Hexagon::A2_tfrpf: {
1630     MCOperand &MO = Inst.getOperand(2);
1631     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1632     std::string R1 = r + llvm::utostr(RegPairNum + 1);
1633     StringRef Reg1(R1);
1634     MO.setReg(matchRegister(Reg1));
1635     // Add a new operand for the second register in the pair.
1636     std::string R2 = r + llvm::utostr(RegPairNum);
1637     StringRef Reg2(R2);
1638     Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1639     Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
1640                        ? Hexagon::C2_ccombinewt
1641                        : Hexagon::C2_ccombinewf);
1642     break;
1643   }
1644   case Hexagon::A2_tfrptnew:
1645   case Hexagon::A2_tfrpfnew: {
1646     MCOperand &MO = Inst.getOperand(2);
1647     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1648     std::string R1 = r + llvm::utostr(RegPairNum + 1);
1649     StringRef Reg1(R1);
1650     MO.setReg(matchRegister(Reg1));
1651     // Add a new operand for the second register in the pair.
1652     std::string R2 = r + llvm::utostr(RegPairNum);
1653     StringRef Reg2(R2);
1654     Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1655     Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
1656                        ? Hexagon::C2_ccombinewnewt
1657                        : Hexagon::C2_ccombinewnewf);
1658     break;
1659   }
1660 
1661   // Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)"
1662   case Hexagon::HEXAGON_V6_vassignpair: {
1663     MCOperand &MO = Inst.getOperand(1);
1664     unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1665     std::string R1 = v + llvm::utostr(RegPairNum + 1);
1666     MO.setReg(MatchRegisterName(R1));
1667     // Add a new operand for the second register in the pair.
1668     std::string R2 = v + llvm::utostr(RegPairNum);
1669     Inst.addOperand(MCOperand::createReg(MatchRegisterName(R2)));
1670     Inst.setOpcode(Hexagon::V6_vcombine);
1671     break;
1672   }
1673 
1674   // Translate a "$Rx =  CONST32(#imm)" to "$Rx = memw(gp+#LABEL) "
1675   case Hexagon::CONST32:
1676   case Hexagon::CONST32_Float_Real:
1677   case Hexagon::CONST32_Int_Real:
1678   case Hexagon::FCONST32_nsdata:
1679     is32bit = true;
1680   // Translate a "$Rx:y =  CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "
1681   case Hexagon::CONST64_Float_Real:
1682   case Hexagon::CONST64_Int_Real:
1683 
1684     // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
1685     if (!Parser.getStreamer().hasRawTextSupport()) {
1686       MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
1687       MCOperand &MO_1 = Inst.getOperand(1);
1688       MCOperand &MO_0 = Inst.getOperand(0);
1689 
1690       // push section onto section stack
1691       MES->PushSection();
1692 
1693       std::string myCharStr;
1694       MCSectionELF *mySection;
1695 
1696       // check if this as an immediate or a symbol
1697       int64_t Value;
1698       bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value);
1699       if (Absolute) {
1700         // Create a new section - one for each constant
1701         // Some or all of the zeros are replaced with the given immediate.
1702         if (is32bit) {
1703           std::string myImmStr = utohexstr(static_cast<uint32_t>(Value));
1704           myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000")
1705                           .drop_back(myImmStr.size())
1706                           .str() +
1707                       myImmStr;
1708         } else {
1709           std::string myImmStr = utohexstr(Value);
1710           myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000")
1711                           .drop_back(myImmStr.size())
1712                           .str() +
1713                       myImmStr;
1714         }
1715 
1716         mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1717                                                ELF::SHF_ALLOC | ELF::SHF_WRITE);
1718       } else if (MO_1.isExpr()) {
1719         // .lita - for expressions
1720         myCharStr = ".lita";
1721         mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1722                                                ELF::SHF_ALLOC | ELF::SHF_WRITE);
1723       } else
1724         llvm_unreachable("unexpected type of machine operand!");
1725 
1726       MES->SwitchSection(mySection);
1727       unsigned byteSize = is32bit ? 4 : 8;
1728       getStreamer().EmitCodeAlignment(byteSize, byteSize);
1729 
1730       MCSymbol *Sym;
1731 
1732       // for symbols, get rid of prepended ".gnu.linkonce.lx."
1733 
1734       // emit symbol if needed
1735       if (Absolute) {
1736         Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16));
1737         if (Sym->isUndefined()) {
1738           getStreamer().EmitLabel(Sym);
1739           getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
1740           getStreamer().EmitIntValue(Value, byteSize);
1741         }
1742       } else if (MO_1.isExpr()) {
1743         const char *StringStart = 0;
1744         const char *StringEnd = 0;
1745         if (*Operands[4]->getStartLoc().getPointer() == '#') {
1746           StringStart = Operands[5]->getStartLoc().getPointer();
1747           StringEnd = Operands[6]->getStartLoc().getPointer();
1748         } else { // no pound
1749           StringStart = Operands[4]->getStartLoc().getPointer();
1750           StringEnd = Operands[5]->getStartLoc().getPointer();
1751         }
1752 
1753         unsigned size = StringEnd - StringStart;
1754         std::string DotConst = ".CONST_";
1755         Sym = getContext().getOrCreateSymbol(DotConst +
1756                                              StringRef(StringStart, size));
1757 
1758         if (Sym->isUndefined()) {
1759           // case where symbol is not yet defined: emit symbol
1760           getStreamer().EmitLabel(Sym);
1761           getStreamer().EmitSymbolAttribute(Sym, MCSA_Local);
1762           getStreamer().EmitValue(MO_1.getExpr(), 4);
1763         }
1764       } else
1765         llvm_unreachable("unexpected type of machine operand!");
1766 
1767       MES->PopSection();
1768 
1769       if (Sym) {
1770         MCInst TmpInst;
1771         if (is32bit) // 32 bit
1772           TmpInst.setOpcode(Hexagon::L2_loadrigp);
1773         else // 64 bit
1774           TmpInst.setOpcode(Hexagon::L2_loadrdgp);
1775 
1776         TmpInst.addOperand(MO_0);
1777         TmpInst.addOperand(
1778             MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext())));
1779         Inst = TmpInst;
1780       }
1781     }
1782     break;
1783 
1784   // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)"
1785   case Hexagon::A2_tfrpi: {
1786     MCOperand &Rdd = Inst.getOperand(0);
1787     MCOperand &MO = Inst.getOperand(1);
1788     int64_t Value;
1789     int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0;
1790     MCOperand imm(MCOperand::createExpr(
1791         HexagonMCExpr::create(MCConstantExpr::create(sVal, Context), Context)));
1792     Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO);
1793     break;
1794   }
1795 
1796   // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)"
1797   case Hexagon::TFRI64_V4: {
1798     MCOperand &Rdd = Inst.getOperand(0);
1799     MCOperand &MO = Inst.getOperand(1);
1800     int64_t Value;
1801     if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1802       unsigned long long u64 = Value;
1803       signed int s8 = (u64 >> 32) & 0xFFFFFFFF;
1804       if (s8 < -128 || s8 > 127)
1805         OutOfRange(IDLoc, s8, -128);
1806       MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1807           MCConstantExpr::create(s8, Context), Context))); // upper 32
1808       auto Expr = HexagonMCExpr::create(
1809                   MCConstantExpr::create(u64 & 0xFFFFFFFF, Context),
1810                   Context);
1811       HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
1812       MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
1813       Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
1814     } else {
1815       MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1816           MCConstantExpr::create(0, Context), Context))); // upper 32
1817       Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO);
1818     }
1819     break;
1820   }
1821 
1822   // Handle $Rdd = combine(##imm, #imm)"
1823   case Hexagon::TFRI64_V2_ext: {
1824     MCOperand &Rdd = Inst.getOperand(0);
1825     MCOperand &MO1 = Inst.getOperand(1);
1826     MCOperand &MO2 = Inst.getOperand(2);
1827     int64_t Value;
1828     if (MO2.getExpr()->evaluateAsAbsolute(Value)) {
1829       int s8 = Value;
1830       if (s8 < -128 || s8 > 127)
1831         OutOfRange(IDLoc, s8, -128);
1832     }
1833     Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);
1834     break;
1835   }
1836 
1837   // Handle $Rdd = combine(#imm, ##imm)"
1838   case Hexagon::A4_combineii: {
1839     MCOperand &Rdd = Inst.getOperand(0);
1840     MCOperand &MO1 = Inst.getOperand(1);
1841     int64_t Value;
1842     if (MO1.getExpr()->evaluateAsAbsolute(Value)) {
1843       int s8 = Value;
1844       if (s8 < -128 || s8 > 127)
1845         OutOfRange(IDLoc, s8, -128);
1846     }
1847     MCOperand &MO2 = Inst.getOperand(2);
1848     Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);
1849     break;
1850   }
1851 
1852   case Hexagon::S2_tableidxb_goodsyntax: {
1853     Inst.setOpcode(Hexagon::S2_tableidxb);
1854     break;
1855   }
1856 
1857   case Hexagon::S2_tableidxh_goodsyntax: {
1858     MCInst TmpInst;
1859     MCOperand &Rx = Inst.getOperand(0);
1860     MCOperand &_dst_ = Inst.getOperand(1);
1861     MCOperand &Rs = Inst.getOperand(2);
1862     MCOperand &Imm4 = Inst.getOperand(3);
1863     MCOperand &Imm6 = Inst.getOperand(4);
1864     Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1865         Imm6.getExpr(), MCConstantExpr::create(1, Context), Context), Context));
1866     TmpInst.setOpcode(Hexagon::S2_tableidxh);
1867     TmpInst.addOperand(Rx);
1868     TmpInst.addOperand(_dst_);
1869     TmpInst.addOperand(Rs);
1870     TmpInst.addOperand(Imm4);
1871     TmpInst.addOperand(Imm6);
1872     Inst = TmpInst;
1873     break;
1874   }
1875 
1876   case Hexagon::S2_tableidxw_goodsyntax: {
1877     MCInst TmpInst;
1878     MCOperand &Rx = Inst.getOperand(0);
1879     MCOperand &_dst_ = Inst.getOperand(1);
1880     MCOperand &Rs = Inst.getOperand(2);
1881     MCOperand &Imm4 = Inst.getOperand(3);
1882     MCOperand &Imm6 = Inst.getOperand(4);
1883     Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1884         Imm6.getExpr(), MCConstantExpr::create(2, Context), Context), Context));
1885     TmpInst.setOpcode(Hexagon::S2_tableidxw);
1886     TmpInst.addOperand(Rx);
1887     TmpInst.addOperand(_dst_);
1888     TmpInst.addOperand(Rs);
1889     TmpInst.addOperand(Imm4);
1890     TmpInst.addOperand(Imm6);
1891     Inst = TmpInst;
1892     break;
1893   }
1894 
1895   case Hexagon::S2_tableidxd_goodsyntax: {
1896     MCInst TmpInst;
1897     MCOperand &Rx = Inst.getOperand(0);
1898     MCOperand &_dst_ = Inst.getOperand(1);
1899     MCOperand &Rs = Inst.getOperand(2);
1900     MCOperand &Imm4 = Inst.getOperand(3);
1901     MCOperand &Imm6 = Inst.getOperand(4);
1902     Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub(
1903         Imm6.getExpr(), MCConstantExpr::create(3, Context), Context), Context));
1904     TmpInst.setOpcode(Hexagon::S2_tableidxd);
1905     TmpInst.addOperand(Rx);
1906     TmpInst.addOperand(_dst_);
1907     TmpInst.addOperand(Rs);
1908     TmpInst.addOperand(Imm4);
1909     TmpInst.addOperand(Imm6);
1910     Inst = TmpInst;
1911     break;
1912   }
1913 
1914   case Hexagon::M2_mpyui: {
1915     Inst.setOpcode(Hexagon::M2_mpyi);
1916     break;
1917   }
1918   case Hexagon::M2_mpysmi: {
1919     MCInst TmpInst;
1920     MCOperand &Rd = Inst.getOperand(0);
1921     MCOperand &Rs = Inst.getOperand(1);
1922     MCOperand &Imm = Inst.getOperand(2);
1923     int64_t Value;
1924     MCExpr const &Expr = *Imm.getExpr();
1925     bool Absolute = Expr.evaluateAsAbsolute(Value);
1926     assert(Absolute);
1927     (void)Absolute;
1928     if (!HexagonMCInstrInfo::mustExtend(Expr)) {
1929       if (Value < 0 && Value > -256) {
1930         Imm.setExpr(HexagonMCExpr::create(
1931             MCConstantExpr::create(Value * -1, Context), Context));
1932         TmpInst.setOpcode(Hexagon::M2_mpysin);
1933       } else if (Value < 256 && Value >= 0)
1934         TmpInst.setOpcode(Hexagon::M2_mpysip);
1935       else
1936         return Match_InvalidOperand;
1937     } else {
1938       if (Value >= 0)
1939         TmpInst.setOpcode(Hexagon::M2_mpysip);
1940       else
1941         return Match_InvalidOperand;
1942     }
1943     TmpInst.addOperand(Rd);
1944     TmpInst.addOperand(Rs);
1945     TmpInst.addOperand(Imm);
1946     Inst = TmpInst;
1947     break;
1948   }
1949 
1950   case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
1951     MCOperand &Imm = Inst.getOperand(2);
1952     MCInst TmpInst;
1953     int64_t Value;
1954     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1955     assert(Absolute);
1956     (void)Absolute;
1957     if (Value == 0) { // convert to $Rd = $Rs
1958       TmpInst.setOpcode(Hexagon::A2_tfr);
1959       MCOperand &Rd = Inst.getOperand(0);
1960       MCOperand &Rs = Inst.getOperand(1);
1961       TmpInst.addOperand(Rd);
1962       TmpInst.addOperand(Rs);
1963     } else {
1964       Imm.setExpr(HexagonMCExpr::create(
1965           MCBinaryExpr::createSub(Imm.getExpr(),
1966                                   MCConstantExpr::create(1, Context), Context),
1967           Context));
1968       TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
1969       MCOperand &Rd = Inst.getOperand(0);
1970       MCOperand &Rs = Inst.getOperand(1);
1971       TmpInst.addOperand(Rd);
1972       TmpInst.addOperand(Rs);
1973       TmpInst.addOperand(Imm);
1974     }
1975     Inst = TmpInst;
1976     break;
1977   }
1978 
1979   case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
1980     MCOperand &Rdd = Inst.getOperand(0);
1981     MCOperand &Rss = Inst.getOperand(1);
1982     MCOperand &Imm = Inst.getOperand(2);
1983     int64_t Value;
1984     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1985     assert(Absolute);
1986     (void)Absolute;
1987     if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1])
1988       MCInst TmpInst;
1989       unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1990       std::string R1 = r + llvm::utostr(RegPairNum + 1);
1991       StringRef Reg1(R1);
1992       Rss.setReg(matchRegister(Reg1));
1993       // Add a new operand for the second register in the pair.
1994       std::string R2 = r + llvm::utostr(RegPairNum);
1995       StringRef Reg2(R2);
1996       TmpInst.setOpcode(Hexagon::A2_combinew);
1997       TmpInst.addOperand(Rdd);
1998       TmpInst.addOperand(Rss);
1999       TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
2000       Inst = TmpInst;
2001     } else {
2002       Imm.setExpr(HexagonMCExpr::create(
2003           MCBinaryExpr::createSub(Imm.getExpr(),
2004                                   MCConstantExpr::create(1, Context), Context),
2005           Context));
2006       Inst.setOpcode(Hexagon::S2_asr_i_p_rnd);
2007     }
2008     break;
2009   }
2010 
2011   case Hexagon::A4_boundscheck: {
2012     MCOperand &Rs = Inst.getOperand(1);
2013     unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
2014     if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
2015       Inst.setOpcode(Hexagon::A4_boundscheck_hi);
2016       std::string Name =
2017           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2018       StringRef RegPair = Name;
2019       Rs.setReg(matchRegister(RegPair));
2020     } else { // raw:lo
2021       Inst.setOpcode(Hexagon::A4_boundscheck_lo);
2022       std::string Name =
2023           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2024       StringRef RegPair = Name;
2025       Rs.setReg(matchRegister(RegPair));
2026     }
2027     break;
2028   }
2029 
2030   case Hexagon::A2_addsp: {
2031     MCOperand &Rs = Inst.getOperand(1);
2032     unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
2033     if (RegNum & 1) { // Odd mapped to raw:hi
2034       Inst.setOpcode(Hexagon::A2_addsph);
2035       std::string Name =
2036           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2037       StringRef RegPair = Name;
2038       Rs.setReg(matchRegister(RegPair));
2039     } else { // Even mapped raw:lo
2040       Inst.setOpcode(Hexagon::A2_addspl);
2041       std::string Name =
2042           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2043       StringRef RegPair = Name;
2044       Rs.setReg(matchRegister(RegPair));
2045     }
2046     break;
2047   }
2048 
2049   case Hexagon::M2_vrcmpys_s1: {
2050     MCOperand &Rt = Inst.getOperand(2);
2051     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2052     if (RegNum & 1) { // Odd mapped to sat:raw:hi
2053       Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
2054       std::string Name =
2055           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2056       StringRef RegPair = Name;
2057       Rt.setReg(matchRegister(RegPair));
2058     } else { // Even mapped sat:raw:lo
2059       Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
2060       std::string Name =
2061           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2062       StringRef RegPair = Name;
2063       Rt.setReg(matchRegister(RegPair));
2064     }
2065     break;
2066   }
2067 
2068   case Hexagon::M2_vrcmpys_acc_s1: {
2069     MCInst TmpInst;
2070     MCOperand &Rxx = Inst.getOperand(0);
2071     MCOperand &Rss = Inst.getOperand(2);
2072     MCOperand &Rt = Inst.getOperand(3);
2073     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2074     if (RegNum & 1) { // Odd mapped to sat:raw:hi
2075       TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
2076       std::string Name =
2077           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2078       StringRef RegPair = Name;
2079       Rt.setReg(matchRegister(RegPair));
2080     } else { // Even mapped sat:raw:lo
2081       TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
2082       std::string Name =
2083           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2084       StringRef RegPair = Name;
2085       Rt.setReg(matchRegister(RegPair));
2086     }
2087     // Registers are in different positions
2088     TmpInst.addOperand(Rxx);
2089     TmpInst.addOperand(Rxx);
2090     TmpInst.addOperand(Rss);
2091     TmpInst.addOperand(Rt);
2092     Inst = TmpInst;
2093     break;
2094   }
2095 
2096   case Hexagon::M2_vrcmpys_s1rp: {
2097     MCOperand &Rt = Inst.getOperand(2);
2098     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
2099     if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi
2100       Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
2101       std::string Name =
2102           r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1);
2103       StringRef RegPair = Name;
2104       Rt.setReg(matchRegister(RegPair));
2105     } else { // Even mapped rnd:sat:raw:lo
2106       Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
2107       std::string Name =
2108           r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum);
2109       StringRef RegPair = Name;
2110       Rt.setReg(matchRegister(RegPair));
2111     }
2112     break;
2113   }
2114 
2115   case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
2116     MCOperand &Imm = Inst.getOperand(2);
2117     int64_t Value;
2118     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
2119     assert(Absolute);
2120     (void)Absolute;
2121     if (Value == 0)
2122       Inst.setOpcode(Hexagon::S2_vsathub);
2123     else {
2124       Imm.setExpr(HexagonMCExpr::create(
2125           MCBinaryExpr::createSub(Imm.getExpr(),
2126                                   MCConstantExpr::create(1, Context), Context),
2127           Context));
2128       Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
2129     }
2130     break;
2131   }
2132 
2133   case Hexagon::S5_vasrhrnd_goodsyntax: {
2134     MCOperand &Rdd = Inst.getOperand(0);
2135     MCOperand &Rss = Inst.getOperand(1);
2136     MCOperand &Imm = Inst.getOperand(2);
2137     int64_t Value;
2138     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
2139     assert(Absolute);
2140     (void)Absolute;
2141     if (Value == 0) {
2142       MCInst TmpInst;
2143       unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
2144       std::string R1 = r + llvm::utostr(RegPairNum + 1);
2145       StringRef Reg1(R1);
2146       Rss.setReg(matchRegister(Reg1));
2147       // Add a new operand for the second register in the pair.
2148       std::string R2 = r + llvm::utostr(RegPairNum);
2149       StringRef Reg2(R2);
2150       TmpInst.setOpcode(Hexagon::A2_combinew);
2151       TmpInst.addOperand(Rdd);
2152       TmpInst.addOperand(Rss);
2153       TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
2154       Inst = TmpInst;
2155     } else {
2156       Imm.setExpr(HexagonMCExpr::create(
2157           MCBinaryExpr::createSub(Imm.getExpr(),
2158                                   MCConstantExpr::create(1, Context), Context),
2159           Context));
2160       Inst.setOpcode(Hexagon::S5_vasrhrnd);
2161     }
2162     break;
2163   }
2164 
2165   case Hexagon::A2_not: {
2166     MCInst TmpInst;
2167     MCOperand &Rd = Inst.getOperand(0);
2168     MCOperand &Rs = Inst.getOperand(1);
2169     TmpInst.setOpcode(Hexagon::A2_subri);
2170     TmpInst.addOperand(Rd);
2171     TmpInst.addOperand(MCOperand::createExpr(
2172         HexagonMCExpr::create(MCConstantExpr::create(-1, Context), Context)));
2173     TmpInst.addOperand(Rs);
2174     Inst = TmpInst;
2175     break;
2176   }
2177   } // switch
2178 
2179   return Match_Success;
2180 }
2181 
2182 
2183 unsigned HexagonAsmParser::matchRegister(StringRef Name) {
2184   if (unsigned Reg = MatchRegisterName(Name))
2185     return Reg;
2186   return MatchRegisterAltName(Name);
2187 }
2188