1 //===-- CSKYInstrInfo.h - CSKY Instruction Information --------*- C++ -*---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the CSKY implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H
14 #define LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H
15 
16 #include "MCTargetDesc/CSKYMCTargetDesc.h"
17 #include "llvm/CodeGen/TargetInstrInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "CSKYGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 class CSKYSubtarget;
25 
26 class CSKYInstrInfo : public CSKYGenInstrInfo {
27 protected:
28   const CSKYSubtarget &STI;
29 
30 public:
31   explicit CSKYInstrInfo(CSKYSubtarget &STI);
32 
33   unsigned isLoadFromStackSlot(const MachineInstr &MI,
34                                int &FrameIndex) const override;
35   unsigned isStoreToStackSlot(const MachineInstr &MI,
36                               int &FrameIndex) const override;
37 
38   void storeRegToStackSlot(MachineBasicBlock &MBB,
39                            MachineBasicBlock::iterator MI, Register SrcReg,
40                            bool IsKill, int FrameIndex,
41                            const TargetRegisterClass *RC,
42                            const TargetRegisterInfo *TRI) const override;
43 
44   void loadRegFromStackSlot(MachineBasicBlock &MBB,
45                             MachineBasicBlock::iterator MI, Register DestReg,
46                             int FrameIndex, const TargetRegisterClass *RC,
47                             const TargetRegisterInfo *TRI) const override;
48 
49   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
50                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
51                    bool KillSrc) const override;
52 
53   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
54                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
55                         const DebugLoc &DL,
56                         int *BytesAdded = nullptr) const override;
57 
58   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
59                      MachineBasicBlock *&FBB,
60                      SmallVectorImpl<MachineOperand> &Cond,
61                      bool AllowModify = false) const override;
62 
63   unsigned removeBranch(MachineBasicBlock &MBB,
64                         int *BytesRemoved = nullptr) const override;
65 
66   bool
67   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
68 
69   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
70 
71   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
72 
73   Register getGlobalBaseReg(MachineFunction &MF) const;
74 
75   // Materializes the given integer Val into DstReg.
76   Register movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
77                   const DebugLoc &DL, int64_t Val,
78                   MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
79 };
80 
81 } // namespace llvm
82 
83 #endif // LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H
84