1 //===-- BPFMCCodeEmitter.cpp - Convert BPF code to machine code -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the BPFMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/BPFMCTargetDesc.h" 14 #include "llvm/ADT/SmallVector.h" 15 #include "llvm/MC/MCCodeEmitter.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/MC/MCFixup.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCRegisterInfo.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Endian.h" 23 #include "llvm/Support/EndianStream.h" 24 #include <cassert> 25 #include <cstdint> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "mccodeemitter" 30 31 namespace { 32 33 class BPFMCCodeEmitter : public MCCodeEmitter { 34 const MCInstrInfo &MCII; 35 const MCRegisterInfo &MRI; 36 bool IsLittleEndian; 37 38 public: 39 BPFMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri, 40 bool IsLittleEndian) 41 : MCII(mcii), MRI(mri), IsLittleEndian(IsLittleEndian) {} 42 BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete; 43 void operator=(const BPFMCCodeEmitter &) = delete; 44 ~BPFMCCodeEmitter() override = default; 45 46 // getBinaryCodeForInstr - TableGen'erated function for getting the 47 // binary encoding for an instruction. 48 uint64_t getBinaryCodeForInstr(const MCInst &MI, 49 SmallVectorImpl<MCFixup> &Fixups, 50 const MCSubtargetInfo &STI) const; 51 52 // getMachineOpValue - Return binary encoding of operand. If the machin 53 // operand requires relocation, record the relocation and return zero. 54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 55 SmallVectorImpl<MCFixup> &Fixups, 56 const MCSubtargetInfo &STI) const; 57 58 uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op, 59 SmallVectorImpl<MCFixup> &Fixups, 60 const MCSubtargetInfo &STI) const; 61 62 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 63 SmallVectorImpl<MCFixup> &Fixups, 64 const MCSubtargetInfo &STI) const override; 65 66 private: 67 FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const; 68 void 69 verifyInstructionPredicates(const MCInst &MI, 70 const FeatureBitset &AvailableFeatures) const; 71 }; 72 73 } // end anonymous namespace 74 75 MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII, 76 MCContext &Ctx) { 77 return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), true); 78 } 79 80 MCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, 81 MCContext &Ctx) { 82 return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), false); 83 } 84 85 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI, 86 const MCOperand &MO, 87 SmallVectorImpl<MCFixup> &Fixups, 88 const MCSubtargetInfo &STI) const { 89 if (MO.isReg()) 90 return MRI.getEncodingValue(MO.getReg()); 91 if (MO.isImm()) 92 return static_cast<unsigned>(MO.getImm()); 93 94 assert(MO.isExpr()); 95 96 const MCExpr *Expr = MO.getExpr(); 97 98 assert(Expr->getKind() == MCExpr::SymbolRef); 99 100 if (MI.getOpcode() == BPF::JAL) 101 // func call name 102 Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_4)); 103 else if (MI.getOpcode() == BPF::LD_imm64) 104 Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8)); 105 else 106 // bb label 107 Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2)); 108 109 return 0; 110 } 111 112 static uint8_t SwapBits(uint8_t Val) 113 { 114 return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4; 115 } 116 117 void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 118 SmallVectorImpl<MCFixup> &Fixups, 119 const MCSubtargetInfo &STI) const { 120 verifyInstructionPredicates(MI, 121 computeAvailableFeatures(STI.getFeatureBits())); 122 123 unsigned Opcode = MI.getOpcode(); 124 support::endian::Writer OSE(OS, 125 IsLittleEndian ? support::little : support::big); 126 127 if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) { 128 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI); 129 OS << char(Value >> 56); 130 if (IsLittleEndian) 131 OS << char((Value >> 48) & 0xff); 132 else 133 OS << char(SwapBits((Value >> 48) & 0xff)); 134 OSE.write<uint16_t>(0); 135 OSE.write<uint32_t>(Value & 0xffffFFFF); 136 137 const MCOperand &MO = MI.getOperand(1); 138 uint64_t Imm = MO.isImm() ? MO.getImm() : 0; 139 OSE.write<uint8_t>(0); 140 OSE.write<uint8_t>(0); 141 OSE.write<uint16_t>(0); 142 OSE.write<uint32_t>(Imm >> 32); 143 } else { 144 // Get instruction encoding and emit it 145 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI); 146 OS << char(Value >> 56); 147 if (IsLittleEndian) 148 OS << char((Value >> 48) & 0xff); 149 else 150 OS << char(SwapBits((Value >> 48) & 0xff)); 151 OSE.write<uint16_t>((Value >> 32) & 0xffff); 152 OSE.write<uint32_t>(Value & 0xffffFFFF); 153 } 154 } 155 156 // Encode BPF Memory Operand 157 uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op, 158 SmallVectorImpl<MCFixup> &Fixups, 159 const MCSubtargetInfo &STI) const { 160 // For CMPXCHG instructions, output is implicitly in R0/W0, 161 // so memory operand starts from operand 0. 162 int MemOpStartIndex = 1, Opcode = MI.getOpcode(); 163 if (Opcode == BPF::CMPXCHGW32 || Opcode == BPF::CMPXCHGD) 164 MemOpStartIndex = 0; 165 166 uint64_t Encoding; 167 const MCOperand Op1 = MI.getOperand(MemOpStartIndex); 168 assert(Op1.isReg() && "First operand is not register."); 169 Encoding = MRI.getEncodingValue(Op1.getReg()); 170 Encoding <<= 16; 171 MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1); 172 assert(Op2.isImm() && "Second operand is not immediate."); 173 Encoding |= Op2.getImm() & 0xffff; 174 return Encoding; 175 } 176 177 #define ENABLE_INSTR_PREDICATE_VERIFIER 178 #include "BPFGenMCCodeEmitter.inc" 179