1 //===-- BPFMCCodeEmitter.cpp - Convert BPF code to machine code -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the BPFMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/BPFMCTargetDesc.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/MC/MCCodeEmitter.h" 17 #include "llvm/MC/MCFixup.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCRegisterInfo.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Endian.h" 23 #include "llvm/Support/EndianStream.h" 24 #include <cassert> 25 #include <cstdint> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "mccodeemitter" 30 31 namespace { 32 33 class BPFMCCodeEmitter : public MCCodeEmitter { 34 const MCInstrInfo &MCII; 35 const MCRegisterInfo &MRI; 36 bool IsLittleEndian; 37 38 public: 39 BPFMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri, 40 bool IsLittleEndian) 41 : MCII(mcii), MRI(mri), IsLittleEndian(IsLittleEndian) {} 42 BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete; 43 void operator=(const BPFMCCodeEmitter &) = delete; 44 ~BPFMCCodeEmitter() override = default; 45 46 // getBinaryCodeForInstr - TableGen'erated function for getting the 47 // binary encoding for an instruction. 48 uint64_t getBinaryCodeForInstr(const MCInst &MI, 49 SmallVectorImpl<MCFixup> &Fixups, 50 const MCSubtargetInfo &STI) const; 51 52 // getMachineOpValue - Return binary encoding of operand. If the machin 53 // operand requires relocation, record the relocation and return zero. 54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 55 SmallVectorImpl<MCFixup> &Fixups, 56 const MCSubtargetInfo &STI) const; 57 58 uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op, 59 SmallVectorImpl<MCFixup> &Fixups, 60 const MCSubtargetInfo &STI) const; 61 62 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 63 SmallVectorImpl<MCFixup> &Fixups, 64 const MCSubtargetInfo &STI) const override; 65 66 private: 67 uint64_t computeAvailableFeatures(const FeatureBitset &FB) const; 68 void verifyInstructionPredicates(const MCInst &MI, 69 uint64_t AvailableFeatures) const; 70 }; 71 72 } // end anonymous namespace 73 74 MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII, 75 const MCRegisterInfo &MRI, 76 MCContext &Ctx) { 77 return new BPFMCCodeEmitter(MCII, MRI, true); 78 } 79 80 MCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, 81 const MCRegisterInfo &MRI, 82 MCContext &Ctx) { 83 return new BPFMCCodeEmitter(MCII, MRI, false); 84 } 85 86 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI, 87 const MCOperand &MO, 88 SmallVectorImpl<MCFixup> &Fixups, 89 const MCSubtargetInfo &STI) const { 90 if (MO.isReg()) 91 return MRI.getEncodingValue(MO.getReg()); 92 if (MO.isImm()) 93 return static_cast<unsigned>(MO.getImm()); 94 95 assert(MO.isExpr()); 96 97 const MCExpr *Expr = MO.getExpr(); 98 99 assert(Expr->getKind() == MCExpr::SymbolRef); 100 101 if (MI.getOpcode() == BPF::JAL) 102 // func call name 103 Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_4)); 104 else if (MI.getOpcode() == BPF::LD_imm64) 105 Fixups.push_back(MCFixup::create(0, Expr, FK_SecRel_8)); 106 else 107 // bb label 108 Fixups.push_back(MCFixup::create(0, Expr, FK_PCRel_2)); 109 110 return 0; 111 } 112 113 static uint8_t SwapBits(uint8_t Val) 114 { 115 return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4; 116 } 117 118 void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 119 SmallVectorImpl<MCFixup> &Fixups, 120 const MCSubtargetInfo &STI) const { 121 verifyInstructionPredicates(MI, 122 computeAvailableFeatures(STI.getFeatureBits())); 123 124 unsigned Opcode = MI.getOpcode(); 125 support::endian::Writer<support::little> LE(OS); 126 support::endian::Writer<support::big> BE(OS); 127 128 if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) { 129 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI); 130 LE.write<uint8_t>(Value >> 56); 131 if (IsLittleEndian) 132 LE.write<uint8_t>((Value >> 48) & 0xff); 133 else 134 LE.write<uint8_t>(SwapBits((Value >> 48) & 0xff)); 135 LE.write<uint16_t>(0); 136 if (IsLittleEndian) 137 LE.write<uint32_t>(Value & 0xffffFFFF); 138 else 139 BE.write<uint32_t>(Value & 0xffffFFFF); 140 141 const MCOperand &MO = MI.getOperand(1); 142 uint64_t Imm = MO.isImm() ? MO.getImm() : 0; 143 LE.write<uint8_t>(0); 144 LE.write<uint8_t>(0); 145 LE.write<uint16_t>(0); 146 if (IsLittleEndian) 147 LE.write<uint32_t>(Imm >> 32); 148 else 149 BE.write<uint32_t>(Imm >> 32); 150 } else { 151 // Get instruction encoding and emit it 152 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI); 153 LE.write<uint8_t>(Value >> 56); 154 if (IsLittleEndian) { 155 LE.write<uint8_t>((Value >> 48) & 0xff); 156 LE.write<uint16_t>((Value >> 32) & 0xffff); 157 LE.write<uint32_t>(Value & 0xffffFFFF); 158 } else { 159 LE.write<uint8_t>(SwapBits((Value >> 48) & 0xff)); 160 BE.write<uint16_t>((Value >> 32) & 0xffff); 161 BE.write<uint32_t>(Value & 0xffffFFFF); 162 } 163 } 164 } 165 166 // Encode BPF Memory Operand 167 uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op, 168 SmallVectorImpl<MCFixup> &Fixups, 169 const MCSubtargetInfo &STI) const { 170 uint64_t Encoding; 171 const MCOperand Op1 = MI.getOperand(1); 172 assert(Op1.isReg() && "First operand is not register."); 173 Encoding = MRI.getEncodingValue(Op1.getReg()); 174 Encoding <<= 16; 175 MCOperand Op2 = MI.getOperand(2); 176 assert(Op2.isImm() && "Second operand is not immediate."); 177 Encoding |= Op2.getImm() & 0xffff; 178 return Encoding; 179 } 180 181 #define ENABLE_INSTR_PREDICATE_VERIFIER 182 #include "BPFGenMCCodeEmitter.inc" 183