1//===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the BPF instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14include "BPFInstrFormats.td"
15
16// Instruction Operands and Patterns
17
18// These are target-independent nodes, but have target-specific formats.
19def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
20def SDT_BPFCallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
21def SDT_BPFCall         : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
22def SDT_BPFSetFlag      : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
23def SDT_BPFSelectCC     : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
24                                               SDTCisSameAs<0, 4>,
25                                               SDTCisSameAs<4, 5>]>;
26def SDT_BPFBrCC         : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
27                                               SDTCisVT<3, OtherVT>]>;
28def SDT_BPFWrapper      : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
29                                               SDTCisPtrTy<0>]>;
30
31def BPFcall         : SDNode<"BPFISD::CALL", SDT_BPFCall,
32                             [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
33                              SDNPVariadic]>;
34def BPFretflag      : SDNode<"BPFISD::RET_FLAG", SDTNone,
35                             [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
36def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart,
37                             [SDNPHasChain, SDNPOutGlue]>;
38def BPFcallseq_end  : SDNode<"ISD::CALLSEQ_END",   SDT_BPFCallSeqEnd,
39                             [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
40def BPFbrcc         : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
41                             [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;
42
43def BPFselectcc     : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
44def BPFWrapper      : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
45
46def brtarget : Operand<OtherVT>;
47def calltarget : Operand<i64>;
48
49def u64imm   : Operand<i64> {
50  let PrintMethod = "printImm64Operand";
51}
52
53def i64immSExt32 : PatLeaf<(imm),
54                [{return isInt<32>(N->getSExtValue()); }]>;
55
56// Addressing modes.
57def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
58def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
59
60// Address operands
61def MEMri : Operand<i64> {
62  let PrintMethod = "printMemOperand";
63  let EncoderMethod = "getMemoryOpValue";
64  let DecoderMethod = "decodeMemoryOpValue";
65  let MIOperandInfo = (ops GPR, i16imm);
66}
67
68// Conditional code predicates - used for pattern matching for jump instructions
69def BPF_CC_EQ  : PatLeaf<(imm),
70                         [{return (N->getZExtValue() == ISD::SETEQ);}]>;
71def BPF_CC_NE  : PatLeaf<(imm),
72                         [{return (N->getZExtValue() == ISD::SETNE);}]>;
73def BPF_CC_GE  : PatLeaf<(imm),
74                         [{return (N->getZExtValue() == ISD::SETGE);}]>;
75def BPF_CC_GT  : PatLeaf<(imm),
76                         [{return (N->getZExtValue() == ISD::SETGT);}]>;
77def BPF_CC_GTU : PatLeaf<(imm),
78                         [{return (N->getZExtValue() == ISD::SETUGT);}]>;
79def BPF_CC_GEU : PatLeaf<(imm),
80                         [{return (N->getZExtValue() == ISD::SETUGE);}]>;
81
82// jump instructions
83class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
84    : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
85              "if $dst "#OpcodeStr#" $src goto $BrDst",
86              [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
87  bits<4> op;
88  bits<1> BPFSrc;
89  bits<4> dst;
90  bits<4> src;
91  bits<16> BrDst;
92
93  let Inst{63-60} = op;
94  let Inst{59} = BPFSrc;
95  let Inst{55-52} = src;
96  let Inst{51-48} = dst;
97  let Inst{47-32} = BrDst;
98
99  let op = Opc;
100  let BPFSrc = 1;
101  let BPFClass = 5; // BPF_JMP
102}
103
104class JMP_RI<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
105    : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
106              "if $dst "#OpcodeStr#" $imm goto $BrDst",
107              [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
108  bits<4> op;
109  bits<1> BPFSrc;
110  bits<4> dst;
111  bits<16> BrDst;
112  bits<32> imm;
113
114  let Inst{63-60} = op;
115  let Inst{59} = BPFSrc;
116  let Inst{51-48} = dst;
117  let Inst{47-32} = BrDst;
118  let Inst{31-0} = imm;
119
120  let op = Opc;
121  let BPFSrc = 0;
122  let BPFClass = 5; // BPF_JMP
123}
124
125multiclass J<bits<4> Opc, string OpcodeStr, PatLeaf Cond> {
126  def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
127  def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
128}
129
130let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
131// cmp+goto instructions
132defm JEQ  : J<0x1, "==",  BPF_CC_EQ>;
133defm JUGT : J<0x2, ">", BPF_CC_GTU>;
134defm JUGE : J<0x3, ">=", BPF_CC_GEU>;
135defm JNE  : J<0x5, "!=",  BPF_CC_NE>;
136defm JSGT : J<0x6, "s>", BPF_CC_GT>;
137defm JSGE : J<0x7, "s>=", BPF_CC_GE>;
138}
139
140// ALU instructions
141class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
142    : InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
143              "$dst "#OpcodeStr#" $imm",
144              [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
145  bits<4> op;
146  bits<1> BPFSrc;
147  bits<4> dst;
148  bits<32> imm;
149
150  let Inst{63-60} = op;
151  let Inst{59} = BPFSrc;
152  let Inst{51-48} = dst;
153  let Inst{31-0} = imm;
154
155  let op = Opc;
156  let BPFSrc = 0;
157  let BPFClass = 7; // BPF_ALU64
158}
159
160class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
161    : InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
162              "$dst "#OpcodeStr#" $src",
163              [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
164  bits<4> op;
165  bits<1> BPFSrc;
166  bits<4> dst;
167  bits<4> src;
168
169  let Inst{63-60} = op;
170  let Inst{59} = BPFSrc;
171  let Inst{55-52} = src;
172  let Inst{51-48} = dst;
173
174  let op = Opc;
175  let BPFSrc = 1;
176  let BPFClass = 7; // BPF_ALU64
177}
178
179multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
180  def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
181  def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
182}
183
184let Constraints = "$dst = $src2" in {
185let isAsCheapAsAMove = 1 in {
186  defm ADD : ALU<0x0, "+=", add>;
187  defm SUB : ALU<0x1, "-=", sub>;
188  defm OR  : ALU<0x4, "|=", or>;
189  defm AND : ALU<0x5, "&=", and>;
190  defm SLL : ALU<0x6, "<<=", shl>;
191  defm SRL : ALU<0x7, ">>=", srl>;
192  defm XOR : ALU<0xa, "^=", xor>;
193  defm SRA : ALU<0xc, "s>>=", sra>;
194}
195  defm MUL : ALU<0x2, "*=", mul>;
196  defm DIV : ALU<0x3, "/=", udiv>;
197}
198
199class MOV_RR<string OpcodeStr>
200    : InstBPF<(outs GPR:$dst), (ins GPR:$src),
201              "$dst "#OpcodeStr#" $src",
202              []> {
203  bits<4> op;
204  bits<1> BPFSrc;
205  bits<4> dst;
206  bits<4> src;
207
208  let Inst{63-60} = op;
209  let Inst{59} = BPFSrc;
210  let Inst{55-52} = src;
211  let Inst{51-48} = dst;
212
213  let op = 0xb;     // BPF_MOV
214  let BPFSrc = 1;   // BPF_X
215  let BPFClass = 7; // BPF_ALU64
216}
217
218class MOV_RI<string OpcodeStr>
219    : InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
220              "$dst "#OpcodeStr#" $imm",
221              [(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
222  bits<4> op;
223  bits<1> BPFSrc;
224  bits<4> dst;
225  bits<32> imm;
226
227  let Inst{63-60} = op;
228  let Inst{59} = BPFSrc;
229  let Inst{51-48} = dst;
230  let Inst{31-0} = imm;
231
232  let op = 0xb;     // BPF_MOV
233  let BPFSrc = 0;   // BPF_K
234  let BPFClass = 7; // BPF_ALU64
235}
236
237class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
238    : InstBPF<(outs GPR:$dst), (ins u64imm:$imm),
239              "$dst "#OpcodeStr#" ${imm}ll",
240              [(set GPR:$dst, (i64 imm:$imm))]> {
241
242  bits<3> mode;
243  bits<2> size;
244  bits<4> dst;
245  bits<64> imm;
246
247  let Inst{63-61} = mode;
248  let Inst{60-59} = size;
249  let Inst{51-48} = dst;
250  let Inst{55-52} = Pseudo;
251  let Inst{47-32} = 0;
252  let Inst{31-0} = imm{31-0};
253
254  let mode = 0;     // BPF_IMM
255  let size = 3;     // BPF_DW
256  let BPFClass = 0; // BPF_LD
257}
258
259let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
260def LD_imm64 : LD_IMM64<0, "=">;
261def MOV_rr : MOV_RR<"=">;
262def MOV_ri : MOV_RI<"=">;
263}
264
265def FI_ri
266    : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
267               "lea\t$dst, $addr",
268               [(set i64:$dst, FIri:$addr)]> {
269  // This is a tentative instruction, and will be replaced
270  // with MOV_rr and ADD_ri in PEI phase
271  let Inst{63-61} = 0;
272  let Inst{60-59} = 3;
273  let Inst{51-48} = 0;
274  let Inst{55-52} = 2;
275  let Inst{47-32} = 0;
276  let Inst{31-0} = 0;
277  let BPFClass = 0;
278}
279
280
281def LD_pseudo
282    : InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm),
283              "ld_pseudo\t$dst, $pseudo, $imm",
284              [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> {
285
286  bits<3> mode;
287  bits<2> size;
288  bits<4> dst;
289  bits<64> imm;
290  bits<4> pseudo;
291
292  let Inst{63-61} = mode;
293  let Inst{60-59} = size;
294  let Inst{51-48} = dst;
295  let Inst{55-52} = pseudo;
296  let Inst{47-32} = 0;
297  let Inst{31-0} = imm{31-0};
298
299  let mode = 0;     // BPF_IMM
300  let size = 3;     // BPF_DW
301  let BPFClass = 0; // BPF_LD
302}
303
304// STORE instructions
305class STORE<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
306    : InstBPF<(outs), (ins GPR:$src, MEMri:$addr),
307              "*("#OpcodeStr#" *)($addr) = $src", Pattern> {
308  bits<3> mode;
309  bits<2> size;
310  bits<4> src;
311  bits<20> addr;
312
313  let Inst{63-61} = mode;
314  let Inst{60-59} = size;
315  let Inst{51-48} = addr{19-16}; // base reg
316  let Inst{55-52} = src;
317  let Inst{47-32} = addr{15-0}; // offset
318
319  let mode = 3;     // BPF_MEM
320  let size = SizeOp;
321  let BPFClass = 3; // BPF_STX
322}
323
324class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
325    : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
326
327def STW : STOREi64<0x0, "u32", truncstorei32>;
328def STH : STOREi64<0x1, "u16", truncstorei16>;
329def STB : STOREi64<0x2, "u8", truncstorei8>;
330def STD : STOREi64<0x3, "u64", store>;
331
332// LOAD instructions
333class LOAD<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
334    : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
335              "$dst = *("#OpcodeStr#" *)($addr)", Pattern> {
336  bits<3> mode;
337  bits<2> size;
338  bits<4> dst;
339  bits<20> addr;
340
341  let Inst{63-61} = mode;
342  let Inst{60-59} = size;
343  let Inst{51-48} = dst;
344  let Inst{55-52} = addr{19-16};
345  let Inst{47-32} = addr{15-0};
346
347  let mode = 3;     // BPF_MEM
348  let size = SizeOp;
349  let BPFClass = 1; // BPF_LDX
350}
351
352class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
353    : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
354
355def LDW : LOADi64<0x0, "u32", zextloadi32>;
356def LDH : LOADi64<0x1, "u16", zextloadi16>;
357def LDB : LOADi64<0x2, "u8", zextloadi8>;
358def LDD : LOADi64<0x3, "u64", load>;
359
360class BRANCH<bits<4> Opc, string OpcodeStr, list<dag> Pattern>
361    : InstBPF<(outs), (ins brtarget:$BrDst),
362              !strconcat(OpcodeStr, " $BrDst"), Pattern> {
363  bits<4> op;
364  bits<16> BrDst;
365  bits<1> BPFSrc;
366
367  let Inst{63-60} = op;
368  let Inst{59} = BPFSrc;
369  let Inst{47-32} = BrDst;
370
371  let op = Opc;
372  let BPFSrc = 0;
373  let BPFClass = 5; // BPF_JMP
374}
375
376class CALL<string OpcodeStr>
377    : InstBPF<(outs), (ins calltarget:$BrDst),
378              !strconcat(OpcodeStr, " $BrDst"), []> {
379  bits<4> op;
380  bits<32> BrDst;
381  bits<1> BPFSrc;
382
383  let Inst{63-60} = op;
384  let Inst{59} = BPFSrc;
385  let Inst{31-0} = BrDst;
386
387  let op = 8;       // BPF_CALL
388  let BPFSrc = 0;
389  let BPFClass = 5; // BPF_JMP
390}
391
392// Jump always
393let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
394  def JMP : BRANCH<0x0, "goto", [(br bb:$BrDst)]>;
395}
396
397// Jump and link
398let isCall=1, hasDelaySlot=0, Uses = [R11],
399    // Potentially clobbered registers
400    Defs = [R0, R1, R2, R3, R4, R5] in {
401  def JAL  : CALL<"call">;
402}
403
404class NOP_I<string OpcodeStr>
405    : InstBPF<(outs), (ins i32imm:$imm),
406              !strconcat(OpcodeStr, "\t$imm"), []> {
407  // mov r0, r0 == nop
408  bits<4> op;
409  bits<1> BPFSrc;
410  bits<4> dst;
411  bits<4> src;
412
413  let Inst{63-60} = op;
414  let Inst{59} = BPFSrc;
415  let Inst{55-52} = src;
416  let Inst{51-48} = dst;
417
418  let op = 0xb;     // BPF_MOV
419  let BPFSrc = 1;   // BPF_X
420  let BPFClass = 7; // BPF_ALU64
421  let src = 0;      // R0
422  let dst = 0;      // R0
423}
424
425let hasSideEffects = 0 in
426  def NOP : NOP_I<"nop">;
427
428class RET<string OpcodeStr>
429    : InstBPF<(outs), (ins),
430              !strconcat(OpcodeStr, ""), [(BPFretflag)]> {
431  bits<4> op;
432
433  let Inst{63-60} = op;
434  let Inst{59} = 0;
435  let Inst{31-0} = 0;
436
437  let op = 9;       // BPF_EXIT
438  let BPFClass = 5; // BPF_JMP
439}
440
441let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
442    isNotDuplicable = 1 in {
443  def RET : RET<"exit">;
444}
445
446// ADJCALLSTACKDOWN/UP pseudo insns
447let Defs = [R11], Uses = [R11] in {
448def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
449                              "#ADJCALLSTACKDOWN $amt",
450                              [(BPFcallseq_start timm:$amt)]>;
451def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
452                              "#ADJCALLSTACKUP $amt1 $amt2",
453                              [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
454}
455
456let usesCustomInserter = 1 in {
457  def Select : Pseudo<(outs GPR:$dst),
458                      (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
459                      "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
460                      [(set i64:$dst,
461                       (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>;
462}
463
464// load 64-bit global addr into register
465def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>;
466
467// 0xffffFFFF doesn't fit into simm32, optimize common case
468def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
469          (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;
470
471// Calls
472def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>;
473def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>;
474
475// Loads
476def : Pat<(extloadi8  ADDRri:$src), (i64 (LDB ADDRri:$src))>;
477def : Pat<(extloadi16 ADDRri:$src), (i64 (LDH ADDRri:$src))>;
478def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>;
479
480// Atomics
481class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
482    : InstBPF<(outs GPR:$dst), (ins MEMri:$addr, GPR:$val),
483              "lock *("#OpcodeStr#" *)($addr) += $val",
484              [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
485  bits<3> mode;
486  bits<2> size;
487  bits<4> dst;
488  bits<20> addr;
489
490  let Inst{63-61} = mode;
491  let Inst{60-59} = size;
492  let Inst{51-48} = addr{19-16}; // base reg
493  let Inst{55-52} = dst;
494  let Inst{47-32} = addr{15-0}; // offset
495
496  let mode = 6;     // BPF_XADD
497  let size = SizeOp;
498  let BPFClass = 3; // BPF_STX
499}
500
501let Constraints = "$dst = $val" in {
502def XADD32 : XADD<0, "u32", atomic_load_add_32>;
503def XADD64 : XADD<3, "u64", atomic_load_add_64>;
504// undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
505// undefined def XADD8  : XADD<2, "xadd8", atomic_load_add_8>;
506}
507
508// bswap16, bswap32, bswap64
509class BSWAP<bits<32> SizeOp, string OpcodeStr, list<dag> Pattern>
510    : InstBPF<(outs GPR:$dst), (ins GPR:$src),
511              !strconcat(OpcodeStr, "\t$dst"),
512              Pattern> {
513  bits<4> op;
514  bits<1> BPFSrc;
515  bits<4> dst;
516  bits<32> imm;
517
518  let Inst{63-60} = op;
519  let Inst{59} = BPFSrc;
520  let Inst{51-48} = dst;
521  let Inst{31-0} = imm;
522
523  let op = 0xd;     // BPF_END
524  let BPFSrc = 1;   // BPF_TO_BE (TODO: use BPF_TO_LE for big-endian target)
525  let BPFClass = 4; // BPF_ALU
526  let imm = SizeOp;
527}
528
529let Constraints = "$dst = $src" in {
530def BSWAP16 : BSWAP<16, "bswap16", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
531def BSWAP32 : BSWAP<32, "bswap32", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
532def BSWAP64 : BSWAP<64, "bswap64", [(set GPR:$dst, (bswap GPR:$src))]>;
533}
534
535let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
536    hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
537class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
538    : InstBPF<(outs), (ins GPR:$skb, i64imm:$imm),
539              "r0 = *("#OpcodeStr#" *)skb[$imm]",
540              [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
541  bits<3> mode;
542  bits<2> size;
543  bits<32> imm;
544
545  let Inst{63-61} = mode;
546  let Inst{60-59} = size;
547  let Inst{31-0} = imm;
548
549  let mode = 1;     // BPF_ABS
550  let size = SizeOp;
551  let BPFClass = 0; // BPF_LD
552}
553
554class LOAD_IND<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
555    : InstBPF<(outs), (ins GPR:$skb, GPR:$val),
556              "r0 = *("#OpcodeStr#" *)skb[$val]",
557              [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
558  bits<3> mode;
559  bits<2> size;
560  bits<4> val;
561
562  let Inst{63-61} = mode;
563  let Inst{60-59} = size;
564  let Inst{55-52} = val;
565
566  let mode = 2;     // BPF_IND
567  let size = SizeOp;
568  let BPFClass = 0; // BPF_LD
569}
570}
571
572def LD_ABS_B : LOAD_ABS<2, "u8", int_bpf_load_byte>;
573def LD_ABS_H : LOAD_ABS<1, "u16", int_bpf_load_half>;
574def LD_ABS_W : LOAD_ABS<0, "u32", int_bpf_load_word>;
575
576def LD_IND_B : LOAD_IND<2, "u8", int_bpf_load_byte>;
577def LD_IND_H : LOAD_IND<1, "u16", int_bpf_load_half>;
578def LD_IND_W : LOAD_IND<0, "u32", int_bpf_load_word>;
579