1 //===-- AVRInstPrinter.cpp - Convert AVR MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an AVR MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AVRInstPrinter.h"
14 
15 #include "MCTargetDesc/AVRMCTargetDesc.h"
16 
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/FormattedStream.h"
24 
25 #include <cstring>
26 
27 #define DEBUG_TYPE "asm-printer"
28 
29 namespace llvm {
30 
31 // Include the auto-generated portion of the assembly writer.
32 #define PRINT_ALIAS_INSTR
33 #include "AVRGenAsmWriter.inc"
34 
35 void AVRInstPrinter::printInst(const MCInst *MI, uint64_t Address,
36                                StringRef Annot, const MCSubtargetInfo &STI,
37                                raw_ostream &O) {
38   unsigned Opcode = MI->getOpcode();
39 
40   // First handle load and store instructions with postinc or predec
41   // of the form "ld reg, X+".
42   // TODO: We should be able to rewrite this using TableGen data.
43   switch (Opcode) {
44   case AVR::LDRdPtr:
45   case AVR::LDRdPtrPi:
46   case AVR::LDRdPtrPd:
47     O << "\tld\t";
48     printOperand(MI, 0, O);
49     O << ", ";
50 
51     if (Opcode == AVR::LDRdPtrPd)
52       O << '-';
53 
54     printOperand(MI, 1, O);
55 
56     if (Opcode == AVR::LDRdPtrPi)
57       O << '+';
58     break;
59   case AVR::STPtrRr:
60     O << "\tst\t";
61     printOperand(MI, 0, O);
62     O << ", ";
63     printOperand(MI, 1, O);
64     break;
65   case AVR::STPtrPiRr:
66   case AVR::STPtrPdRr:
67     O << "\tst\t";
68 
69     if (Opcode == AVR::STPtrPdRr)
70       O << '-';
71 
72     printOperand(MI, 1, O);
73 
74     if (Opcode == AVR::STPtrPiRr)
75       O << '+';
76 
77     O << ", ";
78     printOperand(MI, 2, O);
79     break;
80   default:
81     if (!printAliasInstr(MI, Address, O))
82       printInstruction(MI, Address, O);
83 
84     printAnnotation(O, Annot);
85     break;
86   }
87 }
88 
89 const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum,
90                                                   MCRegisterInfo const &MRI) {
91   // GCC prints register pairs by just printing the lower register
92   // If the register contains a subregister, print it instead
93   if (MRI.getNumSubRegIndices() > 0) {
94     unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo);
95     RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum;
96   }
97 
98   return getRegisterName(RegNum);
99 }
100 
101 void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
102                                   raw_ostream &O) {
103   if (OpNo >= MI->size()) {
104     // Not all operands are correctly disassembled at the moment. This means
105     // that some machine instructions won't have all the necessary operands
106     // set.
107     // To avoid asserting, print <unknown> instead until the necessary support
108     // has been implemented.
109     O << "<unknown>";
110     return;
111   }
112 
113   const MCOperand &Op = MI->getOperand(OpNo);
114   const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).OpInfo[OpNo];
115 
116   if (Op.isReg()) {
117     bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) ||
118                     (MOI.RegClass == AVR::PTRDISPREGSRegClassID) ||
119                     (MOI.RegClass == AVR::ZREGRegClassID);
120 
121     if (isPtrReg) {
122       O << getRegisterName(Op.getReg(), AVR::ptr);
123     } else {
124       O << getPrettyRegisterName(Op.getReg(), MRI);
125     }
126   } else if (Op.isImm()) {
127     O << Op.getImm();
128   } else {
129     assert(Op.isExpr() && "Unknown operand kind in printOperand");
130     O << *Op.getExpr();
131   }
132 }
133 
134 /// This is used to print an immediate value that ends up
135 /// being encoded as a pc-relative value.
136 void AVRInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
137                                    raw_ostream &O) {
138   if (OpNo >= MI->size()) {
139     // Not all operands are correctly disassembled at the moment. This means
140     // that some machine instructions won't have all the necessary operands
141     // set.
142     // To avoid asserting, print <unknown> instead until the necessary support
143     // has been implemented.
144     O << "<unknown>";
145     return;
146   }
147 
148   const MCOperand &Op = MI->getOperand(OpNo);
149 
150   if (Op.isImm()) {
151     int64_t Imm = Op.getImm();
152     O << '.';
153 
154     // Print a position sign if needed.
155     // Negative values have their sign printed automatically.
156     if (Imm >= 0)
157       O << '+';
158 
159     O << Imm;
160   } else {
161     assert(Op.isExpr() && "Unknown pcrel immediate operand");
162     O << *Op.getExpr();
163   }
164 }
165 
166 void AVRInstPrinter::printMemri(const MCInst *MI, unsigned OpNo,
167                                 raw_ostream &O) {
168   assert(MI->getOperand(OpNo).isReg() && "Expected a register for the first operand");
169 
170   const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
171 
172   // Print the register.
173   printOperand(MI, OpNo, O);
174 
175   // Print the {+,-}offset.
176   if (OffsetOp.isImm()) {
177     int64_t Offset = OffsetOp.getImm();
178 
179     if (Offset >= 0)
180       O << '+';
181 
182     O << Offset;
183   } else if (OffsetOp.isExpr()) {
184     O << *OffsetOp.getExpr();
185   } else {
186     llvm_unreachable("unknown type for offset");
187   }
188 }
189 
190 } // end of namespace llvm
191 
192