1 //===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the AVR specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRTargetMachine.h"
15 
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/TargetPassConfig.h"
18 #include "llvm/IR/Module.h"
19 #include "llvm/IR/LegacyPassManager.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 #include "AVRTargetObjectFile.h"
23 #include "AVR.h"
24 #include "MCTargetDesc/AVRMCTargetDesc.h"
25 
26 namespace llvm {
27 
28 static const char *AVRDataLayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-n8";
29 
30 /// Processes a CPU name.
31 static StringRef getCPU(StringRef CPU) {
32   if (CPU.empty() || CPU == "generic") {
33     return "avr2";
34   }
35 
36   return CPU;
37 }
38 
39 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
40   return RM.hasValue() ? *RM : Reloc::Static;
41 }
42 
43 AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
44                                    StringRef CPU, StringRef FS,
45                                    const TargetOptions &Options,
46                                    Optional<Reloc::Model> RM, CodeModel::Model CM,
47                                    CodeGenOpt::Level OL)
48     : LLVMTargetMachine(
49           T, AVRDataLayout, TT,
50           getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), CM, OL),
51       SubTarget(TT, getCPU(CPU), FS, *this) {
52   this->TLOF = make_unique<AVRTargetObjectFile>();
53   initAsmInfo();
54 }
55 
56 namespace {
57 /// AVR Code Generator Pass Configuration Options.
58 class AVRPassConfig : public TargetPassConfig {
59 public:
60   AVRPassConfig(AVRTargetMachine *TM, PassManagerBase &PM)
61       : TargetPassConfig(TM, PM) {}
62 
63   AVRTargetMachine &getAVRTargetMachine() const {
64     return getTM<AVRTargetMachine>();
65   }
66 
67   bool addInstSelector() override;
68   void addPreSched2() override;
69   void addPreRegAlloc() override;
70   void addPreEmitPass() override;
71 };
72 } // namespace
73 
74 TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
75   return new AVRPassConfig(this, PM);
76 }
77 
78 extern "C" void LLVMInitializeAVRTarget() {
79   // Register the target.
80   RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
81 }
82 
83 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
84   return &SubTarget;
85 }
86 
87 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
88   return &SubTarget;
89 }
90 
91 //===----------------------------------------------------------------------===//
92 // Pass Pipeline Configuration
93 //===----------------------------------------------------------------------===//
94 
95 bool AVRPassConfig::addInstSelector() {
96   return false;
97 }
98 
99 void AVRPassConfig::addPreRegAlloc() {
100 }
101 
102 void AVRPassConfig::addPreSched2() { }
103 
104 void AVRPassConfig::addPreEmitPass() {
105 }
106 
107 } // end of namespace llvm
108